CN114883346A - Array substrate, manufacturing method thereof and display panel - Google Patents
Array substrate, manufacturing method thereof and display panel Download PDFInfo
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- CN114883346A CN114883346A CN202210488642.5A CN202210488642A CN114883346A CN 114883346 A CN114883346 A CN 114883346A CN 202210488642 A CN202210488642 A CN 202210488642A CN 114883346 A CN114883346 A CN 114883346A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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Abstract
The invention provides an array substrate, a manufacturing method thereof and a display panel; the array substrate comprises a pixel driving circuit positioned in a display area and a peripheral driving circuit positioned in a peripheral circuit area on the peripheral side of the display area, wherein the peripheral driving circuit comprises a first thin film transistor, the pixel driving circuit comprises a second thin film transistor, and the mobility of a first oxide semiconductor pattern of the first thin film transistor is different from that of a second oxide semiconductor pattern of the second thin film transistor. According to the embodiment of the invention, based on the difference of the display area and the peripheral circuit area on the characteristic requirements of the thin film transistor, the requirements of the display panel on high mobility and stability are met by adopting the oxide semiconductor materials with different mobilities for the semiconductor patterns of the thin film transistor in the peripheral circuit area and the thin film transistor in the display area.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate and a display panel.
Background
Currently, oxide semiconductor materials are widely used in the field of semiconductor display technology, and have characteristics of high mobility and Low leakage current compared to amorphous Silicon (a-Si), and can achieve large area uniformity and lower manufacturing cost compared to Low Temperature Poly-Silicon (LTPS), and thus, oxide semiconductors are widely used as semiconductor layers of Thin Film Transistors (TFTs) in realizing large and medium sized display panels.
In order to further improve the quality of the display panel, reduce the panel frame (border) and realize the narrow frame display, a conventional method is to increase the driving current capability of the peripheral driving circuit to reduce the size of the driving circuit, and an Oxide semiconductor material (e.g., Indium Gallium Tin Oxide (IGTO) material with higher mobility, which is about 20-30 cm in mobility, is used 2 V.s) can realize higher mobility, thereby compressing the size of the TFT and achieving the purpose of reducing the size of a driving circuit; it follows that high mobility Oxide materials have a mobility of 10cm compared to low mobility Oxide semiconductor materials (e.g., Indium Gallium Zinc Oxide (IGZO) materials) 2 V · s), device stability may be reduced, resulting in failure of the TFT.
Therefore, the conventional display panel has a technical problem that high mobility and stability cannot be simultaneously achieved, and an improvement is required.
Disclosure of Invention
The invention provides an array substrate, a manufacturing method thereof and a display panel, which aim to solve the technical problem that the existing display panel cannot simultaneously give consideration to high mobility and stability.
In order to solve the above problems, the technical scheme provided by the invention is as follows:
the embodiment of the invention provides an array substrate, which comprises a display area and a peripheral circuit area positioned on the peripheral side of the display area, wherein the array substrate comprises a peripheral driving circuit positioned in the peripheral circuit area and a pixel driving circuit positioned in the display area, the peripheral driving circuit comprises a first thin film transistor, the pixel driving circuit comprises a second thin film transistor, and the mobility of a first oxide semiconductor pattern of the first thin film transistor is different from that of a second oxide semiconductor pattern of the second thin film transistor.
In the array substrate provided by the embodiment of the invention, the mobility of the first oxide semiconductor pattern is higher than that of the second oxide semiconductor pattern.
In the array substrate provided by the embodiment of the invention, the material of the first oxide semiconductor pattern includes indium gallium tin oxide, and the material of the second oxide semiconductor pattern includes indium gallium zinc oxide.
In the array substrate provided in the embodiments of the present invention, the array substrate includes a substrate, a first oxide semiconductor layer over the substrate, the first oxide semiconductor layer including the first oxide semiconductor pattern, a second gate insulating layer over the first oxide semiconductor layer, and a second oxide semiconductor layer over the second gate insulating layer, the second oxide semiconductor layer including the second oxide semiconductor pattern.
In the array substrate provided in the embodiment of the present invention, the array substrate further includes a second metal layer located above the second insulating layer, the second metal layer includes a first source and a first drain of the first thin film transistor, and the first source and the first drain are electrically connected to the first oxide semiconductor pattern through a via hole of the second gate insulating layer.
In the array substrate provided in the embodiment of the present invention, the second metal layer further includes a second source electrode and a second drain electrode of the second thin film transistor, and the second source electrode and the second drain electrode are in direct contact with the second oxide semiconductor pattern.
In the array substrate provided in the embodiment of the present invention, the array substrate further includes a first metal layer located on the substrate and a first gate insulating layer located on the first metal layer, the first oxide semiconductor layer is located on the first gate insulating layer, and the first metal layer includes a gate electrode of the first thin film transistor.
In the array substrate provided by the embodiment of the invention, the first metal layer further includes a gate of the second thin film transistor.
Further, an embodiment of the present invention further provides a manufacturing method of an array substrate, where the array substrate includes a peripheral driving circuit in the peripheral circuit area and a pixel driving circuit in the display area, the peripheral driving circuit includes a first thin film transistor, the pixel driving circuit includes a second thin film transistor, and mobility of a first oxide semiconductor pattern of the first thin film transistor is different from mobility of a second oxide semiconductor pattern of the second thin film transistor; the manufacturing method comprises the following steps:
providing a substrate;
forming a first metal layer on the substrate, and patterning the first metal layer to form a gate of the first thin film transistor and a gate of the second thin film transistor;
forming a first gate insulating layer on the first metal layer;
forming a first oxide semiconductor layer on the first gate insulating layer, patterning the first oxide semiconductor layer to form the first oxide semiconductor pattern;
forming a second gate insulating layer over the first oxide semiconductor pattern;
forming a second oxide semiconductor layer over the second gate insulating layer, patterning the second oxide semiconductor layer to form the second oxide semiconductor pattern;
patterning the second gate insulating layer to form a via hole;
depositing a second metal layer over the second gate insulating layer and the second oxide semiconductor pattern, and patterning the second metal layer to form a first source electrode and a first drain electrode of the first thin film transistor and a second source electrode and a second drain electrode of the second thin film transistor.
Further, an embodiment of the present invention further provides a display panel, including the array substrate according to any one of the embodiments or the array substrate manufactured by the method according to the embodiment.
The invention has the beneficial effects that: the invention provides an array substrate, a manufacturing method thereof and a display panel, wherein the array substrate comprises a pixel driving circuit positioned in a display area and a peripheral driving circuit positioned in a peripheral circuit area on the peripheral side of the display area, the peripheral driving circuit comprises a first thin film transistor, the pixel driving circuit comprises a second thin film transistor, and the mobility of a first oxide semiconductor pattern of the first thin film transistor is different from that of a second oxide semiconductor pattern of the second thin film transistor. According to the embodiment of the invention, based on the difference of the display area and the peripheral circuit area on the characteristic requirements of the thin film transistor, the requirements of the display panel on high mobility and stability are met by adopting the oxide semiconductor materials with different mobilities for the semiconductor patterns of the thin film transistor in the peripheral circuit area and the thin film transistor in the display area.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 to 8 are schematic cross-sectional views of an array substrate according to an embodiment of the invention;
fig. 9 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In this application, the word "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the invention. In the following description, details are set forth for the purpose of explanation. It will be apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and processes are not shown in detail to avoid obscuring the description of the invention with unnecessary detail. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Aiming at the technical problem that the existing display panel cannot simultaneously give consideration to high mobility and stability, the embodiment of the invention can be relieved.
In order to alleviate the above problem, the present application provides an array substrate, and in particular, the array substrate provided by the present application includes a pixel driving circuit located in a display region and a peripheral driving circuit located in a peripheral circuit region on a peripheral side of the display region, the peripheral driving circuit includes a first thin film transistor, the pixel driving circuit includes a second thin film transistor, and mobility of a first oxide semiconductor pattern of the first thin film transistor and mobility of a second oxide semiconductor pattern of the second thin film transistor are different.
In an embodiment, please refer to fig. 8, and fig. 8 is a schematic cross-sectional view of an array substrate according to an embodiment of the present invention. As shown in fig. 8, an array substrate according to an embodiment of the present invention includes a display region 101 and a peripheral circuit region 102 located on a peripheral side of the display region 101, the array substrate includes a peripheral driver circuit located in the peripheral circuit region 102 and a pixel driver circuit located in the display region 101, the peripheral driver circuit includes a first thin film transistor, the pixel driver circuit includes a second thin film transistor, and mobility of a first oxide semiconductor pattern 10 of the first thin film transistor and mobility of a second oxide semiconductor pattern 11 of the second thin film transistor are different.
That is, the present embodiment provides an array substrate, which includes a pixel driving circuit in a display region and a peripheral driving circuit in a peripheral circuit region on a peripheral side of the display region, wherein the peripheral driving circuit includes a first thin film transistor, the pixel driving circuit includes a second thin film transistor, and mobility of a first oxide semiconductor pattern of the first thin film transistor is different from mobility of a second oxide semiconductor pattern of the second thin film transistor. According to the embodiment of the invention, based on the difference of the display area and the peripheral circuit area on the characteristic requirements of the thin film transistor, the requirements of the display panel on high mobility and stability are met by adopting the oxide semiconductor materials with different mobilities for the semiconductor patterns of the thin film transistors in the peripheral circuit area and the display area, meanwhile, the thin film transistor with the etching barrier layer structure is adopted in the peripheral circuit area, the problem of stability reduction caused by the high mobility semiconductor can be solved, the size of the thin film transistor of the peripheral drive circuit can be reduced, the design space is further saved, the frame of the display panel is reduced, and the comprehensive performance of the display panel is improved.
In one embodiment, the mobility of the first oxide semiconductor pattern 10 is higher than that of the second oxide semiconductor pattern 11. Specifically, in the array substrate, the characteristic requirements of the peripheral circuit region and the display region on the thin film transistors are different, and the peripheral circuit region requires the thin film transistors with higher mobility, so in the application, oxide semiconductor materials with different mobilities are adopted for the semiconductor patterns of the thin film transistors in the peripheral circuit region and the display region, so that the mobility of the first oxide semiconductor pattern of the first thin film transistor in the peripheral circuit region is higher than that of the second oxide semiconductor pattern of the second thin film transistor in the display region, and meanwhile, the first thin film transistor in the peripheral circuit region adopts an etching barrier layer structure during preparation, so that the stability reduction caused by high mobility can be improved, the size reduction of the first thin film transistor in the peripheral drive circuit can be realized, and the narrow frame of the display panel can be realized.
Preferably, the mobility of the first oxide semiconductor pattern 10 is about 20 to 30cm 2 V.s, the mobility of the second oxide semiconductor pattern 11 is about 10cm 2 /V·s。
In one embodiment, the material of the first oxide semiconductor pattern 10 includes indium gallium tin oxide, and the material of the second oxide semiconductor pattern 11 includes indium gallium zinc oxide. The indium gallium tin oxide semiconductor material has higher mobility, and can meet the requirement of high mobility of the first oxide semiconductor pattern; specifically, the mobility of the InGaSn oxide material is about 20-30 cm 2 The mobility of the/V.s, indium gallium zinc oxide material is about 10cm 2 /V·s。
In one embodiment, the array substrate includes a substrate 12, a first oxide semiconductor layer including the first oxide semiconductor pattern 10, over the substrate 12, a second gate insulating layer 14 over the first oxide semiconductor layer, and a second oxide semiconductor layer including the second oxide semiconductor pattern 11, over the second gate insulating layer 14, as shown in fig. 8. Specifically, the first oxide semiconductor pattern 10 and the second oxide semiconductor pattern 11 are located at different film layers.
It should be noted that the first thin film transistor is fabricated by using an etching stop layer structure, and the second thin film transistor is fabricated by using a conventional back channel etching structure.
In one embodiment, as shown in fig. 8, the array substrate further includes a second metal layer located above the second gate insulating layer 14, the second metal layer includes a first source 15 and a first drain 16 of the first thin film transistor, and the first source 15 and the first drain 16 are electrically connected to the first oxide semiconductor pattern 10 through a via of the second gate insulating layer 14. In the present embodiment, the second gate insulating layer 14 is formed as an etch stop layer to prevent the sensitive first oxide semiconductor pattern 10 from being affected when the second metal layer is patterned, considering that the first oxide semiconductor pattern 10 has higher mobility than the second oxide semiconductor pattern 11 and is more easily affected by the process.
In one embodiment, as shown in fig. 8, the second metal layer further includes a second source electrode 17 and a second drain electrode 18 of the second thin film transistor, and the second source electrode 17 and the second drain electrode 18 are in direct contact with the second oxide semiconductor pattern 11. In the present embodiment, since the second oxide semiconductor pattern 11 has a lower mobility than the first oxide semiconductor pattern 10 and is less affected by the process than the first oxide semiconductor pattern 10, the second source electrode 17 and the second drain electrode 18 are in direct contact with the second oxide semiconductor pattern 11 in order to simplify the process. By designing the etch stop layer for the more sensitive first oxide semiconductor pattern 10 and not for the second oxide semiconductor pattern 11 with relatively low mobility, the design of designing the etch stop layer for all oxide semiconductors in the prior art is broken through, so that the mobility performance is ensured, and the process is simplified.
In one embodiment, as shown in fig. 8, the array substrate further includes a first metal layer on the substrate 12 and a first gate insulating layer 13 on the first metal layer, the first oxide semiconductor layer is on the first gate insulating layer 13, and the first metal layer includes a gate electrode 19 of the first thin film transistor.
In one embodiment, as shown in fig. 8, the first metal layer further includes a gate electrode 20 of the second thin film transistor; the grid electrodes of two thin film transistors are designed on the same layer, so that the process complexity can be reduced.
The embodiment of the present application further provides a manufacturing method of an array substrate, where the array substrate includes a peripheral driving circuit in the peripheral circuit region and a pixel driving circuit in the display region, the peripheral driving circuit includes a first thin film transistor, the pixel driving circuit includes a second thin film transistor, and mobility of a first oxide semiconductor pattern of the first thin film transistor is different from mobility of a second oxide semiconductor pattern of the second thin film transistor; the manufacturing method comprises the following steps:
providing a substrate;
forming a first metal layer on the substrate, and patterning the first metal layer to form a gate of the first thin film transistor and a gate of the second thin film transistor;
forming a first gate insulating layer on the first metal layer;
forming a first oxide semiconductor layer on the first gate insulating layer, patterning the first oxide semiconductor layer to form the first oxide semiconductor pattern;
forming a second gate insulating layer over the first oxide semiconductor pattern;
forming a second oxide semiconductor layer over the second gate insulating layer, patterning the second oxide semiconductor layer to form the second oxide semiconductor pattern;
patterning the second gate insulating layer to form a via hole;
depositing a second metal layer over the second gate insulating layer and the second oxide semiconductor pattern, and patterning the second metal layer to form a first source electrode and a first drain electrode of the first thin film transistor and a second source electrode and a second drain electrode of the second thin film transistor.
A method for manufacturing an array substrate according to an embodiment of the present application will now be described with reference to fig. 1 to 8 and 9.
As shown in fig. 1 to 8 and 9, the method for manufacturing an array substrate provided by the present application includes the following steps:
and step S1, cleaning the substrate.
Providing a glass substrate as a substrate, and cleaning the glass substrate.
Step S2, depositing a first metal layer, and performing a patterned etching process to form a gate pattern.
Specifically, as shown in fig. 1, a first metal layer is deposited on the cleaned glass substrate 12, wherein the first metal layer has a double-layer structure (not shown in the figure), wherein the first layer may be a transition metal material, such as molybdenum (Mo), titanium (Ti), tungsten (W), chromium (Cr), nickel (Ni), and an alloy material thereof, and has a thickness of 50-500 angstroms, and the second layer may be a metal material, such as copper (Cu), aluminum (Al), and has a thickness of 2000-5000 angstroms;
further, the first metal layer is patterned to form a gate electrode 19 of the first thin film transistor in the peripheral circuit region 102 and a gate electrode 20 of the second thin film transistor in the display region 101.
Step S3, depositing a first gate insulation layer.
Specifically, as shown in fig. 2, a first gate insulating layer 13 is deposited over the gate electrode 19 of the first thin film transistor and the gate electrode 20 of the second thin film transistor, and the first gate insulating layer 13 may cover not only the upper surfaces of the gate electrode 19 of the first thin film transistor and the gate electrode 20 of the second thin film transistor but also the side surfaces of the gate electrode 19 of the first thin film transistor and the gate electrode 20 of the second thin film transistor; the material of the first gate insulating layer 13 may be silicon dioxide (SiO2) with a thickness of 1000-4000 angstroms.
Step S4, depositing a first oxide semiconductor layer, and pattern etching to form a first oxide semiconductor pattern.
Specifically, as shown in fig. 3, a first oxide semiconductor layer is deposited on the first gate insulating layer 13, and the material of the first oxide semiconductor layer may be a high-mobility oxide semiconductor material, such as indium-gallium-tin-oxide, with a thickness of 100-;
further, patterning the first oxide semiconductor layer for forming the first oxide semiconductor pattern 10;
note that the first oxide semiconductor pattern 10 is located in the peripheral circuit region 102 of the array substrate.
Step S5, a second gate insulating layer (etching stopper layer) is formed.
Specifically, as shown in fig. 4, a second gate insulating layer 14 is deposited over the first oxide semiconductor pattern 10, and the second gate insulating layer 14 may cover not only the upper surface of the first oxide semiconductor pattern 10 but also the side surface of the first oxide semiconductor pattern 10; the material of the second gate insulating layer 14 may be silicon dioxide (SiO2) with a thickness of 1000-.
Note that the second gate insulating layer 14 may also be referred to as an etch stopper layer.
Step S6, depositing a second oxide semiconductor layer, and pattern etching to form a second oxide semiconductor pattern.
Specifically, as shown in fig. 5, a second oxide semiconductor layer is deposited on the second gate insulating layer 14, and the material of the second oxide semiconductor layer may be an oxide semiconductor material, such as indium gallium zinc oxide, with a thickness of 100-;
further, patterning the second oxide semiconductor layer for forming the second oxide semiconductor pattern 11;
it should be noted that the second oxide semiconductor pattern 11 is located in the display region 101 of the array substrate.
Step S7, the second gate insulating layer is patterned to form an opening.
Specifically, as shown in fig. 6, the second gate insulating layer 14 is etched by a photolithography process to define the first oxide semiconductor pattern 10 and contact holes for the source and drain of the first thin film transistor.
And step S8, depositing a second metal layer, and forming a source and drain electrode pattern by patterning and etching.
Specifically, as shown in fig. 7, a second metal layer is deposited on the second oxide semiconductor pattern 11, and the second metal layer not only covers the upper surface of the second oxide semiconductor pattern 11, but also covers the side surface of the second oxide semiconductor pattern 11, the second gate insulating layer 14 region not covered by the second oxide semiconductor pattern, and the via hole region on the second gate insulating layer 14; the second metal layer has a double-layer structure (not shown), wherein the first layer may be a transition metal material, such as molybdenum (Mo), titanium (Ti), tungsten (W), chromium (Cr), nickel (Ni), and alloys thereof, or a conductive oxide material, such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Aluminum Zinc Oxide (AZO), with a thickness of 50-500 angstroms; the second layer is made of metal material, such as copper (Cu) and aluminum (Al), with a thickness of 2000-10000A, and the first source 15 and the first drain 16 of the first TFT and the second source 17 and the second drain 18 of the second TFT are defined by using the same mask.
Step S9, a passivation layer (protective layer) is produced.
Specifically, as shown in fig. 8, a passivation layer 21 is deposited on the second metal layer, where the passivation layer 21 is a silicon dioxide thin film with a thickness of 1000-.
And finishing the manufacture of the array substrate.
According to the above description, in the manufacturing method of the array substrate provided by the present application, the mobility of the material used for the semiconductor patterns of the thin film transistors in the peripheral circuit region and the display region is different, so as to meet the requirements of different regions on the characteristics of the thin film transistors, and meanwhile, the thin film transistor with the etching barrier layer structure is used in the peripheral circuit region, which not only can improve the problem of stability reduction caused by a high mobility semiconductor, but also can reduce the size of the thin film transistor of the peripheral driving circuit, thereby realizing a narrow frame of the display panel.
Correspondingly, the embodiment of the invention also provides a display panel, and the display panel comprises the array substrate provided by the invention or the array substrate manufactured according to the method provided by the invention. The display panel can be applied to electronic terminals with display functions, such as fixed terminals like desktop computers and televisions, mobile terminals like smart phones and tablet computers, wearable devices like smart glasses and telephone watches, and the like.
According to the above embodiments:
the invention provides an array substrate, a manufacturing method and a display panel, wherein the array substrate comprises a pixel driving circuit positioned in a display area and a peripheral driving circuit positioned in a peripheral circuit area on the peripheral side of the display area, the peripheral driving circuit comprises a first thin film transistor, the pixel driving circuit comprises a second thin film transistor, and the mobility of a first oxide semiconductor pattern of the first thin film transistor is different from that of a second oxide semiconductor pattern of the second thin film transistor. According to the embodiment of the invention, based on the difference of the display area and the peripheral circuit area on the characteristic requirements of the thin film transistor, the requirements of the display panel on high mobility and stability are met by adopting the oxide semiconductor materials with different mobilities for the semiconductor patterns of the thin film transistors in the peripheral circuit area and the display area, meanwhile, the thin film transistor with the etching barrier layer structure is adopted in the peripheral circuit area, the problem of stability reduction caused by the high mobility semiconductor can be solved, the size of the thin film transistor of the peripheral drive circuit can be reduced, the design space is further saved, the frame of the display panel is reduced, and the comprehensive performance of the display panel is improved.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (10)
1. An array substrate comprises a display area and a peripheral circuit area located on the periphery side of the display area, and is characterized in that the array substrate comprises a peripheral driving circuit located in the peripheral circuit area and a pixel driving circuit located in the display area, the peripheral driving circuit comprises a first thin film transistor, the pixel driving circuit comprises a second thin film transistor, and mobility of a first oxide semiconductor pattern of the first thin film transistor is different from mobility of a second oxide semiconductor pattern of the second thin film transistor.
2. The array substrate of claim 1, wherein the first oxide semiconductor pattern has a higher mobility than the second oxide semiconductor pattern.
3. The array substrate of claim 2, wherein the material of the first oxide semiconductor pattern comprises indium gallium tin oxide, and the material of the second oxide semiconductor pattern comprises indium gallium zinc oxide.
4. The array substrate of claim 2, wherein the array substrate comprises a substrate, a first oxide semiconductor layer over the substrate, the first oxide semiconductor layer comprising the first oxide semiconductor pattern, a second gate insulating layer over the first oxide semiconductor layer, and a second oxide semiconductor layer over the second gate insulating layer, the second oxide semiconductor layer comprising the second oxide semiconductor pattern.
5. The array substrate of claim 4, further comprising a second metal layer over the second insulating layer, the second metal layer comprising a first source and a first drain of the first thin film transistor, the first source and the first drain being electrically connected to the first oxide semiconductor pattern through a via of the second gate insulating layer.
6. The array substrate of claim 5, wherein the second metal layer further comprises a second source electrode and a second drain electrode of the second thin film transistor, the second source electrode and the second drain electrode being in direct contact with the second oxide semiconductor pattern.
7. The array substrate of claim 4, further comprising a first metal layer on the substrate and a first gate insulating layer on the first metal layer, wherein the first oxide semiconductor layer is on the first gate insulating layer, and wherein the first metal layer comprises a gate of the first thin film transistor.
8. The array substrate of claim 7, wherein the first metal layer further comprises a gate of the second thin film transistor.
9. The manufacturing method of the array substrate is characterized in that the array substrate comprises a peripheral driving circuit and a pixel driving circuit, wherein the peripheral driving circuit is located in a peripheral circuit area, the pixel driving circuit is located in a display area, the peripheral driving circuit comprises a first thin film transistor, the pixel driving circuit comprises a second thin film transistor, and the mobility of a first oxide semiconductor pattern of the first thin film transistor is different from that of a second oxide semiconductor pattern of the second thin film transistor; the manufacturing method comprises the following steps:
providing a substrate;
forming a first metal layer on the substrate, and patterning the first metal layer to form a gate of the first thin film transistor and a gate of the second thin film transistor;
forming a first gate insulating layer on the first metal layer;
forming a first oxide semiconductor layer on the first gate insulating layer, patterning the first oxide semiconductor layer to form the first oxide semiconductor pattern;
forming a second gate insulating layer over the first oxide semiconductor pattern;
forming a second oxide semiconductor layer over the second gate insulating layer, patterning the second oxide semiconductor layer to form the second oxide semiconductor pattern;
patterning the second gate insulating layer to form a via hole;
depositing a second metal layer over the second gate insulating layer and the second oxide semiconductor pattern, and patterning the second metal layer to form a first source electrode and a first drain electrode of the first thin film transistor and a second source electrode and a second drain electrode of the second thin film transistor.
10. A display panel comprising the array substrate according to any one of claims 1 to 8 or the array substrate manufactured by the method according to claim 9.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117525090A (en) * | 2024-01-05 | 2024-02-06 | 惠科股份有限公司 | Array substrate preparation method, array substrate, display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117525090A (en) * | 2024-01-05 | 2024-02-06 | 惠科股份有限公司 | Array substrate preparation method, array substrate, display panel and display device |
| CN117525090B (en) * | 2024-01-05 | 2024-05-03 | 惠科股份有限公司 | Array substrate preparation method, array substrate, display panel and display device |
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