CN113192985A - TFT substrate and preparation method thereof, display panel and display device - Google Patents
TFT substrate and preparation method thereof, display panel and display device Download PDFInfo
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
Abstract
The application provides a TFT substrate and a preparation method thereof, a display panel and a display device, wherein the TFT substrate comprises a substrate; the first metal oxide structure and the second metal oxide structure are arranged on the substrate at intervals; the first metal structure is arranged on the first metal oxide structure, and the first metal oxide structure comprises a first conductive structure close to the first metal structure; the second metal structure and the third metal structure are arranged on the second metal oxide structure at intervals, and the second metal oxide structure comprises a second conductive structure close to the second metal structure and a third conductive structure close to the third metal structure; the first gate insulating layer is arranged on the substrate, the first metal structure, the second metal structure, the third metal structure and the second metal oxide structure, wherein the first gate insulating layer is not covered by the first metal structure and the second metal structure. The application can reduce the complexity of the manufacturing process.
Description
Technical Field
The present disclosure relates to display technologies, and particularly to a TFT substrate, a method for manufacturing the TFT substrate, a display panel and a display device.
Background
With the development of Display technology, flat panel Display devices such as Liquid Crystal Displays (LCDs) have advantages of high image quality, power saving, thin body, and wide application range, and thus are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, and desktop computers, and become the mainstream of Display devices. A Thin Film Transistor (TFT) is a main driving element in a display device such as an LCD, and is directly related to the development of a high-performance display device.
Currently, a common hybrid TFT includes a Low Temperature Poly-Silicon (LTPS) TFT and an Indium Gallium Zinc Oxide (IGZO) TFT. When the IGZO TFT adopts a top gate structure, a conductor process is required to be performed on a source/drain contact region to reduce contact resistance. The commonly used method of conductimerization is Ar Plasma bombardment, which creates oxygen vacancies at the surface of the IGZO, thereby increasing the conductivity of the IGZO. In order to perform Ar Plasma bombardment only on the source/drain contact region of IGZO, the gate insulating layer covering the source/drain contact region needs to be etched away to expose the source/drain contact region, which increases the complexity of the manufacturing process.
Disclosure of Invention
The embodiment of the application provides a TFT substrate, a preparation method thereof, a display panel and a display device, and can reduce the complexity of a manufacturing process.
An embodiment of the present application provides a TFT substrate, including:
a substrate base plate;
the first metal oxide structure and the second metal oxide structure are arranged on the substrate at intervals;
a first metal structure disposed on the first metal oxide structure, the first metal oxide structure including a first conductive structure proximate to the first metal structure;
the second metal structure and the third metal structure are arranged on the second metal oxide structure at intervals, and the second metal oxide structure comprises a second conductive structure close to the second metal structure and a third conductive structure close to the third metal structure;
and the first gate insulating layer is arranged on the substrate, the first metal structure, the second metal structure, the third metal structure and the part of the second metal oxide structure which is not covered by the second metal structure and the third metal structure.
In the TFT substrate provided in the embodiments of the present application, the substrate includes:
a glass substrate;
the first shading layer and the second shading layer are arranged on the glass substrate at intervals;
the buffer layer is arranged on the glass substrate, the first shading layer and the second shading layer;
an active layer disposed on the buffer layer, the active layer including a channel region, a source contact region and a drain contact region connected by the channel region;
and the second gate insulating layer is arranged on the buffer layer and the active layer.
In the TFT substrate provided in the embodiment of the present application, the TFT substrate further includes:
the second metal layer is arranged on the first grid insulation layer;
the interlayer dielectric layer is arranged on the first grid electrode insulating layer and the second metal layer;
the first through hole is arranged corresponding to the source contact region and penetrates through the second grid insulation layer, the first grid insulation layer and the interlayer dielectric layer;
the second through hole is arranged corresponding to the drain contact region and penetrates through the second grid insulating layer, the first grid insulating layer and the interlayer dielectric layer;
a third via hole corresponding to the second metal structure and penetrating through the first gate insulating layer and the interlayer dielectric layer;
a fourth via hole corresponding to the third metal structure and penetrating through the first gate insulating layer and the interlayer dielectric layer;
and metal is arranged in the first via hole, the second via hole, the third via hole and the fourth via hole.
In the TFT substrate provided in the embodiment of the present application, the second metal structure includes a first sub-metal structure and a second sub-metal structure disposed on the first sub-metal structure, the first sub-metal structure is made of aluminum, and the second sub-metal structure is made of molybdenum.
The embodiment of the application also provides a display panel, which comprises the TFT substrate in any embodiment of the application.
The embodiment of the application also provides a display device which comprises the display panel in any embodiment of the application.
The embodiment of the present application further provides a method for manufacturing a TFT substrate, including: providing a substrate base plate;
sequentially forming a first metal oxide layer and a first metal layer on the substrate base plate;
etching the first metal layer and the first metal oxide layer to obtain a first metal oxide structure and a second metal oxide structure which are arranged on the substrate at intervals, a first metal structure arranged on the first metal oxide structure, and a second metal structure and a third metal structure which are arranged on the second metal oxide structure at intervals;
annealing the first metal structure, the second metal structure and the third metal structure, so that a part of the first metal oxide structure close to the first metal structure is formed into a first conductive structure, a part of the second metal oxide structure close to the second metal structure is formed into a second conductive structure, and a part of the second metal oxide structure close to the third metal structure is formed into a third conductive structure;
forming a first gate insulating layer on portions of the substrate base plate, the first metal structure, the second metal structure, the third metal structure, and the second metal oxide structure not covered by the second metal structure and the third metal structure.
The method for manufacturing a TFT substrate provided in an embodiment of the present application is characterized in that the etching of the first metal layer and the first metal oxide layer is performed to obtain a first metal oxide structure and a second metal oxide structure that are located on the substrate at an interval, and a first metal structure located on the first metal oxide structure and a second metal structure and a third metal structure that are located on the second metal oxide structure at an interval, and the method includes:
performing patterning processing on the first metal layer to form a first photoresist pattern and a second photoresist pattern on the first metal layer, wherein the second photoresist pattern comprises a first sub-photoresist pattern, a second sub-photoresist pattern and a third sub-photoresist pattern which are connected through the first sub-photoresist pattern;
etching off the parts of the first metal layer and the first metal oxide layer which are not covered by the first photoresist pattern and the second photoresist pattern to obtain a first metal oxide structure and a second metal oxide structure which are arranged on the substrate at intervals, a first metal structure arranged on the first metal oxide structure and a metal structure to be etched arranged on the second metal oxide structure;
removing the first sub-photoresist pattern;
and etching off the part of the metal structure to be etched, which is not covered by the first photoresist pattern, the second sub photoresist pattern and the third sub photoresist pattern, so as to obtain a second metal structure and a third metal structure which are arranged on the second metal oxide structure at intervals.
The method for manufacturing a TFT substrate provided in the embodiments of the present application is characterized in that providing a substrate includes:
providing a glass substrate;
forming a first shading layer and a second shading layer on the glass substrate at intervals;
forming a buffer layer on the glass substrate, the first light-shielding layer and the second light-shielding layer;
forming an active layer on the buffer layer, the active layer including a channel region, a source contact region and a drain contact region connected by the channel region;
forming a second gate insulating layer on the buffer layer and the active layer;
the sequentially forming a first metal oxide layer and a first metal layer on the substrate base plate comprises:
sequentially forming a first metal oxide layer and a first metal layer on the second gate insulating layer;
the forming a first gate insulating layer on portions of the substrate base plate, the first metal structure, the second metal structure, the third metal structure, and the second metal oxide structure not covered by the second metal structure and the third metal structure includes:
forming a first gate insulating layer on portions of the second gate insulating layer, the first metal structure, the second metal structure, the third metal structure, and the second metal oxide structure not covered by the second metal structure and the third metal structure.
In the method for manufacturing a TFT substrate according to an embodiment of the present application, after forming the first gate insulating layer on the second gate insulating layer, the first metal structure, the second metal structure, the third metal structure, and the portion of the second metal oxide structure not covered by the second metal structure and the third metal structure, the method further includes:
forming a second metal layer on the first gate insulating layer;
forming an interlayer dielectric layer on the first gate insulating layer and the second metal layer;
etching the second gate insulating layer, the first gate insulating layer and the interlayer dielectric layer to obtain a first via hole which corresponds to the source electrode contact region and penetrates through the second gate insulating layer, the first gate insulating layer and the interlayer dielectric layer, and a second via hole which corresponds to the drain electrode contact region and penetrates through the second gate insulating layer, the first gate insulating layer and the interlayer dielectric layer;
etching the first gate insulating layer and the interlayer dielectric layer to obtain a third via hole which corresponds to the second metal structure and penetrates through the first gate insulating layer and the interlayer dielectric layer, and a fourth via hole which corresponds to the third metal structure and penetrates through the first gate insulating layer and the interlayer dielectric layer;
depositing metal in the first via, the second via, the third via, and the fourth via.
In the method for manufacturing a TFT substrate according to an embodiment of the present application, the second metal structure includes a first sub-metal structure and a second sub-metal structure located on the first sub-metal structure, the first sub-metal structure is made of aluminum, the second sub-metal structure is made of molybdenum, and the second metal structure is annealed to form a second conductive structure in a portion of the second metal oxide structure close to the second metal structure, including:
and annealing the first sub-metal structure to form aluminum atoms, wherein the aluminum atoms are diffused into the second metal oxide structure to form doping, so that the part of the second metal oxide structure close to the first sub-metal structure is formed into a second conductive structure.
The application provides a TFT base plate, includes: a substrate base plate; the first metal oxide structure and the second metal oxide structure are arranged on the substrate at intervals; a first metal structure disposed on the first metal oxide structure, the first metal oxide structure including a first conductive structure proximate to the first metal structure; the second metal structure and the third metal structure are arranged on the second metal oxide structure at intervals, and the second metal oxide structure comprises a second conductive structure close to the second metal structure and a third conductive structure close to the third metal structure; and the first gate insulating layer is arranged at the parts, which are not covered by the first metal structure and the second metal structure, of the substrate base plate, the first metal structure, the second metal structure, the third metal structure and the second metal oxide structure.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required in the embodiments are briefly described below. The drawings in the following description are only some embodiments of the present application, and it will be obvious to those skilled in the art that other drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a TFT substrate according to an embodiment of the present disclosure;
fig. 2 to fig. 6 are process diagrams corresponding to the respective flows shown in fig. 1 provided in the embodiment of the present application;
fig. 7 to 12 are process diagrams corresponding to steps 1031 to 1034 provided in the embodiment of the present application;
fig. 13 to 17 are process diagrams corresponding to steps 1011 to 1015 according to an embodiment of the present disclosure;
FIG. 18 is a process diagram corresponding to step 1051 and provided in an embodiment of the present application;
fig. 19 to 22 are process diagrams corresponding to steps 10511 to 10515 according to an embodiment of the present application;
fig. 23 is a schematic view of a first structure of a TFT substrate according to an embodiment of the present disclosure;
fig. 24 is a schematic structural diagram of a substrate provided in an embodiment of the present application;
fig. 25 is a schematic view of a second structure of a TFT substrate according to an embodiment of the present disclosure;
fig. 26 is a schematic view of a third structure of a TFT substrate according to an embodiment of the present disclosure;
fig. 27 is a schematic structural diagram of a display panel according to an embodiment of the present application;
fig. 28 is a schematic structural diagram of a display device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a method for manufacturing a TFT substrate according to an embodiment of the present disclosure. The process may include:
As shown in fig. 2, a substrate 10 may be provided.
Therein, as shown in fig. 3, a first metal oxide layer 20 may be formed on the base substrate 10. A first metal layer 30 is formed on the first metal oxide layer 20.
The first metal Oxide layer 20 may be made of Indium Gallium Zinc Oxide (IGZO).
Specifically, the step of forming the first metal layer 30 on the first metal oxide layer 20, where the first metal layer 30 includes a first sub-metal layer and a second sub-metal layer disposed on the first sub-metal layer, may include: a first sub-metal layer is formed on the first metal oxide layer 20, and a second sub-metal layer is formed on the first sub-metal layer. The material from which the first sub-metal layer is made may be aluminum. The material of which the second sub-metal layer is made may be molybdenum.
Referring to fig. 3 and fig. 4, a wet etching process may be performed on the first metal layer 30 and the first metal oxide layer 20 shown in fig. 3 to etch away a portion of the first metal layer 30 and a portion of the first metal oxide layer 20 on the substrate 10, so as to obtain the first metal oxide structure 21 and the second metal oxide structure 22 on the substrate 10 at an interval, and the first metal structure 31 on the first metal oxide structure 21 and the second metal structure 32 and the third metal structure 33 on the second metal oxide structure 22 at an interval, as shown in fig. 4.
Specifically, the wet etching process performed on the first metal layer 30 may include: and carrying out wet etching treatment on the first sub-metal layer and the second sub-metal layer.
The first metal structure 31 includes a third sub-metal structure and a fourth sub-metal structure disposed on the third sub-metal structure, and when wet etching is performed on the first sub-metal layer and the second sub-metal layer, the third sub-metal structure and the fourth sub-metal structure located on the third sub-metal structure can be obtained.
The second metal structure 32 includes a first sub-metal structure and a second sub-metal structure disposed on the first sub-metal structure, and the third metal structure 33 includes a fifth sub-metal structure and a sixth sub-metal structure disposed on the fifth sub-metal structure, and when the first sub-metal layer and the second sub-metal layer are subjected to etching treatment, the first sub-metal structure and the second sub-metal structure disposed on the first sub-metal structure, as well as the fifth sub-metal structure and the sixth sub-metal structure disposed on the fifth sub-metal structure, can also be obtained. The first sub-metal structure and the fifth sub-metal structure are arranged at intervals, and the second sub-metal structure and the sixth sub-metal structure are arranged at intervals.
Referring to fig. 4 and 5, the first metal structure 31, the second metal structure 32, and the third metal structure 33 shown in fig. 4 may be annealed to form the first conductive structure 211, the second conductive structure 221, and the third conductive structure 222 shown in fig. 5.
Specifically, the temperature corresponding to the annealing treatment is 200 ℃ to 400 ℃.
In some embodiments, when the first metal structure 31, the second metal structure 32, and the third metal structure 33 are annealed, the substrate base plate 10, the first metal oxide structure 21, the second metal oxide structure 22, the first metal structure 31, the second metal structure 32, and the third metal structure 33 as shown in fig. 4 may be annealed.
Referring to fig. 5 and 6, a first gate insulating layer 40 shown in fig. 6 may be formed on the substrate 10, the first metal structure 31, the second metal structure 32, the third metal structure 33 and the second metal oxide structure 22 shown in fig. 5, which are not covered by the second metal structure 32 and the third metal structure 33. The thickness of the first gate insulating layer 40 is greater than the total thickness of the first metal oxide structure 21 and the first metal structure 31. The thickness of the first gate insulating layer 40 is greater than the total thickness of the second metal oxide structure 22 and the second metal structure 32. The thickness of the first gate insulating layer 40 is greater than the total thickness of the second metal oxide structure 22 and the third metal structure 33.
The application provides a preparation method of a TFT substrate, which comprises the following steps: providing a substrate base plate; sequentially forming a first metal oxide layer and a first metal layer on the substrate base plate; etching the first metal layer and the first metal oxide layer to obtain a first metal oxide structure and a second metal oxide structure which are arranged on the substrate at intervals, a first metal structure arranged on the first metal oxide structure, and a second metal structure and a third metal structure which are arranged on the second metal oxide structure at intervals; annealing the first metal structure, the second metal structure and the third metal structure, so that a part of the first metal oxide structure close to the first metal structure is formed into a first conductive structure, a part of the second metal oxide structure close to the second metal structure is formed into a second conductive structure, and a part of the second metal oxide structure close to the third metal structure is formed into a third conductive structure; forming a first gate insulating layer on the substrate, the first metal structure, the second metal structure, the third metal structure and the second metal oxide structure, where the portions of the substrate, the first metal structure, the second metal structure, the third metal structure and the second metal oxide structure are not covered by the second metal structure and the third metal structure, so as to finally form the TFT substrate.
In some embodiments, step 103 may comprise:
step 1031, performing a patterning process on the first metal layer 30 to form a first photoresist pattern 51 and a second photoresist pattern 52 on the first metal layer 30, wherein the second photoresist pattern 52 includes a first sub-photoresist pattern 521, a second sub-photoresist pattern 522 and a third sub-photoresist pattern 523 connected by the first sub-photoresist pattern 521.
As shown in fig. 7, after the first metal oxide layer 20 and the first metal layer 30 are sequentially formed on the substrate 10, the first metal layer 30 may be exposed using a Halftone mask to form a first photoresist pattern 51 and a second photoresist pattern 52 on the first metal layer 30. The second photoresist pattern 52 includes a first sub-photoresist pattern 521, a second sub-photoresist pattern 522 and a third sub-photoresist pattern 523 connected by the first sub-photoresist pattern 521.
Specifically, the first, second and third sub-photoresist patterns 51, 522 and 523 have the same thickness. The thickness of the first sub photoresist pattern 521 is less than the thickness of the first, second and third sub photoresist patterns 51, 522 and 523.
Step 1032, etching away the portions of the first metal layer 30 and the first metal oxide layer 20 not covered by the first photoresist pattern 51 and the second photoresist pattern 52, so as to obtain the first metal oxide structure 21 and the second metal oxide structure 22 spaced on the substrate base plate 10, and the first metal structure 31 on the first metal oxide structure 21 and the metal structure to be etched 34 on the second metal oxide structure 22.
Referring to fig. 7 and 8, a wet etching process may be performed on the first metal layer 30 and the first metal oxide layer 20 shown in fig. 7 to etch away the portions of the first metal layer 30 and the first metal oxide layer 20 not covered by the first photoresist pattern 51 and the second photoresist pattern 52, so as to obtain the first metal oxide structure 21 and the second metal oxide structure 22 on the substrate 10 at an interval, and the first metal structure 31 on the first metal oxide structure 21 and the to-be-etched metal structure 34 on the second metal oxide structure 22 shown in fig. 8.
Step 1033, remove the first sub-photoresist pattern 521.
Step 1034, etch away the portions of the metal structure 34 to be etched, which are not covered by the first photoresist pattern 51, the second sub-photoresist pattern 522, and the third sub-photoresist pattern 523, to obtain the second metal structure 32 and the third metal structure 33 spaced apart from the second metal oxide structure 22.
Referring to fig. 8 to 10, the first sub-photoresist pattern 521 shown in fig. 8 may be stripped to remove the first sub-photoresist pattern 521. Wet etching may be performed on the portions of the metal structure 34 to be etched that are not covered by the first photoresist pattern 51, the second sub-photoresist pattern 522, and the third sub-photoresist pattern 523, so as to obtain the second metal structure 32 and the third metal structure 33 spaced apart from each other on the second metal oxide structure 22.
After obtaining the second metal structure 32 and the third metal structure 33 spaced apart on the second metal oxide structure 22, the first photoresist pattern 51, the second sub-photoresist pattern 522, and the third sub-photoresist pattern 523 may be removed.
In some embodiments, referring to fig. 8, 11 and 12, the step of removing the first sub-photoresist pattern 521 may include: the first and second photoresist patterns 51 and 52 shown in fig. 8 are stripped by an Ashing process (Ashing process) to remove portions of the first and second sub photoresist patterns 521 and 522, portions of the third and first sub photoresist patterns 523 and 51, resulting in the third, fourth and fifth sub photoresist patterns 53, 524 and 525 shown in fig. 11. The thicknesses of the removed portions of the first, second and third sub-photoresist patterns 51, 522 and 523 are the same as the thickness of the first sub-photoresist pattern 521. The wet etching process may be performed on the portions of the metal structure 34 to be etched that are not covered by the third photoresist pattern 53, the fourth sub-photoresist pattern 524, and the fifth sub-photoresist pattern 525, so as to obtain the second metal structure 32 and the third metal structure 33 spaced apart from each other on the second metal oxide structure 22.
After obtaining the second metal structure 32 and the third metal structure 33 spaced apart on the second metal oxide structure 22, the third photoresist pattern 53, the fourth sub-photoresist pattern 524, and the fifth sub-photoresist pattern 525 may be removed by using a Striper process. The Striper process is a process of stripping the remaining photoresist.
In some embodiments, step 101 may include:
in step 1011, a glass substrate 11 is provided.
As shown in fig. 13, a glass substrate 11 may be provided.
Step 1012 is to form a first light-shielding layer 12 and a second light-shielding layer 13 on the glass substrate 11 at an interval.
As shown in fig. 14, a first light-shielding layer 12 and a second light-shielding layer 13 may be formed on the glass substrate 11 at an interval.
Step 1013 is to form the buffer layer 14 on the glass substrate 11, the first light-shielding layer 12, and the second light-shielding layer 13.
As shown in fig. 15, a buffer layer 14 may be formed on the glass substrate 11, the first light-shielding layer 12, and the second light-shielding layer 13.
Step 1014, forming an active layer 15 on the buffer layer 14, the active layer 15 including a channel region 151, and a source contact region 152 and a drain contact region 153 connected through the channel region 151.
Referring to fig. 15 and 16, a polysilicon pattern may be formed on the buffer layer 14. The active layer 15 shown in fig. 16 is finally formed by performing annealing at a high temperature by yellow light and phosphorus ion doping, and performing hydrogenation and activation processes to form first and second doped regions at intervals on the polysilicon pattern. The first doped region is the source contact region 152 and the second doped region is the drain contact region 153. The portion of the polysilicon pattern where the first doped region and the second doped region are not formed is the channel region 151. Wherein the first doped region comprises a first heavily doped region (N +) and a first lightly doped region (N-), and the second doped region comprises a second heavily doped region (N +) and a second lightly doped region (N-).
Step 1015, a second gate insulating layer 16 is formed on the buffer layer 14 and the active layer 15.
Here, as shown in fig. 17, a second gate insulating layer 16 may be formed on the buffer layer 14 and the active layer 15.
Specifically, the step of forming the second gate insulating layer 16 on the buffer layer 14 and the active layer 15, where the second gate insulating layer 16 includes a first sub-gate insulating layer and a second sub-gate insulating layer disposed on the first sub-gate insulating layer, may include: forming a first sub-gate insulating layer on the buffer layer 14 and the active layer 15; and forming a second sub-gate insulating layer on the first sub-gate insulating layer. The material for manufacturing the first sub-gate insulating layer is silicon nitride (SiNx). The material for manufacturing the second sub-gate insulating layer is silicon oxide (SiOx).
Step 105 may include:
step 1051 forms a first gate insulation layer 40 on the second gate insulation layer 16, the first metal structure 31, the second metal structure 32, the third metal structure 33, and the portion of the second metal oxide structure 22 not covered by the second metal structure 32 and the third metal structure 33.
As shown in fig. 18, a first gate insulating layer 40 may be formed on the second gate insulating layer 16, the first metal structure 31, the second metal structure 32, the third metal structure 33, and the second metal oxide structure 22, which are not covered by the second metal structure 32 and the third metal structure 33.
Specifically, the first gate insulating layer 40 includes a third sub-gate insulating layer and a fourth sub-gate insulating layer disposed on the third sub-gate insulating layer, and step 1051 may include: forming a third sub-gate insulating layer on the second gate insulating layer 16, the first metal structure 31, the second metal structure 32, the third metal structure 33, and the portion of the second metal oxide structure 22 not covered by the second metal structure 32 and the third metal structure 33; and forming a fourth sub-gate insulating layer on the third sub-gate insulating layer. The material for manufacturing the third sub-gate insulating layer is silicon nitride (SiNx). The fourth sub-gate insulating layer is made of silicon oxide (SiOx).
In some embodiments, after step 1051, it may include:
step 10511 forms a second metal layer 60 on the first gate insulation layer 40.
Wherein, as shown in fig. 19, a second metal layer 60 may be formed on the first gate insulating layer 40. The second metal layer 60 may serve as a gate electrode of the IGZO TFT. The material of which the second metal layer 60 is made may be molybdenum, aluminum, titanium, or an alloy thereof, or a laminate thereof.
Step 10512 forms an interlevel dielectric layer 70 over the first gate insulator layer 40 and the second metal layer 60.
As shown in fig. 20, an interlayer dielectric layer 70 may be formed on the first gate insulating layer 40 and the second metal layer 60.
Step 10513, etching the second gate insulating layer 16, the first gate insulating layer 40, and the interlayer dielectric layer 70 to obtain a first via hole 81 corresponding to the source contact region 152 and penetrating through the second gate insulating layer 16, the first gate insulating layer 40, and the interlayer dielectric layer 70, and a second via hole 82 corresponding to the drain contact region 153 and penetrating through the second gate insulating layer 16, the first gate insulating layer 40, and the interlayer dielectric layer 70.
As shown in fig. 21, the second gate insulating layer 16, the first gate insulating layer 40 and the interlayer dielectric layer 70 may be etched to obtain a first via hole 81 corresponding to the source contact region 152 and penetrating through the second gate insulating layer 16, the first gate insulating layer 40 and the interlayer dielectric layer 70, and a second via hole 82 corresponding to the drain contact region 153 and penetrating through the second gate insulating layer 16, the first gate insulating layer 40 and the interlayer dielectric layer 70.
Step 10514, etching the first gate insulating layer 40 and the interlayer dielectric layer 70 to obtain a third via hole 83 corresponding to the second metal structure 32 and penetrating through the first gate insulating layer 40 and the interlayer dielectric layer 70, and a fourth via hole 84 corresponding to the third metal structure 33 and penetrating through the first gate insulating layer 40 and the interlayer dielectric layer 70.
As shown in fig. 21, the first gate insulating layer 40 and the interlayer dielectric layer 70 may be etched to obtain a third via hole 83 corresponding to the second metal structure 32 and penetrating through the first gate insulating layer 40 and the interlayer dielectric layer 70, and a fourth via hole 84 corresponding to the third metal structure 33 and penetrating through the first gate insulating layer 40 and the interlayer dielectric layer 70.
Step 10515 deposits metal 90 in first via 81, second via 82, third via 83, and fourth via 84.
Referring to fig. 21 and 22, a metal 90 may be deposited in the first via 81, the second via 82, the third via 83, and the fourth via 84 shown in fig. 21, resulting in the structure shown in fig. 22.
In some embodiments, the structure shown in fig. 21 may be HF cleaned, and after cleaning, metal 90 may be deposited in first via 81, second via 82, third via 83, and fourth via 84.
Specifically, the metal 90 may be molybdenum, aluminum, titanium, or an alloy thereof, or a laminate thereof.
In some embodiments, the second metal structure 32 includes a first sub-metal structure and a second sub-metal structure located on the first sub-metal structure, the first sub-metal structure is made of aluminum, the second sub-metal structure is made of molybdenum, and the second metal structure 32 is annealed to form a portion of the second metal oxide structure 22 close to the second metal structure 32 into the second conductive structure 221, including:
annealing the first sub-metal structure to form aluminum atoms, and diffusing the aluminum atoms into the second metal oxide structure 22 to form a dopant, so that a portion of the second metal oxide structure 22 close to the first sub-metal structure is formed as the second conductive structure 221.
In some embodiments, the first metal structure 31 includes a third sub-metal structure and a fourth sub-metal structure located on the third sub-metal structure, the third sub-metal structure is made of aluminum, the fourth sub-metal structure is made of molybdenum, and the annealing process is performed on the first metal structure 31 to form a portion of the first metal oxide structure 21 close to the first metal structure 31 as the first conductive structure 211, including:
annealing the third sub-metal structure to form aluminum atoms, and diffusing the aluminum atoms into the first metal oxide structure 21 to form a dopant, so that a portion of the first metal oxide structure 21 close to the third sub-metal structure is formed as the first conductive structure 211.
In some embodiments, the third metal structure 33 includes a fifth sub-metal structure and a sixth sub-metal structure located on the fifth sub-metal structure, the fifth sub-metal structure is made of aluminum, the sixth sub-metal structure is made of molybdenum, and the annealing process is performed on the third metal structure 33 to form a third conductive structure 222 on a portion of the second metal oxide structure 22 close to the third metal structure 33, including:
annealing the fifth sub-metal structure to form aluminum atoms, the aluminum atoms diffusing into the second metal oxide structure 22 to form a dopant, such that a portion of the second metal oxide structure 22 near the fifth sub-metal structure is formed as the third conductive structure 222.
Wherein the first metal structure 31 and the first metal oxide structure 21 including the first conductive structure 211 constitute the gate of the LTPS TFT. The metal 90 corresponding to the source contact region 152 constitutes the source of the LTPS TFT. The metal 90 corresponding to the drain contact region 153 constitutes the drain of the LTPS TFT. The second metal structure 32 and the portion of the second metal oxide structure 22 corresponding to the second metal structure 32 including the second conductive structure 221 are source contact regions of an IGZO TFT. The third metal structure 33 and the portion of the second metal oxide structure 22 corresponding to the third metal structure 33 that includes the third conductive structure 222 are the drain contact region of the IGZO TFT. The second metal oxide structure 22 also includes a channel region. The channel region connects the source contact region and the drain contact region. The metal 90 corresponding to the second metal structure 32 constitutes the source of the IGZO TFT. The metal 90 corresponding to the third metal structure 33 constitutes a drain of the IGZO TFT. The second metal layer 60 constitutes a gate electrode of the IGZO TFT.
According to the preparation method of the TFT substrate provided by the embodiment of the application, the second conductive structure and the third conductive structure can be respectively formed on the source contact region and the drain contact region of the IGZO TFT in an aluminum atom diffusion mode, namely, oxygen vacancies are formed on the surface of the second metal oxide structure corresponding to the second metal structure and the third metal structure, so that the contact resistance is reduced. The first conductive structure may also be formed on the gate of the LTPS TFT by aluminum atom diffusion, i.e., oxygen vacancies may be generated on the surface of the first metal oxide structure to reduce contact resistance.
Referring to fig. 23, fig. 23 is a schematic view illustrating a first structure of a TTF substrate according to an embodiment of the present application. The TFT substrate 100 may be prepared through steps 101 to 105.
The TFT substrate 100 may include a substrate 10, a first metal oxide structure 21, a second metal oxide structure 22, a first metal structure 31, a first conductive structure 211, a second metal structure 32, a third metal structure 33, a second conductive structure 221, a third conductive structure 222, and a first gate insulating layer 40.
The first metal oxide structure 21 and the second metal oxide structure 22 are disposed at an interval on the substrate 10. The first metal structure 31 is disposed on the first metal oxide structure 21. The first metal oxide structure 21 includes a first conductive structure 211 proximate to the first metal structure 31. The second metal structure 32 and the third metal structure 33 are disposed at an interval on the second metal oxide structure 22. Second metal oxide structure 22 includes second conductive structure 221 adjacent second metal structure 32 and third conductive structure 222 adjacent third metal structure 33. The first gate insulating layer 40 is disposed on the substrate 10, the first metal structure 31, the second metal structure 32, the third metal structure 33, and the second metal oxide structure 22 at a portion not covered by the second metal structure 32 and the third metal structure 33.
The application provides a TFT base plate, includes: a substrate base plate; the first metal oxide structure and the second metal oxide structure are arranged on the substrate at intervals; a first metal structure disposed on the first metal oxide structure, the first metal oxide structure including a first conductive structure proximate to the first metal structure; the second metal structure and the third metal structure are arranged on the second metal oxide structure at intervals, and the second metal oxide structure comprises a second conductive structure close to the second metal structure and a third conductive structure close to the third metal structure; and the first gate insulating layer is arranged at the parts, which are not covered by the first metal structure and the second metal structure, of the substrate base plate, the first metal structure, the second metal structure, the third metal structure and the second metal oxide structure.
Referring to fig. 24, fig. 24 is a schematic structural diagram of the substrate base plate 10 according to the embodiment of the present application. The base substrate 10 may be prepared through steps 1011 to 1015.
The base substrate 10 includes a glass substrate 11, a first light-shielding layer 12, a second light-shielding layer 13, a buffer layer 14, an active layer 15, and a second gate insulating layer 16.
The first light-shielding layer 12 and the second light-shielding layer 13 are disposed on the glass substrate 11 at an interval. The buffer layer 14 is provided on the glass substrate 11, the first light-shielding layer 12, and the second light-shielding layer 13. The active layer 15 is disposed on the buffer layer 14. The active layer 15 includes a channel region 151, and a source contact region 152 and a drain contact region 153 connected through the channel region 151. The second gate insulating layer 16 is disposed on the buffer layer 14 and the active layer 15.
Referring to fig. 25, fig. 25 is a schematic view illustrating a second structure of a TTF substrate according to an embodiment of the present application. The TFT substrate can be prepared by the preparation method of the TFT substrate.
The TFT substrate 100 further includes a second metal layer 60, an interlayer dielectric layer 70, a first via 81, a second via 82, a third via 83, and a fourth via 84, and a metal 90.
The second metal layer 60 is disposed on the first gate insulating layer 40. An interlayer dielectric layer 70 is disposed on the first gate insulating layer 40 and the second metal layer 60. The first via 81 is disposed corresponding to the source contact region 152 and penetrates the second gate insulating layer 16, the first gate insulating layer 40, and the interlayer dielectric layer 70. The second via 82 is disposed corresponding to the drain contact region 153 and penetrates the second gate insulating layer 16, the first gate insulating layer 40, and the interlayer dielectric layer 70. The third via 83 is disposed corresponding to the second metal structure 32 and penetrates the first gate insulating layer 40 and the interlayer dielectric layer 70. The fourth via 84 is disposed corresponding to the third metal structure 33 and penetrates the first gate insulating layer 40 and the interlayer dielectric layer 70. A metal 90 is disposed in the first, second, third and fourth vias 81, 82, 83 and 84.
In some embodiments, as shown in fig. 26, the first metal structure 31 includes a third sub-metal structure 311 and a fourth sub-metal structure 312 disposed on the third sub-metal structure 311, the third sub-metal structure 311 is made of aluminum, and the fourth sub-metal structure 312 is made of molybdenum. The second metal structure 32 includes a first sub-metal structure 321 and a second sub-metal structure 322 disposed on the first sub-metal structure 321, wherein the first sub-metal structure 321 is made of aluminum, and the second sub-metal structure 322 is made of molybdenum. The third metal structure 33 includes a fifth sub-metal structure 331 and a sixth sub-metal structure 332 disposed on the fifth sub-metal structure 331, where the material for fabricating the fifth sub-metal structure is aluminum, and the material for fabricating the sixth sub-metal structure is molybdenum.
Referring to fig. 27, fig. 27 is a schematic structural diagram of a display panel according to an embodiment of the present application.
The display panel 1000 includes the TFT substrate 100 described in the above embodiments. The display panel 1000 further includes a display layer 200 and a cover plate 300. The display layer 200 is disposed on the TFT substrate 100. The cover plate 300 is disposed on the display layer 200. The display layer 200 may be a display layer of an LCD display panel. The display layer 200 may also be a display layer of an OLED display panel.
Referring to fig. 28, fig. 28 is a schematic structural diagram of a display device according to an embodiment of the present application.
The display device 10000 can include a display panel 1000, a control circuit 2000, and a case 3000. It should be noted that the display device 10000 shown in fig. 28 is not limited to the above, and may further include other devices, such as a camera, an antenna structure, a thread unlocking module, and the like.
The display panel 1000 is disposed on the housing 3000.
In some embodiments, the display panel 1000 may be fixed to the housing 3000, and the display panel 1000 and the housing 3000 form a closed space to accommodate the control circuit 2000 and the like.
In some embodiments, the housing 3000 may be made of a flexible material, such as a plastic housing or a silicone housing.
The control circuit 2000 may be a motherboard of the display device 10000, and one, two or more functional components of a battery, an antenna structure, a microphone, a speaker, an earphone interface, a universal serial bus interface, a camera, a distance sensor, an ambient light sensor, a receiver, a processor, and the like may be integrated on the control circuit 2000.
The display panel 1000 is mounted in the housing 3000, and the display panel 1000 is electrically connected to the control circuit 2000 to form a display surface of the display device 10000. The display panel 1000 may include a display area and a non-display area. The display area may be used to display a screen of the display device 10000 or provide a user with touch control. The non-display area may be used to set various functional components.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The TFT substrate, the manufacturing method thereof, the display panel and the display device provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to explain the principles and embodiments of the present application, and the description of the embodiments above is only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (11)
1. A TFT substrate, comprising:
a substrate base plate;
the first metal oxide structure and the second metal oxide structure are arranged on the substrate at intervals;
a first metal structure disposed on the first metal oxide structure, the first metal oxide structure including a first conductive structure proximate to the first metal structure;
the second metal structure and the third metal structure are arranged on the second metal oxide structure at intervals, and the second metal oxide structure comprises a second conductive structure close to the second metal structure and a third conductive structure close to the third metal structure;
and the first gate insulating layer is arranged on the substrate, the first metal structure, the second metal structure, the third metal structure and the part of the second metal oxide structure which is not covered by the second metal structure and the third metal structure.
2. The TFT substrate of claim 1, wherein the base substrate comprises:
a glass substrate;
the first shading layer and the second shading layer are arranged on the glass substrate at intervals;
the buffer layer is arranged on the glass substrate, the first shading layer and the second shading layer;
an active layer disposed on the buffer layer, the active layer including a channel region, a source contact region and a drain contact region connected by the channel region;
and the second gate insulating layer is arranged on the buffer layer and the active layer.
3. The TFT substrate of claim 2, further comprising:
the second metal layer is arranged on the first grid insulation layer;
the interlayer dielectric layer is arranged on the first grid electrode insulating layer and the second metal layer;
the first through hole is arranged corresponding to the source contact region and penetrates through the second grid insulation layer, the first grid insulation layer and the interlayer dielectric layer;
the second through hole is arranged corresponding to the drain contact region and penetrates through the second grid insulating layer, the first grid insulating layer and the interlayer dielectric layer;
a third via hole corresponding to the second metal structure and penetrating through the first gate insulating layer and the interlayer dielectric layer;
a fourth via hole corresponding to the third metal structure and penetrating through the first gate insulating layer and the interlayer dielectric layer;
and metal is arranged in the first via hole, the second via hole, the third via hole and the fourth via hole.
4. The TFT substrate according to any one of claims 1 to 3, wherein the second metal structure comprises a first sub-metal structure and a second sub-metal structure disposed on the first sub-metal structure, the first sub-metal structure is made of aluminum, and the second sub-metal structure is made of molybdenum.
5. A display panel comprising the TFT substrate according to any one of claims 1 to 4.
6. A display device characterized by comprising the display panel according to claim 5.
7. A method for manufacturing a TFT substrate includes:
providing a substrate base plate;
sequentially forming a first metal oxide layer and a first metal layer on the substrate base plate;
etching the first metal layer and the first metal oxide layer to obtain a first metal oxide structure and a second metal oxide structure which are arranged on the substrate at intervals, a first metal structure arranged on the first metal oxide structure, and a second metal structure and a third metal structure which are arranged on the second metal oxide structure at intervals;
annealing the first metal structure, the second metal structure and the third metal structure, so that a part of the first metal oxide structure close to the first metal structure is formed into a first conductive structure, a part of the second metal oxide structure close to the second metal structure is formed into a second conductive structure, and a part of the second metal oxide structure close to the third metal structure is formed into a third conductive structure;
forming a first gate insulating layer on portions of the substrate base plate, the first metal structure, the second metal structure, the third metal structure, and the second metal oxide structure not covered by the second metal structure and the third metal structure.
8. The method according to claim 7, wherein the etching the first metal layer and the first metal oxide layer to obtain a first metal oxide structure and a second metal oxide structure spaced apart from each other on the substrate, and a first metal structure on the first metal oxide structure and a second metal structure and a third metal structure spaced apart from each other on the second metal oxide structure comprises:
performing patterning processing on the first metal layer to form a first photoresist pattern and a second photoresist pattern on the first metal layer, wherein the second photoresist pattern comprises a first sub-photoresist pattern, a second sub-photoresist pattern and a third sub-photoresist pattern which are connected through the first sub-photoresist pattern;
etching off the parts of the first metal layer and the first metal oxide layer which are not covered by the first photoresist pattern and the second photoresist pattern to obtain a first metal oxide structure and a second metal oxide structure which are arranged on the substrate at intervals, a first metal structure arranged on the first metal oxide structure and a metal structure to be etched arranged on the second metal oxide structure;
removing the first sub-photoresist pattern;
and etching off the part of the metal structure to be etched, which is not covered by the first photoresist pattern, the second sub photoresist pattern and the third sub photoresist pattern, so as to obtain a second metal structure and a third metal structure which are arranged on the second metal oxide structure at intervals.
9. The method of claim 7, wherein the providing a substrate comprises:
providing a glass substrate;
forming a first shading layer and a second shading layer on the glass substrate at intervals;
forming a buffer layer on the glass substrate, the first light-shielding layer and the second light-shielding layer;
forming an active layer on the buffer layer, the active layer including a channel region, a source contact region and a drain contact region connected by the channel region;
forming a second gate insulating layer on the buffer layer and the active layer;
the sequentially forming a first metal oxide layer and a first metal layer on the substrate base plate comprises:
sequentially forming a first metal oxide layer and a first metal layer on the second gate insulating layer;
the forming a first gate insulating layer on portions of the substrate base plate, the first metal structure, the second metal structure, the third metal structure, and the second metal oxide structure not covered by the second metal structure and the third metal structure includes:
forming a first gate insulating layer on portions of the second gate insulating layer, the first metal structure, the second metal structure, the third metal structure, and the second metal oxide structure not covered by the second metal structure and the third metal structure.
10. The method of manufacturing a TFT substrate according to claim 9, wherein after forming the first gate insulating layer on the second gate insulating layer, the first metal structure, the second metal structure, the third metal structure, and the portion of the second metal oxide structure not covered by the second metal structure and the third metal structure, the method further comprises:
forming a second metal layer on the first gate insulating layer;
forming an interlayer dielectric layer on the first gate insulating layer and the second metal layer;
etching the second gate insulating layer, the first gate insulating layer and the interlayer dielectric layer to obtain a first via hole which corresponds to the source electrode contact region and penetrates through the second gate insulating layer, the first gate insulating layer and the interlayer dielectric layer, and a second via hole which corresponds to the drain electrode contact region and penetrates through the second gate insulating layer, the first gate insulating layer and the interlayer dielectric layer;
etching the first gate insulating layer and the interlayer dielectric layer to obtain a third via hole which corresponds to the second metal structure and penetrates through the first gate insulating layer and the interlayer dielectric layer, and a fourth via hole which corresponds to the third metal structure and penetrates through the first gate insulating layer and the interlayer dielectric layer;
depositing metal in the first via, the second via, the third via, and the fourth via.
11. The method of manufacturing a TFT substrate according to any one of claims 7 to 10, wherein the second metal structure includes a first sub-metal structure and a second sub-metal structure located on the first sub-metal structure, a material for manufacturing the first sub-metal structure is aluminum, a material for manufacturing the second sub-metal structure is molybdenum, and the annealing process is performed on the second metal structure so that a portion of the second metal oxide structure close to the second metal structure is formed as a second conductive structure, including:
and annealing the first sub-metal structure to form aluminum atoms, wherein the aluminum atoms are diffused into the second metal oxide structure to form doping, so that the part of the second metal oxide structure close to the first sub-metal structure is formed into a second conductive structure.
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| JP2023087648A (en) * | 2021-12-13 | 2023-06-23 | エルジー ディスプレイ カンパニー リミテッド | Display device including oxide semiconductor |
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| CN110137084A (en) * | 2019-05-30 | 2019-08-16 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof, electronic device substrate and electronic device |
| CN110797355A (en) * | 2019-11-27 | 2020-02-14 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and manufacturing method thereof |
| CN111755462A (en) * | 2020-06-23 | 2020-10-09 | 武汉华星光电半导体显示技术有限公司 | Array substrate and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| GB2612901A (en) * | 2021-10-21 | 2023-05-17 | Lg Display Co Ltd | Thin film transistor substrate and display device comprising the same |
| JP2023087648A (en) * | 2021-12-13 | 2023-06-23 | エルジー ディスプレイ カンパニー リミテッド | Display device including oxide semiconductor |
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