CN110137084A - Thin film transistor (TFT) and preparation method thereof, electronic device substrate and electronic device - Google Patents
Thin film transistor (TFT) and preparation method thereof, electronic device substrate and electronic device Download PDFInfo
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- CN110137084A CN110137084A CN201910463831.5A CN201910463831A CN110137084A CN 110137084 A CN110137084 A CN 110137084A CN 201910463831 A CN201910463831 A CN 201910463831A CN 110137084 A CN110137084 A CN 110137084A
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- film transistor
- thin film
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- 238000002360 preparation method Methods 0.000 title claims abstract description 72
- 239000000758 substrate Substances 0.000 title claims abstract description 71
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- 239000002184 metal Substances 0.000 claims abstract description 147
- 239000004020 conductor Substances 0.000 claims abstract description 45
- 239000010949 copper Substances 0.000 claims description 27
- 238000000137 annealing Methods 0.000 claims description 26
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
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- 239000004411 aluminium Substances 0.000 claims description 8
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- 239000010410 layer Substances 0.000 description 349
- 238000000034 method Methods 0.000 description 45
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- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 4
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
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- WUUZKBJEUBFVMV-UHFFFAOYSA-N copper molybdenum Chemical compound [Cu].[Mo] WUUZKBJEUBFVMV-UHFFFAOYSA-N 0.000 description 3
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
Abstract
A kind of thin film transistor (TFT) and preparation method thereof, electronic device substrate and electronic device, the preparation method of the thin film transistor (TFT), comprising: underlay substrate is provided；Metal layer is formed on underlay substrate, metal layer includes first part and second part insulated from each other；Active layer is formed on the metal layer, and active layer includes source area and drain region, and the first part of metal layer contacts source area, and the second part of metal layer contacts drain region；And by metal layer to the processing of active layer conductorization, so that source area and drain region are by conductor.The preparation method reduces the risk of poor contact existing for the conductor region of the active layer of thin film transistor (TFT).
Description
Technical field
Embodiment of the disclosure is related to a kind of thin film transistor (TFT) and preparation method thereof, electronic device substrate and electronic device.
Background technique
Thin film transistor (TFT) (TFT) includes the structures such as grid, source electrode, drain electrode, gate insulating layer and semiconductor layer.Grid passes through
Gate insulating layer is separated with semiconductor layer, and source electrode and drain electrode is directly contacted with semiconductor layer.When the voltage applied on grid reaches
When predetermined value, the channel region of the semiconductor layer between source electrode and drain electrode becomes conductive or non-conductive, when semiconductor layer
When channel region becomes conduction, electric current can produce between source electrode and drain electrode, thus thin film transistor (TFT) can play switch member
The effect of part.
Summary of the invention
At least one embodiment of the disclosure provides a kind of preparation method of thin film transistor (TFT), comprising: provides underlay substrate；?
Metal layer is formed on the underlay substrate, wherein the metal layer includes first part and second part insulated from each other；Institute
It states and forms active layer on metal layer, wherein the active layer includes source area and drain region, and described first of the metal layer
Tap touches the source area, and the second part of the metal layer contacts the drain region；And pass through the metal layer pair
The active layer conductorization processing, so that the source area and the drain region are by conductor.
For example, in the preparation method for the thin film transistor (TFT) that at least one embodiment of the disclosure provides, in the metal layer
It is upper to form the active layer, comprising: to form the first insulating layer on the metal layer, first insulating layer is made to cover the gold
Belong to layer and exposes the first part and the second part；And the active layer is formed on the first insulating layer.
For example, passing through the metal in the preparation method for the thin film transistor (TFT) that at least one embodiment of the disclosure provides
Layer is to active layer conductorization processing, comprising: makes annealing treatment to the metal layer and the active layer, so that the source area
With the drain region by conductor.
For example, in the preparation method for the thin film transistor (TFT) that at least one embodiment of the disclosure provides, the annealing
Temperature be 100-400 DEG C, time of the annealing is 10-500min.
For example, in the preparation method for the thin film transistor (TFT) that at least one embodiment of the disclosure provides, the metal layer
Material is aluminium, copper, titanium, molybdenum or alloy.
For example, at least one embodiment of the disclosure provide thin film transistor (TFT) preparation method further include: formed source electrode and
Drain electrode, wherein institute's source electrode is electrically connected with the source area of the active layer, the drain electrode of the drain electrode and the active layer
Area's electrical connection.
For example, the metal layer is also in the preparation method for the thin film transistor (TFT) that at least one embodiment of the disclosure provides
Including Part III, the Part III and the first part and the second part are insulated from each other, and the Part III exists
Orthographic projection on the underlay substrate is located at the active layer in the orthographic projection on the underlay substrate.
For example, in the preparation method for the thin film transistor (TFT) that at least one embodiment of the disclosure provides, the Part III
It is configured as the grid of the thin film transistor (TFT).
For example, passing through the gold in the preparation method for the thin film transistor (TFT) that at least one embodiment of the disclosure provides
After belonging to layer to active layer conductorization processing, the preparation method further include: form gate insulator on the active layer
Layer；Grid is formed on the gate insulating layer；And second insulating layer is formed on the grid.
For example, passing through the gold in the preparation method for the thin film transistor (TFT) that at least one embodiment of the disclosure provides
Before belonging to layer to active layer conductorization processing, the preparation method further include: form gate insulator on the active layer
Layer；Grid is formed on the gate insulating layer；And second insulating layer is formed on the grid.
For example, passing through the gold in the preparation method for the thin film transistor (TFT) that at least one embodiment of the disclosure provides
Before belonging to layer to active layer conductorization processing, the preparation method further include: form gate insulator on the active layer
Layer；After being handled by the metal layer the active layer conductorization, the preparation method further include: exhausted in the grid
Grid is formed in edge layer, and forms second insulating layer on the grid.
At least one embodiment of the disclosure also provides a kind of thin film transistor (TFT), comprising: metal layer, active layer, source electrode and leakage
Pole, wherein the metal layer is opaque metal layer, and the active layer is located on the metal layer, and the metal layer includes that
The first part and second part, the first part of this insulation contact the source area of the active layer, and the second part connects
The drain region of the active layer, the source area and the drain region are touched relative to the channel region of the active layer by conductor,
The source electrode is electrically connected with the source area of the active layer, and the drain electrode and the drain region of the active layer are electrically connected
It connects.
For example, in the thin film transistor (TFT) that at least one embodiment of the disclosure provides, the material of the metal layer be aluminium,
Copper, titanium, molybdenum or alloy.
For example, the thin film transistor (TFT) that at least one embodiment of the disclosure provides further includes the first insulating layer, wherein described the
One insulating layer is arranged between the metal layer and the active layer, and first insulating layer covers the metal layer except described the
Other parts outside a part of and described second part.
For example, the metal layer further includes third portion in the thin film transistor (TFT) that at least one embodiment of the disclosure provides
Point, the Part III and the first part and the second part are insulated from each other, and the Part III is located at described active
In the orthographic projection of layer on the metal layer.
For example, the Part III is configured as institute in the thin film transistor (TFT) that at least one embodiment of the disclosure provides
State the grid of transistor.
For example, the thin film transistor (TFT) that at least one embodiment of the disclosure provides further includes gate insulating layer, grid and second
Insulating layer, wherein the gate insulating layer is located at side of the active layer far from the metal layer, and the grid is located at described
Side of the gate insulating layer far from the active layer, the second insulating layer are located at the grid far from the gate insulating layer
Side.
At least one embodiment of the disclosure also provides a kind of electronic device substrate, including described in disclosure any embodiment
Thin film transistor (TFT).
At least one embodiment of the disclosure also provides a kind of electronic device, including electronics described in disclosure any embodiment
Device substrate.
Detailed description of the invention
In order to illustrate more clearly of the technical solution of the embodiment of the present disclosure, the attached drawing to embodiment is simply situated between below
It continues, it should be apparent that, the accompanying drawings in the following description merely relates to some embodiments of the present disclosure, rather than the limitation to the disclosure.
Fig. 1 is a kind of flow chart of the preparation method for thin film transistor (TFT) that some embodiments of the disclosure provide；
Fig. 2 is a kind of partial cross section structural schematic diagram for thin film transistor (TFT) that some embodiments of the disclosure provide；
Fig. 3 is the exemplary stream of the preparation method for the thin film transistor (TFT) shown in Fig. 2 that some embodiments of the disclosure provide
Cheng Tu；
Fig. 4 A-4F is the schematic diagram of the specific steps of the preparation method of thin film transistor (TFT) shown in corresponding diagram 3；
Fig. 5 is the square of the conductor region of the active layer obtained respectively by two kinds of conductor methods at different temperatures
The line chart of resistance；
Fig. 6 is the partial cross section structural schematic diagram for another thin film transistor (TFT) that some embodiments of the disclosure provide；
The exemplary stream of the preparation method of thin film transistor (TFT) shown in Fig. 6 that Fig. 7 provides for some embodiments of the disclosure
Cheng Tu；
Fig. 8 is a kind of partial plan view for electronic device substrate that some embodiments of the disclosure provide；And
Fig. 9 is a kind of part circuit structure schematic diagram for electronic device that some embodiments of the disclosure provide.
Specific embodiment
To keep the purposes, technical schemes and advantages of the embodiment of the present disclosure clearer, below in conjunction with the embodiment of the present disclosure
Attached drawing, the technical solution of the embodiment of the present disclosure is clearly and completely described.Obviously, described embodiment is this public affairs
The a part of the embodiment opened, instead of all the embodiments.Based on described embodiment of the disclosure, ordinary skill
Personnel's every other embodiment obtained under the premise of being not necessarily to creative work, belongs to the range of disclosure protection.
Unless otherwise defined, the technical term or scientific term used herein should be in disclosure fields and has
The ordinary meaning that the personage of general technical ability is understood." first ", " second " used in the disclosure and similar word are not
It indicates any sequence, quantity or importance, and is used only to distinguish different component parts.Equally, "one", " one " or
The similar word such as "the" does not indicate that quantity limits yet, but indicates that there are at least one." comprising " or "comprising" etc. are similar
Word means that the element or object that occur before the word are covered the element for appearing in the word presented hereinafter or object and its waited
Together, other elements or object are not excluded for.
It, can be with using plasma (such as the plasma of helium or argon gas currently, during preparing thin film transistor (TFT)
Body) conductor is carried out to the active layer (i.e. the source area of active layer and drain region) in thin film transistor (TFT) with source electrode, the lap-joint that drains
Change.But after using plasma method conductor, the conductor region of active layer still has biggish impedance, and
It is easy to be influenced by conductor technological fluctuation, is unable to reach good turn-on effect, and then lead to source electrode, drain electrode and active layer
Between generate poor contact risk.Therefore, there are unstability by the preparation process of thin film transistor (TFT).
At least one embodiment of the disclosure provides a kind of preparation method of thin film transistor (TFT), which, which passes through, utilizes gold
Belong to layer and need the region of conductor to carry out conductor processing the active layer of thin film transistor (TFT), reduces active layer and source electrode, leakage
The square resistance of pole lap-joint (i.e. contact area) enables the conductor region of active layer to reach good turn-on effect, into
And the risk that poor contact is generated between source electrode, drain electrode and active layer is avoided, improve the steady of the preparation process of thin film transistor (TFT)
It is qualitative.
In the following, some embodiments of the present disclosure will be described in detail with reference made to the accompanying drawings.It should be noted that in different attached drawings
Identical appended drawing reference will be used to refer to the identical element described.
Fig. 1 is a kind of flow chart of the preparation method for thin film transistor (TFT) that some embodiments of the disclosure provide.Such as Fig. 1 institute
Show, which includes the following steps.
Step S10: underlay substrate is provided.
Step S20: metal layer is formed on underlay substrate.Metal layer includes first part insulated from each other and second
Point.
Step S30: active layer is formed on the metal layer.The active layer includes source area and drain region, and the first of metal layer
Part contact source area, the second part of metal layer contact drain region.
Step S40: by metal layer to the processing of active layer conductorization, so that source area and drain region are by conductor.
Below in conjunction with the specific structure of some thin film transistor (TFT)s, the thin film transistor (TFT) that some embodiments of the disclosure are provided
Preparation method be illustrated.
Fig. 2 is a kind of partial cross section structural schematic diagram for thin film transistor (TFT) that some embodiments of the disclosure provide, and Fig. 3 is this
The exemplary process diagram of the preparation method for the thin film transistor (TFT) shown in Fig. 2 that some embodiments provide is disclosed, and Fig. 4 A-4F is pair
Answer the schematic diagram of the specific steps of the preparation method of thin film transistor (TFT) shown in Fig. 3.Below in conjunction with Fig. 2, Fig. 3 and figure
4A-4F is illustrated one embodiment of the disclosure.
For example, as shown in Fig. 2, thin film transistor (TFT) 100 includes the metal layer 120 set gradually on underlay substrate 110,
One insulating layer 130, active layer 140, gate insulating layer 151, grid 152, second insulating layer 153, source electrode 161 and drain electrode 162.
For example, the first insulating layer 130 is located at side of the metal layer 120 far from underlay substrate 110, active layer 140 is located at the
It is exhausted far from first that one side of the insulating layer 130 far from metal layer 120, gate insulating layer 151 and grid 152 are located at active layer 140
The side of edge layer 130, second insulating layer 153 are located at the side of gate insulating layer 151 and grid 152 far from active layer 140.Source electrode
161 contact with the source area 141 of active layer 140, and drain electrode 162 is contacted with the drain region 142 of active layer 140.
For example, metal layer 120 includes first part 121 insulated from each other and second part 122, and in Fig. 2, first part
121 from the contacts-side-down source area 141 of active layer 140, and second part 122 is from the contacts-side-down drain region 142 of active layer 140.
Below by taking the specific structure of thin film transistor (TFT) 100 shown in Fig. 2 as an example, to the preparation side of thin film transistor (TFT) 100
Method is illustrated.
For example, the preparation method of thin film transistor (TFT) 100 includes the steps that as described below in conjunction with shown in Fig. 3 and Fig. 4 A- Fig. 4 F
S101~S109.
Step S101: underlay substrate 110 is provided.
Step S102: metal layer 120 is formed on underlay substrate 110.
For example, underlay substrate 110 can be adopted for glass substrate, plastic base etc., such as the material of underlay substrate 110
With polyimides (PI), polyethylene (PE), polypropylene (PP), Triafol T (TAC) etc., embodiment of the disclosure to this not
It is restricted.
As shown in Figure 4 A, for example, metal layer 120 includes first part 121 insulated from each other and second part 122.For
Later by the active layer of formation 140, first part 121 is corresponding with source area 141 (as shown in Figure 2) of active layer 140, and second
Part 122 is corresponding with drain region 142 (as shown in Figure 2) of active layer 140, and the active layer 140 is in source area 141 and drain region
It include channel region between 142.
For example, the material of metal layer 120 can be the metal or alloy such as aluminium, copper, titanium, molybdenum, embodiment of the disclosure is to this
With no restriction.
For example, metal layer 120 can be formed by the methods of physical vapour deposition (PVD), chemical vapor deposition.For example, metal layer
120 can be handled by patterning processes to form first part 121 and second part 122, and embodiment of the disclosure is to this
With no restriction.
For example, metal layer 120 can be opaque metal layer.As described below, in another example, the metal layer 120 is also
It can be used for being formed the part of the light shield layer of thin film transistor (TFT) 100.For example, thin film transistor (TFT) has for the situation of bottom gate type
Active layer by from the light of underlay substrate side irradiation after meeting so that photo-generated carrier increase, cause thin film transistor (TFT) generation threshold
The bad phenomenons such as threshold voltage drift, leakage current increase.It in another example, is the situation of opaque metal layer in metal layer 120,
The part as light shield layer of metal layer 120 can be blocked to be injected for example from underlay substrate 110 far from the direction of metal layer 120
Environment light (such as blue light) avoids light from being irradiated to the other structures or function of the thin film transistor (TFT) 100 being arranged on metal layer 120
Energy component, and then the interference that extraneous light generates thin film transistor (TFT) 100 is reduced, improve the stabilization of thin film transistor (TFT) 100
Property, improve the working performance of thin film transistor (TFT) 100.
In addition, the situation of interception is played in metal layer 120, since thin film transistor (TFT) 100 no longer needs to separately prepare list
Only light shield layer and corresponding insulating layer, therefore the overall structure of thin film transistor (TFT) 100 is simplified, and makes thin film transistor (TFT)
100 preparation cost reduces, and also optimizes the preparation process of thin film transistor (TFT) 100, reduces and exists during the preparation process
Technique it is uncertain, and then improve the stability of 100 preparation process of thin film transistor (TFT), make the characteristic of thin film transistor (TFT) 100
It is more stable.
For example, specifically, metal layer 120 further includes Part III 123, Part III 123 as shown in Fig. 2 and Fig. 4 A
Between first part 121 and second part 122, and it is insulated from each other with first part 121 and second part 122.Third portion
123 are divided to be located at active layer 140 in the orthographic projection on underlay substrate 110 in the orthographic projection on underlay substrate 110, such as at least
In one example, Part III 123 is corresponding with the channel region of active layer 140, for example, Part III 123 is from source electrode 161 to leakage
Width on the direction of pole 162 is less than the width of active layer 140.
For example, metal layer 120 further includes Part IV 124 and Part V 125, Part IV in other examples
124 and Part V 125 and first part 121, second part 122 and Part III 123 it is insulated from each other.For example, in metal layer
120 for opaque metal layer and situation that the light shield layer as thin film transistor (TFT) 100 uses, and the 4th of opaque metal layer 120 the
Part 124 and Part V 125 can cover the most surfaces of underlay substrate 110, to prevent from underlay substrate 110 far from gold
Belong to such as environment light that the direction of layer 120 is injected to such as structure or function of thin film transistor (TFT) 100 is arranged on metal layer 120
Component generates interference, and then promotes the stability of thin film transistor (TFT) 100, improves the working performance of thin film transistor (TFT) 100.
Step S103: forming the first insulating layer 130 on metal layer 120, and the first insulating layer 130 is made to cover metal layer 120
And expose first part 121 and second part 122.
For example, the first insulating layer 130 is arranged between metal layer 120 and active layer 140 as shown in Fig. 2 and Fig. 4 B, first
Insulating layer 130 covers other parts of the metal layer 120 in addition to first part 121 and second part 122.For example, passing through composition work
Skill is to 130 composition of the first insulating layer, so that the first part 121 of 130 expose metal layer 120 of the first insulating layer and second
Divide 122, so that the source area that first part 121 and second part 122 can respectively with the active layer 140 formed in subsequent technique
141 and drain region 142 contact, and then can use in the subsequent process metal layer 120 to source area 141 and drain region 142 into
Column conductorization processing.
For example, the first insulating layer 130 generallys use organic insulating material (for example, acrylic resin) or inorganic insulation
Material is (for example, silicon nitride SiNx or silicon oxide sio x) are formed.For example, the first insulating layer 130 can for by silicon nitride or
The single layer structure that silica is constituted, or the double-layer structure being made of silicon nitride and silica.
For example, the first insulating layer 130 can pass through physical gas-phase deposite method, chemical vapor deposition method or coating shape
At, embodiment of the disclosure to this with no restriction.
Step S104: active layer 140 is formed on the first insulating layer 130.
As shown in Figure 4 C, for example, in some embodiments of the present disclosure, since the first insulating layer 130 covers metal layer 120
And first part 121 and second part 122 are exposed, therefore the first part 121 of metal layer 120 contacts the source electrode of active layer 140
The second part 122 in area 141, metal layer 120 contacts the drain region 142 of active layer 140, and then can lead in subsequent steps
The first part 121 and second part 122 for crossing metal layer 120 lead the source area 141 of active layer 140 and drain region 142
Bodyization processing, to obtain source area 141 and the drain region 142 of conductor.
For example, active layer 140 can be formed using semiconductor material, the semiconductor material be, for example, amorphous silicon, microcrystal silicon,
Polysilicon, oxide semiconductor etc., oxide semiconductor material for example can be indium gallium zinc oxide (IGZO), zinc oxide
(ZnO) etc..For example, active layer 140 can be patterned for example, by photoetching process and forms semiconductor pattern, the implementation of the disclosure
Example to this with no restriction.
Step S105: metal layer 120 and active layer 140 are made annealing treatment, so that source area 141 and drain region 142 are led
Body.
For example, annealing can be carried out using the method for compressed air (CDA).The temperature of annealing can be 100
DEG C -400 DEG C, such as can be set between 100 DEG C -300 DEG C.The time of annealing can be 10-500min, the disclosure
Embodiment to this with no restriction.
As shown in Figure 4 D, for example, when being made annealing treatment to metal layer 120 and active layer 140, due to source area 141
It is contacted with the first part 121 of metal layer 120, the second part 122 of drain region 142 and metal layer 120 contacts, and therefore, is moving back
Under the high temperature action of fire process, source area 141 and first part 121 are diffused into one another, such as first part 121 is by the metal of itself
Atom is diffused into source area 141, with 141 conductor of inducing source area；Drain region 142 and second part 122 diffuse into one another, the
The metallic atom of itself is diffused into drain region 142 by two parts 122, with 142 conductor of induced drain area.
For example, being made annealing treatment source area 141 and drain region 142 to induce active layer 140 using metal layer 120
After conductor, the square resistance for the source area 141 of active layer 140 contacted with source electrode 161 and the drain electrode contacted with drain electrode 162
The square resistance in area 142 can be reduced, and thus the contact resistance between source electrode 161 and source area 141 reduces, drain electrode
Contact resistance between 162 and drain region 142 reduces.Therefore, when thin film transistor (TFT) 100 works, source can be better achieved
Electric signal transmission between pole 161, drain electrode 162 and active layer 140, improves the stability of thin film transistor (TFT) 100, and it is brilliant to improve film
The working performance of body pipe 100.
Step S106: gate insulating layer 151 is formed on active layer 140.
As shown in Figure 4 E, for example, the material of gate insulating layer 151 includes silicon nitride (SiNx), silica (SiOx), oxidation
Aluminium (Al2O3), aluminium nitride (AlN) or other suitable materials.For example, gate insulating layer 152 can be by physical vapour deposition (PVD) side
Method, chemical vapor deposition method or coating method are formed.Embodiment of the disclosure to this with no restriction.
Step S107: grid 152 is formed on gate insulating layer 151.
As shown in Figure 4 E, grid 152 is formed on gate insulating layer 151, at least one example, from source electrode
161 on the direction of drain electrode 162, the Part III 123 of the width and metal layer 120 of grid 152 it is of same size, or be less than
The width of Part III 123；In another example orthographic projection of the grid 152 on underlay substrate 110 is in Part III 123 in substrate base
Within orthographic projection on plate 110.
For example, the material of grid 152 can be copper base metal, for example, copper (Cu), copper molybdenum alloy (Cu/Mo), copper-titanium alloy
(Cu/Ti), copper-molybdenum titanium alloy (Cu/Mo/Ti), copper-molybdenum tungsten alloy (Cu/Mo/W), copper-molybdenum niobium alloy (Cu/Mo/Nb) etc..For example,
The material of grid 152 may be chromium Base Metal, for example, chrome molybdenum (Cr/Mo), chromium titanium alloy (Cr/Ti), chromium molybdenum titanium alloy
(Cr/Mo/Ti) etc..It for example, the material of grid 152 can also be aluminum or aluminum alloy etc., or is other suitable materials.
For example, grid 152 can be with gate insulating layer 151 using the same patterning processes are patterned or the two can be with
It is patterned in two patterning processes respectively, embodiment of the disclosure to this with no restriction.
Step S108: second insulating layer 153 is formed on grid 152.
For example, second insulating layer 153 generallys use organic insulating material (for example, acrylic resin) or inorganic insulation
Material is (for example, perhaps silicon oxide sio x) formation for example can be the list being made of silicon nitride or silica to silicon nitride SiNx
Layer structure, or the double-layer structure etc. being made of silicon nitride and silica.For example, second insulating layer 153 can pass through physics gas
Phase deposition method, chemical vapor deposition method or coating method are formed.Embodiment of the disclosure to this with no restriction.
And as shown in Figure 4 E, the patterned formation of second insulating layer 153 exposes source area 141 and drain region 142 respectively
Two via holes, for realizing being electrically connected between the source electrode 161 and drain electrode 162 and source area 141 and drain region 142 formed later
It connects.
For example, step S106, step S107 and step S108 can also be in steps in some other embodiment of the disclosure
It is carried out before rapid S105, that is to say, that step S105 can be executed after step S108.That is, to metal layer 120 and active
Before the annealing of floor 140 is to utilize 120 inducing source area 141 of metal layer and 142 conductor of drain region, on active layer 140
Gate insulating layer 151 is formed, forms grid 152 on gate insulating layer 151, and form second insulating layer on grid 152
153。
For example, being made annealing treatment the source electrode to induce active layer 140 using metal layer 120 to thin film transistor (TFT) 100
When 142 conductor of area 141 and drain region, since the both side surface of grid 152 is respectively by gate insulating layer 151 and second insulating layer
153 are covered, and grid 152 and active layer 140 are insulated from each other, therefore, will not be right when carrying out annealing process again after step S107
The performance of grid 152 causes undesirable influence.
For example, in some other embodiment of the disclosure, step S105 can also step S106 and step S107 it
Between execute.That is, having before by metal layer 120 to source area 141 and 142 conductorization of the drain region processing of active layer 140
Gate insulating layer 151 is formed in active layer 140；The source area 141 of active layer 140 and drain region 142 are led by metal layer 120
After bodyization processing, grid 152 is formed on gate insulating layer 151, and second insulating layer 153 is formed on grid 152.
For example, the execution sequence of step S105 correspondingly can also be adjusted flexibly in some other embodiment of the disclosure
It is whole, such as can be according to different actual demands, the annealing process in step S105 is after forming a layer insulating
Can, embodiment of the disclosure to this with no restriction.
Step S109: source electrode 161 and drain electrode 162 are formed.Source electrode 161 is electrically connected with the source area 141 of active layer 140, leakage
Pole 162 is electrically connected with the drain region 142 of active layer 140.
As illustrated in figure 4f, source electrode 161 and drain electrode 162 are insulated from each other.For example, source electrode 161 and the material of drain electrode 162 can be
Copper base metal, for example, copper (Cu), copper molybdenum alloy (Cu/Mo), copper-titanium alloy (Cu/Ti), copper-molybdenum titanium alloy (Cu/Mo/Ti), copper
Molybdenum and tungsten alloy (Cu/Mo/W), copper-molybdenum niobium alloy (Cu/Mo/Nb) etc.；Or, or chromium Base Metal, for example, chrome molybdenum
(Cr/Mo), chromium titanium alloy (Cr/Ti), chromium molybdenum titanium alloy (Cr/Mo/Ti) etc. or other suitable materials, the implementation of the disclosure
Example to this with no restriction.
It, can sedimentary origin drain electrode layer film be simultaneously in second insulating layer 153 for example, in some embodiments of the present disclosure
Technique is patterned to it to form source-drain electrode layer.The source-drain electrode layer includes source electrode 161 and drain electrode 162, the reality of the disclosure
Example is applied to this with no restriction.
For example, in some embodiments of the present disclosure, after step S109 forms source electrode 161 and drain electrode 162, film crystal
The preparation method of pipe 100 can also include forming such as third insulating layer (not shown) on source electrode 161 and drain electrode 162.For example,
Annealing process in step S105 can also execute after forming third insulating layer, and embodiment of the disclosure does not limit this
System.
For example, being carried out in the case of being executed after forming third insulating layer to thin film transistor (TFT) 100 in step S105
When annealing, since the surface region that source electrode 161 and source area 141 contact can interpenetrate, drain electrode 162 and drain region
The surface region of 142 contacts can interpenetrate, therefore the contact resistance between source electrode 161 and source area 141 can be further
It reduces, the contact resistance between drain electrode 162 and drain region 142 can further decrease, source area 141 and leakage after making conductor
Polar region 142 can preferably transmission telecommunications number, reach better turn-on effect.Thus, it is possible to substantially reduce thin film transistor (TFT) 100
The risk of poor contact that may be present, and then significant the stability for promoting thin film transistor (TFT) 100, improve thin film transistor (TFT)
100 working performance.
For example, the preparation method for the thin film transistor (TFT) 100 that some embodiments of the present disclosure provide can also include it is more or
Less step, and the sequence between each step is unrestricted, it can be depending on different actual demands.
For example, the material used by metal layer 120, for aluminum metal, Fig. 5 is to be obtained respectively by two kinds of conductor methods
The broken line of the square resistance of the conductor region (i.e. source area 141 and drain region 142) of the active layer 140 arrived at different temperatures
Figure.
For example, as shown in figure 5, broken line 1 indicates the conductor region obtained by the method for plasma in different temperatures
Lower corresponding square resistance, broken line 2 indicate the conductor region obtained by the method for metal inducement institute at different temperatures
Corresponding square resistance.
As shown in figure 5, it is greater than 100 DEG C or so of situation in temperature, the active layer obtained using the method that metal layer induces
The square resistance in 140 conductor region (such as source area 141 and drain region 142) is lower than to be obtained using the method for plasma
Active layer 140 conductor region square resistance.For example, the situation for being 250 DEG C in temperature, the side induced using metal layer
The numerical value of the square resistance in the conductor region that method obtains utilizes plasma between 1.E+06 Ω/~1.E+07 Ω/
The numerical value of the square resistance in the conductor region that the method for body obtains utilizes between 1.E+03 Ω/~1.E+04 Ω/
The square resistance in the conductor region that the method for metal layer induction obtains is than the conductor area that the method using plasma obtains
The low 3 several magnitudes of the square resistance in domain.
Therefore, the region (such as source area and drain region) of conductor is needed to active layer using the method that metal layer induces
The square resistance in conductor region can be substantially reduced by carrying out conductorization processing, and the conductor region of active layer is made to reach good
Turn-on effect, such as source area for thereby reducing active layer may be deposited with source electrode electrical contact or drain region with when draining and being in electrical contact
Poor contact risk, improve the stability of thin film transistor (TFT) significantly, improve the working performance of thin film transistor (TFT), together
When also improve thin film transistor (TFT) preparation process stability, optimize the manufacturing process of thin film transistor (TFT).
For example, annealing can be carried out using the method for compressed air (CDA) in some embodiments of the present disclosure.
The temperature of annealing can be 100 DEG C -400 DEG C, such as can be set between 100 DEG C -300 DEG C.The time of annealing
It can be 10-500min.
For example, in some embodiments of the present disclosure, since metal layer 120 is arranged in active layer 140 close to underlay substrate
110 side (i.e. the side far from source electrode 161 and drain electrode 162), therefore during annealing, metal layer 120 is because of height
Temperature effect and issuable metal oxide (such as aluminium oxide) are located at active layer 140 close to the side of underlay substrate 110, because
And the metal oxide source area 141 that active layer 140 will not be contacted with source electrode 161 and the drain electrode contacted with drain electrode 162
Area 142 has an impact, thus reduces the uncertainty that may be present during the preparation process of thin film transistor (TFT) 100, improves thin
The stability of the preparation process of film transistor 100 improves the working performance of thin film transistor (TFT) 100.
In addition, the microstructure of the material of active layer 140 may change under the high temperature action of annealing process,
And then the apparent property of active layer 140 is made to change.For example, the original under the high temperature action of annealing process, in active layer 140
Son obtains energy, can reselect the lower lattice position of energy, and then can reduce microstructure in active layer 140
Defect keeps the characteristic of thin film transistor (TFT) 100 more stable, reaches better working performance.
For example, in embodiment of the disclosure, making metal layer 120 induce active layer 140 using the method for annealing
142 conductor of source area 141 and drain region makes conductorization treated source area 141 and the square resistance of drain region 142 significantly
Reduce, so thin film transistor (TFT) 100 work when can be better achieved active layer 140 source area 141 and drain region 142 it
Between electric signal transmission, promoted thin film transistor (TFT) 100 stability.It, can be with root in some other embodiment of the disclosure
According to different actual demands, using the method for other high-temperature process or other suitable processes, to be lured using metal layer 120
Lead 142 conductor of source area 141 and drain region of active layer 140, embodiment of the disclosure to this with no restriction.
It should be noted that Fig. 2 and Fig. 3 illustrate only the part-structure of thin film transistor (TFT) 100 and corresponding exemplary
Preparation method.Thin film transistor (TFT) 100 can also include other structures or functional layer, and correspondingly, which can also include
Other corresponding preparation steps, embodiment of the disclosure to this with no restriction.
It should be noted that thin film transistor (TFT) 100 shown in Fig. 2 and Fig. 3 is the thin film transistor (TFT) of top-gate type structure, and
In some other embodiment of the disclosure, thin film transistor (TFT) 100 can also be the thin film transistor (TFT) of bottom-gate type configuration, the disclosure
Embodiment to this with no restriction.
Fig. 6 is the partial cross section structural schematic diagram for another thin film transistor (TFT) 200 that some embodiments of the disclosure provide, figure
The exemplary process diagram of the preparation method of thin film transistor (TFT) 200 shown in 7 Fig. 6 provided for some embodiments of the disclosure.
For example, in addition to grid, gate insulating layer and second insulating layer, the structure of thin film transistor (TFT) 200 shown in Fig. 6 with
The structure of thin film transistor (TFT) 100 shown in Fig. 2 is substantially the same, and which is not described herein again.
For example, in thin film transistor (TFT) 200 shown in Fig. 6, due to the Part III 223 of metal layer 220 and first part
221 and second part 222 it is insulated from each other, and orthographic projection of the Part III 223 on underlay substrate 210 is located at active layer 240 and exists
In orthographic projection on underlay substrate 210, therefore Part III 223 can be additionally configured to the grid of thin film transistor (TFT) 200, i.e., and
Three parts 223 can be multiplexed with the grid of thin film transistor (TFT) 200.Therefore, compared with situation shown in Fig. 2, in film crystal
In pipe 200, without still further preparing the structures such as grid and gate insulating layer, to simplify the whole knot of thin film transistor (TFT) 200
Structure reduces the preparation cost of thin film transistor (TFT) 200, while also optimizing the preparation process of thin film transistor (TFT) 200.
For example, as shown in fig. 7, by taking the specific structure of thin film transistor (TFT) 200 shown in fig. 6 as an example, thin film transistor (TFT) 200
Preparation method may comprise steps of S201~S207.
Step S201: underlay substrate 210 is provided.
Step S202: metal layer 220 is formed on underlay substrate 210.Metal layer 220 includes first part insulated from each other
221, second part 222 and Part III 223.
Step S203: forming the first insulating layer 230 on metal layer 220, and the first insulating layer 230 is made to cover metal layer 220
And expose first part 221 and second part 222.
Step S204: active layer 240 is formed on the first insulating layer 230.
Step S205: metal layer 220 and active layer 240 are made annealing treatment, so that source area 241 and drain region 242 are led
Body.
Step S206: the 4th insulating layer 254 is formed on active layer 240.
Step S207: source electrode 261 and drain electrode 262 are formed.Source electrode 261 is electrically connected with the source area 241 of active layer 240, leakage
Pole 262 is electrically connected with the drain region 242 of active layer 240.
For example, the 4th insulating layer 254 generallys use organic insulating material (for example, acrylic resin) or inorganic insulation
Material is (for example, perhaps silicon oxide sio x) formation for example can be the list being made of silicon nitride or silica to silicon nitride SiNx
Layer structure, or the double-layer structure etc. being made of silicon nitride and silica.For example, the 4th insulating layer 254 can pass through physics gas
Phase deposition method, chemical vapor deposition method or coating the methods of formed, embodiment of the disclosure to this with no restriction.
The detailed content and technical effect of the preparation method for the thin film transistor (TFT) 200 that embodiment of the disclosure provides can join
The description of the preparation method above in connection with thin film transistor (TFT) 100 is examined, which is not described herein again.
As needed, such as in preparation it is used for the situation of the array substrate of liquid crystal display device (LCD), can also continue to
The structure such as pixel electrode, public electrode is prepared on underlay substrate, and grid line can be prepared while preparing grid,
While preparing source electrode and drain electrode, data line etc. can be prepared.Such as the battle array of Organic Light Emitting Diode (OLED) is used in preparation
The situation of column substrate can also continue to prepare on underlay substrate such as pixel defining layer, anode, luminescent layer, cathode, and
The structures such as other thin film transistor (TFT)s, capacitor can also be prepared.For example, preparation for other kinds of electronic device (such as at
As device) substrate situation, other component, including but not limited to signal wire, capacitor, photosensitive member can also be prepared as needed
Part etc..
At least one embodiment of the disclosure also provides a kind of thin film transistor (TFT), which includes: metal layer, active
Layer, source electrode and drain electrode.Metal layer is opaque metal layer, and active layer is located on metal layer, and metal layer includes insulated from each other
A part and second part, first part contact the source area of active layer, and second part contacts the drain region of active layer, source area
With drain region relative to active layer channel region by conductor, source electrode is electrically connected with the source area of active layer, drain electrode and active layer
Drain region electrical connection.
For example, the opaque metal layer can be configured as in the thin film transistor (TFT) that some embodiments of the disclosure provide
Such as light shield layer of thin film transistor (TFT).For example, due to the first part of the opaque metal layer and second part respectively with it is active
The source area of layer and drain region contact, thus under certain fabrication condition, which can also induce active
The source area and drain region conductor of layer.Therefore, which both can be to the knot for the thin film transistor (TFT) being arranged on
Structure or functional component play the role of protecting shading, at the same can also induce under such as hot conditions the source area of active layer with
Drain region conductor.
Therefore, in the source area and drain region conductor of the active layer using opaque metal layer induction thin film transistor (TFT)
Situation, the thin film transistor (TFT) that some embodiments of the disclosure provide no longer needs to additionally prepare for example new metal layer as light shield layer
And corresponding insulating layer, or no longer need to be additionally provided source area and drain region conductor of the new metal layer to induce active layer
Change, and then simplify the structure of thin film transistor (TFT), reduces the preparation cost of thin film transistor (TFT), while also simplifying film crystal
The preparation process of pipe reduces the uncertainty of the technique present in the preparation process of thin film transistor (TFT), makes thin film transistor (TFT)
Characteristic is more stable.
For example, thin film transistor (TFT) can be thin film transistor (TFT) 100 shown in Fig. 2 in some embodiments of the present disclosure
Or thin film transistor (TFT) 200 shown in Fig. 6.The specific structure and technical effect for the thin film transistor (TFT) that the embodiment of the present disclosure provides can
With the description of the thin film transistor (TFT) 200 with reference to shown in thin film transistor (TFT) 100 shown in Fig. 2 or Fig. 6, which is not described herein again.
For example, in the thin film transistor (TFT) that at least one embodiment of the disclosure provides, the material of metal layer can for aluminium,
The opaque metals such as copper, titanium, molybdenum or alloy.
As shown in Figure 2 and Figure 6, for example, the thin film transistor (TFT) that at least one embodiment of the disclosure provides further includes first exhausted
Edge layer.First insulating layer is arranged between metal layer and active layer, and the first insulating layer covers metal layer and removes first part and second
Other parts outside part.
As shown in Fig. 2, for example, metal layer further includes in the thin film transistor (TFT) that at least one embodiment of the disclosure provides
Part III, Part III and first part and second part are insulated from each other, and Part III is located at active layer on the metal layer
In orthographic projection.
As shown in fig. 6, for example, Part III is matched in the thin film transistor (TFT) that at least one embodiment of the disclosure provides
It is set to the grid of thin film transistor (TFT), thus in active layer (namely far from underlay substrate side) without re-forming grid, by
This formed bottom gate thin film transistor also or could be formed with second grid and thus obtain double grid transistor npn npn.
As shown in Fig. 2, for example, at least one embodiment of the disclosure provide thin film transistor (TFT) further include gate insulating layer,
Grid and second insulating layer.Gate insulating layer is located at side of the active layer far from metal layer, and it is separate that grid is located at gate insulating layer
The side of active layer, second insulating layer are located at side of the grid far from gate insulating layer.
At least one embodiment of the disclosure also provides a kind of electronic device substrate, including described in disclosure any embodiment
Thin film transistor (TFT), such as may include thin film transistor (TFT) 100 or thin film transistor (TFT) shown in fig. 6 200 shown in Fig. 2.
Below for including the electronic device substrate of thin film transistor (TFT) 100 shown in Fig. 2, to some embodiments of the disclosure
The electronic device substrate of offer is illustrated.
Fig. 8 is a kind of partial plan view for electronic device substrate that some embodiments of the disclosure provide.
In conjunction with shown in Fig. 2 and Fig. 8, in electronic device substrate 30, source electrode 161 is by being arranged in second insulating layer 153
The first via hole 171 be electrically connected with the source area 141 of active layer 140, drain electrode 162 is by being arranged in second insulating layer 153
Second via hole 172 is electrically connected with the drain region 142 of active layer 140.
For example, electronic device substrate 30 further includes the pixel electrode 310 being arranged on underlay substrate 110, pixel electrode 310
It is electrically connected to each other with drain electrode 162.For example, fluted (not shown), pixel electrode can be set in the surface of second insulating layer 153
310 are formed in the groove.
For example, electronic device substrate 30 further includes the public electrode 320 being arranged on underlay substrate 110, public electrode 320
It is covered by second insulating layer 153.
For example, pixel electrode 310 and public electrode 320 can be plate electrode, or gap electrode.For example, picture
Plain electrode 310 and public electrode 320 may include multiple branch electrodes, i.e., the two all has pectinate texture, and pixel electrode 310
Branch and the branch of public electrode 320 for example overlap each other or arrangement interlaced with each other.As shown in figure 8, pixel electrode 310 is narrow
Electrode is stitched, including multiple branch electrodes for example parallel to each other, branch electrodes are opened by slit separation；Public electrode 320 is plate
Electrode.For example, in the present embodiment, pixel electrode 310 is formed on public electrode 320, the electronic device substrate 30 is for example
It can be used for Senior super dimension field switch technology (Advanced Super Dimension Switch, abbreviation ADS) type liquid crystal surface
Plate.
As shown in figure 8, electrode assembly substrate 30 further includes grid line 330, for example, grid line 330 can integrally be set with grid 152
It sets and is covered by second insulating layer 153.
For example, electrode assembly substrate 30 further includes data line 340, data line 340 extends in the longitudinal direction, and grid line 330 exists
Extend in horizontal direction, the two intersection insulated from each other, thin film transistor (TFT) 100 is for example formed at the position that the two is intersected.
For example, the material of data line 340 may include copper base metal, aluminium based metal, nickel based metal etc..For example, this is copper-based
Metal is the stable copper of performances such as copper (Cu), ormolu (CuZn), corronil (CuNi) or Alfenide (CuZnNi)
Base alloy.
For example, data line 340 can be set in second insulating layer 153, thus source electrode 161 can with data line 340 that
This is electrically connected or is formed as one.Alternatively, data line 340 can be set on underlay substrate 110 and be covered by second insulating layer 153
Lid (guarantee data line 340 and the setting insulated from each other of grid line 330, for example, in the two position setting insulation intersected with each other and
Such as each line segment that data line 340 is separated by grid line 330 is electrically connected to each other by bridged electrodes), thus in second insulating layer
It can also include a via hole (not shown) on 153, source electrode 161 is electrically connected by the via hole with data line 340.
For example, source electrode 161 is electrically connected with drain electrode 162 by active layer 140 when being applied open signal on grid line 330,
Thin film transistor (TFT) 100 is connected, so that pixel electrode 310 is electrically connected with data line 340, the signal applied on data line 340
Pixel electrode 310 can be passed to；When being applied shutdown signal on grid line 330, thin film transistor (TFT) 100 ends, to make
Pixel electrode 310 is obtained to be electrically connected with the disconnection of data line 340.
It should be noted that a pixel region is illustrated only in Fig. 8, but those skilled in the art can know
Road, the electronic device substrate 30 include multiple such pixel regions, and multiple pixel arrangement is array to constitute display area.
It should be noted that electronic device substrate 30 shown in Fig. 8 for example can be applied in liquid crystal display panel, and in this public affairs
In some other embodiment opened, electronic device substrate can also include other structures, and can be applied to such as OLED
In the other kinds of display panel such as panel, embodiment of the disclosure to this with no restriction.
Thin film transistor (TFT) (example described in the technical effect and realization principle and the embodiment of the present disclosure of electronic device substrate 30
Such as thin film transistor (TFT) 100 or thin film transistor (TFT) 200) it is essentially identical, details are not described herein.
At least one embodiment of the disclosure also provides a kind of electronic device, including electronics described in disclosure any embodiment
Device substrate.
For example, the electronic device that the embodiment of the present disclosure provides may include electronic device substrate 30 shown in fig. 8.Below
By it is a kind of including the electronic device with sensitization function of electronic device substrate 30 shown in Fig. 8 for, to some realities of the disclosure
The electronic device for applying example offer is illustrated.
Fig. 9 is a kind of part circuit structure schematic diagram for electronic device that some embodiments of the disclosure provide.Such as Fig. 9 institute
Show, electronic device 40 includes multiple pixel regions (such as pixel unit) shown in fig. 8.For example, each pixel unit includes
Photodiode 410 and thin film transistor (TFT) 100.
For example, in conjunction with shown in Fig. 8 and Fig. 9, the thin film transistor (TFT) 100 of an each pixel unit grid line adjacent thereto
330 electrical connections, the photodiode 410 of each pixel unit via in the pixel unit thin film transistor (TFT) 100 and with its phase
An adjacent data line 340 (or read line) electrical connection.In the matrix of multiple pixel units composition, in every one-row pixels unit
Each thin film transistor (TFT) 100 grid 152 and a grid line 330 adjacent thereto electrical connection, in each column pixel unit
The source electrode 161 of each thin film transistor (TFT) 100 and a data line 340 adjacent thereto electrical connection, the film of each pixel unit
The cathode of the photodiode 410 of the drain electrode 162 and pixel unit of transistor 100 is electrically connected, and the photoelectricity of the pixel unit
The anode of diode 410 can be electrically connected with such as bias line 420.For example, bias line 420 is parallel with grid line 330, and every a line
Pixel unit shares same bias line 420.For example, each grid line 330 is electrically connected with gate driving circuit, pieces of data line
340 are electrically connected with data drive circuit.
For example, by taking the electronic device 40 shown in Fig. 9 with sensitization function as an example, photodiode 410 directly or
When ground connection induction such as photosignal, electronic device 40 applies scanning signal to each pixel unit by grid line 330 to control
The switch state of thin film transistor (TFT) 100 indirectly controls data drive circuit by data line 340 to each photoelectricity two to reach
The read functions for the photosignal that pole pipe 410 generates, and then electronic device 40 is made to realize sensitization function.For example, working as film crystal
When pipe 100 is opened, the photosignal that photodiode 410 corresponding with thin film transistor (TFT) 100 generates may be connected to thin
The data line 340 of the source electrode 161 of film transistor 100 is acquired, and then realizes the acquisition to 410 photosignal of photodiode.
For example, electronic device 40 can also be the electronic device with other function, correspondingly, each of electronic device 40
May include other corresponding functional components in pixel unit, embodiment of the disclosure to this with no restriction.
Electronic device substrate described in the technical effect and realization principle and the embodiment of the present disclosure of electronic device 40 (such as
Electronic device substrate 30) or thin film transistor (TFT) (such as thin film transistor (TFT) 100 or thin film transistor (TFT) 200) it is essentially identical, herein not
It repeats again.
For example, electronic device 40 can be liquid crystal display panel, Electronic Paper, oled panel, mobile phone, tablet computer, television set, show
Show any products or components having a display function such as device, laptop, Digital Frame, navigator, embodiment of the disclosure
With no restriction to this.
There is the following to need to illustrate:
(1) embodiment of the present disclosure attached drawing relates only to the structure being related to the embodiment of the present disclosure, and other structures can refer to
It is commonly designed.
(2) for clarity, in the attached drawing for describing implementation of the disclosure example, the thickness in layer or region is amplified
Or reduce, i.e., these attached drawings are not drawn according to actual ratio.It is appreciated that ought such as layer, film, region or substrate etc
When element is referred to as being located at "above" or "below" another element, then the element " direct " can be located at "above" or "below" another element,
Or may exist intermediary element.
(3) in the absence of conflict, the feature in embodiment of the disclosure and embodiment can be combined with each other to obtain
New embodiment.
The above, the only specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, it is any
Those familiar with the art can easily think of the change or the replacement in the technical scope that the disclosure discloses, and should all contain
It covers within the protection scope of the disclosure.Therefore, the protection scope of the disclosure should be subject to the protection scope in claims.
Claims (19)
1. a kind of preparation method of thin film transistor (TFT), comprising:
Underlay substrate is provided；
Metal layer is formed on the underlay substrate, wherein the metal layer includes first part insulated from each other and second
Point；
Active layer is formed on the metal layer, wherein the active layer includes source area and drain region, the institute of the metal layer
It states first part and contacts the source area, the second part of the metal layer contacts the drain region；And
The active layer conductorization is handled by the metal layer, so that the source area and the drain region are by conductor.
2. the preparation method of thin film transistor (TFT) according to claim 1, wherein formed on the metal layer described active
Layer, comprising:
The first insulating layer is formed on the metal layer, and first insulating layer is made to cover the metal layer and exposure described first
Part and the second part；And
The active layer is formed on the first insulating layer.
3. the preparation method of thin film transistor (TFT) according to claim 1 or 2, wherein have by the metal layer to described
The processing of active layer conductorization, comprising:
The metal layer and the active layer are made annealing treatment, so that the source area and the drain region are by conductor.
4. the preparation method of thin film transistor (TFT) according to claim 3, wherein the temperature of the annealing is 100-
400 DEG C, the time of the annealing is 10-500min.
5. the preparation method of thin film transistor (TFT) according to claim 1 or 2, wherein the material of the metal layer be aluminium,
Copper, titanium, molybdenum or alloy.
6. the preparation method of thin film transistor (TFT) according to claim 1 or 2, further includes: source electrode and drain electrode is formed,
Wherein, institute's source electrode is electrically connected with the source area of the active layer, the drain electrode of the drain electrode and the active layer
Area's electrical connection.
7. the preparation method of thin film transistor (TFT) according to claim 1 or 2, wherein the metal layer further includes third portion
Point,
The Part III and the first part and the second part are insulated from each other, and the Part III is in the substrate base
Orthographic projection on plate is located at the active layer in the orthographic projection on the underlay substrate.
8. the preparation method of thin film transistor (TFT) according to claim 7, wherein the Part III is configured as described thin
The grid of film transistor.
9. the preparation method of thin film transistor (TFT) according to claim 1 or 2, wherein passing through the metal layer to described
After the processing of active layer conductorization, the preparation method further include:
Gate insulating layer is formed on the active layer；
Grid is formed on the gate insulating layer；And
Second insulating layer is formed on the grid.
10. the preparation method of thin film transistor (TFT) according to claim 1 or 2, wherein passing through the metal layer to described
Before the processing of active layer conductorization, the preparation method further include:
Gate insulating layer is formed on the active layer；
Grid is formed on the gate insulating layer；And
Second insulating layer is formed on the grid.
11. the preparation method of thin film transistor (TFT) according to claim 1 or 2, wherein passing through the metal layer to described
Before the processing of active layer conductorization, the preparation method further include:
Gate insulating layer is formed on the active layer；
After being handled by the metal layer the active layer conductorization, the preparation method further include:
Grid is formed on the gate insulating layer, and
Second insulating layer is formed on the grid.
12. a kind of thin film transistor (TFT), comprising: metal layer, active layer, source electrode and drain electrode,
Wherein, the metal layer is opaque metal layer, and the active layer is located on the metal layer,
The metal layer includes first part and second part insulated from each other, and the first part contacts the source of the active layer
Polar region, the second part contact the drain region of the active layer,
The source area and the drain region relative to the active layer channel region by conductor, the source electrode with it is described active
The source area electrical connection of layer, the drain electrode are electrically connected with the drain region of the active layer.
13. thin film transistor (TFT) according to claim 12, wherein the material of the metal layer is aluminium, copper, titanium, molybdenum
Or alloy.
14. thin film transistor (TFT) according to claim 12 or 13 further includes the first insulating layer,
Wherein, first insulating layer is arranged between the metal layer and the active layer, and first insulating layer covers institute
State other parts of the metal layer in addition to the first part and the second part.
15. thin film transistor (TFT) according to claim 12 or 13, wherein the metal layer further includes Part III,
The Part III and the first part and the second part are insulated from each other,
The Part III is located in the orthographic projection of the active layer on the metal layer.
16. thin film transistor (TFT) according to claim 15, wherein the Part III is configured as the grid of the transistor
Pole.
It further include gate insulating layer, grid and second insulating layer 17. thin film transistor (TFT) described in 3 or 14 according to claim 1,
Wherein, the gate insulating layer is located at side of the active layer far from the metal layer,
The grid is located at side of the gate insulating layer far from the active layer,
The second insulating layer is located at side of the grid far from the gate insulating layer.
18. a kind of electronic device substrate, including the thin film transistor (TFT) as described in claim 12-17 is any.
19. a kind of electronic device, including electronic device substrate as claimed in claim 18.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910463831.5A CN110137084B (en) | 2019-05-30 | 2019-05-30 | Thin film transistor, preparation method thereof, electronic device substrate and electronic device |
| PCT/CN2020/088117 WO2020238557A1 (en) | 2019-05-30 | 2020-04-30 | Thin film transistor and preparation method therefor, electronic apparatus substrate, and electronic apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910463831.5A CN110137084B (en) | 2019-05-30 | 2019-05-30 | Thin film transistor, preparation method thereof, electronic device substrate and electronic device |
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| CN110137084A true CN110137084A (en) | 2019-08-16 |
| CN110137084B CN110137084B (en) | 2022-07-29 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110707106A (en) * | 2019-10-29 | 2020-01-17 | 京东方科技集团股份有限公司 | Thin film transistor, preparation method and display device |
| CN110706599A (en) * | 2019-10-25 | 2020-01-17 | 深圳市华星光电技术有限公司 | Display panel and display device |
| CN111446295A (en) * | 2020-04-08 | 2020-07-24 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor, array substrate and display panel |
| WO2020238557A1 (en) * | 2019-05-30 | 2020-12-03 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method therefor, electronic apparatus substrate, and electronic apparatus |
| CN113192985A (en) * | 2021-04-23 | 2021-07-30 | 武汉华星光电技术有限公司 | TFT substrate and preparation method thereof, display panel and display device |
| US20220310665A1 (en) * | 2020-09-04 | 2022-09-29 | Tcl China Star Optoelectronics Technology Co., Ltd. | Array substrate and manufacturing method thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113745342B (en) * | 2021-08-23 | 2023-09-26 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor, manufacturing method thereof and display panel |
| KR20230056907A (en) * | 2021-10-21 | 2023-04-28 | 엘지디스플레이 주식회사 | Thin film transistor substrate and display apparatus comprising the same |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008135666A (en) * | 2006-11-29 | 2008-06-12 | Toshiba Corp | Semiconductor laminated film |
| CN105789320A (en) * | 2016-03-11 | 2016-07-20 | 深圳市华星光电技术有限公司 | Metal oxide film transistor and manufacturing method thereof as well as array substrate |
| CN106129122A (en) * | 2016-08-31 | 2016-11-16 | 京东方科技集团股份有限公司 | Oxide thin film transistor and preparation method thereof, array base palte, display device |
| CN106653767A (en) * | 2016-12-12 | 2017-05-10 | 深圳市华星光电技术有限公司 | Array substrate and fabrication method therefor |
| CN107863354A (en) * | 2017-10-20 | 2018-03-30 | 武汉华星光电技术有限公司 | Array base palte and preparation method thereof |
| CN107946244A (en) * | 2017-11-22 | 2018-04-20 | 深圳市华星光电半导体显示技术有限公司 | A kind of array base palte and preparation method thereof |
| CN109192661A (en) * | 2018-08-28 | 2019-01-11 | 合肥鑫晟光电科技有限公司 | Thin film transistor (TFT) and preparation method thereof, array substrate and display panel |
| CN109686793A (en) * | 2018-12-24 | 2019-04-26 | 合肥鑫晟光电科技有限公司 | Thin film transistor (TFT) and preparation method, array substrate, display device |
| CN109712993A (en) * | 2019-01-02 | 2019-05-03 | 南京中电熊猫平板显示科技有限公司 | Array substrate and manufacturing method and display device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101090252B1 (en) * | 2004-09-24 | 2011-12-06 | 삼성전자주식회사 | Thin film transistor array panel and method for manufacturing the same |
| CN106876481B (en) * | 2017-05-04 | 2020-11-03 | 京东方科技集团股份有限公司 | Oxide thin film transistor, manufacturing method thereof, array substrate and display device |
| CN110137084B (en) * | 2019-05-30 | 2022-07-29 | 京东方科技集团股份有限公司 | Thin film transistor, preparation method thereof, electronic device substrate and electronic device |
-
2019
- 2019-05-30 CN CN201910463831.5A patent/CN110137084B/en active Active
-
2020
- 2020-04-30 WO PCT/CN2020/088117 patent/WO2020238557A1/en active Application Filing
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008135666A (en) * | 2006-11-29 | 2008-06-12 | Toshiba Corp | Semiconductor laminated film |
| CN105789320A (en) * | 2016-03-11 | 2016-07-20 | 深圳市华星光电技术有限公司 | Metal oxide film transistor and manufacturing method thereof as well as array substrate |
| CN106129122A (en) * | 2016-08-31 | 2016-11-16 | 京东方科技集团股份有限公司 | Oxide thin film transistor and preparation method thereof, array base palte, display device |
| CN106653767A (en) * | 2016-12-12 | 2017-05-10 | 深圳市华星光电技术有限公司 | Array substrate and fabrication method therefor |
| CN107863354A (en) * | 2017-10-20 | 2018-03-30 | 武汉华星光电技术有限公司 | Array base palte and preparation method thereof |
| CN107946244A (en) * | 2017-11-22 | 2018-04-20 | 深圳市华星光电半导体显示技术有限公司 | A kind of array base palte and preparation method thereof |
| CN109192661A (en) * | 2018-08-28 | 2019-01-11 | 合肥鑫晟光电科技有限公司 | Thin film transistor (TFT) and preparation method thereof, array substrate and display panel |
| CN109686793A (en) * | 2018-12-24 | 2019-04-26 | 合肥鑫晟光电科技有限公司 | Thin film transistor (TFT) and preparation method, array substrate, display device |
| CN109712993A (en) * | 2019-01-02 | 2019-05-03 | 南京中电熊猫平板显示科技有限公司 | Array substrate and manufacturing method and display device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020238557A1 (en) * | 2019-05-30 | 2020-12-03 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method therefor, electronic apparatus substrate, and electronic apparatus |
| CN110706599A (en) * | 2019-10-25 | 2020-01-17 | 深圳市华星光电技术有限公司 | Display panel and display device |
| CN110707106A (en) * | 2019-10-29 | 2020-01-17 | 京东方科技集团股份有限公司 | Thin film transistor, preparation method and display device |
| CN111446295A (en) * | 2020-04-08 | 2020-07-24 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor, array substrate and display panel |
| US20220310665A1 (en) * | 2020-09-04 | 2022-09-29 | Tcl China Star Optoelectronics Technology Co., Ltd. | Array substrate and manufacturing method thereof |
| CN113192985A (en) * | 2021-04-23 | 2021-07-30 | 武汉华星光电技术有限公司 | TFT substrate and preparation method thereof, display panel and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110137084B (en) | 2022-07-29 |
| WO2020238557A1 (en) | 2020-12-03 |
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