CN107863354A - Array base palte and preparation method thereof - Google Patents
Array base palte and preparation method thereof Download PDFInfo
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- CN107863354A CN107863354A CN201710986111.8A CN201710986111A CN107863354A CN 107863354 A CN107863354 A CN 107863354A CN 201710986111 A CN201710986111 A CN 201710986111A CN 107863354 A CN107863354 A CN 107863354A
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- insulating barrier
- oxide semiconductor
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- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 239000010410 layer Substances 0.000 claims abstract description 208
- 230000004888 barrier function Effects 0.000 claims abstract description 60
- 239000010408 film Substances 0.000 claims abstract description 55
- 239000004065 semiconductor Substances 0.000 claims abstract description 48
- 239000000463 material Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000010409 thin film Substances 0.000 claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 239000011229 interlayer Substances 0.000 claims abstract description 22
- 239000002210 silicon-based material Substances 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 21
- 229920005591 polysilicon Polymers 0.000 claims description 17
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 6
- 239000011787 zinc oxide Substances 0.000 claims description 5
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical group O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims 1
- 229910052725 zinc Inorganic materials 0.000 claims 1
- 239000011701 zinc Substances 0.000 claims 1
- 230000008569 process Effects 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 229910004205 SiNX Inorganic materials 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- -1 boron ion Chemical class 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005984 hydrogenation reaction Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000004568 cement Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present invention discloses a kind of array base palte and preparation method thereof.Array base palte, which is included in, is provided with the first film transistor spaced a predetermined distance and being set up in parallel and the second thin film transistor (TFT) in substrate.The first film transistor includes folding the first active layer, first grid insulating barrier, first grid, interlayer insulating film and the first source/drain set on the substrate successively, and first source/drain is electrically connected with first active layer.Second thin film transistor (TFT) includes second grid, second grid insulating barrier, the second active layer, etch stop layer and the second source/drain being cascading on the substrate.First active layer and the second grid are polycrystalline silicon material, and the first grid includes oxide semiconductor material with second active layer.
Description
Technical field
The present invention relates to the manufacture technology field of array base palte in display technology field, more particularly to display.
Background technology
Display screen has been applied in the electronic installation of the production of people and the every field of life more and more widely, example
Such as mobile phone, tablet personal computer or the field of household appliances or outdoor advertising etc. such as desktop computer consumer electronics field, TV are public
Apparatus field.
Display screen is mainly that LCDs (Liquid Crystal Display, LCD) or organic light emission show at present
Display screen (Organic Light Emitting Diode, OLED).In order to improve the display effect of display, either it is applied to
Outdoor large display screen curtain or the small display screen curtain applied to consumer electronics, increasing people start notice
The narrow frame design of display device is invested, narrow frame display device can effectively reduce the area of non-display area in mosaic screen,
Screen accounting is effectively improved, significantly improves overall display effect.Thus, narrow frame turns into urgently to be resolved hurrily in current field of display
The problem of.
The content of the invention
To solve the problems, such as narrow frame, the present invention provides a kind of array base palte with reduced size.
Further, there is provided the preparation method of aforementioned array substrate.
The array base palte that the embodiment of this hair one provides, is provided with first spaced a predetermined distance and be set up in parallel in substrate
Thin film transistor (TFT) and the second thin film transistor (TFT).The first film transistor includes folding first set on the substrate successively
Active layer, first grid insulating barrier, first grid, interlayer insulating film and the first source/drain, first source/drain
It is electrically connected with first active layer.The second gate that second thin film transistor (TFT) is cascading on the substrate
Pole, second grid insulating barrier, the second active layer, etch stop layer and the second source/drain.Wherein, first active layer
It is polycrystalline silicon material with the second grid, the first grid includes oxide semiconductor material with second active layer
Material.
The array substrate manufacturing method that the embodiment of this hair one provides, including step：
Substrate is provided, and cushion is formed in substrate side；
Polysilicon layer is formed in the buffer-layer surface and is patterned, and forms the first active layer spaced a predetermined distance
With second grid；
In first active layer the exhausted of first active layer and second grid is covered with being formed on the second grid
Edge layer, the insulating barrier respectively constitute first grid insulating barrier and second grid insulating barrier；
Set on the first grid insulating barrier and the second grid insulating barrier oxide semiconductor material layer and
Patterned, wherein, the corresponding oxide semiconductor material for covering the first grid insulating barrier forms first layer by layer
Grid；The corresponding oxide semiconductor material layer for covering the second grid insulating barrier forms the second active layer；
Insulating barrier is formed on the first grid and second active layer, wherein, the institute of the corresponding first grid
State insulating barrier and form interlayer insulating film, the insulating barrier of corresponding second active layer forms the etch stop layer；
In the interlayer insulating film with forming metal level on the etch stop layer and being patterned, wherein, it is corresponding
The first grid position forms the first source/drain, and first source/drain electrically connects with first active layer
Connect, first active layer, the first grid insulating barrier, the first grid, the interlayer insulating film and described first
Source/drain forms first film transistor；The corresponding second grid position forms the second source/drain, and described second
Source/drain is electrically connected with second active layer, and the second grid, the second grid insulating barrier, described second have
Active layer, etch stop layer and second source/drain form the second thin film transistor (TFT).
Compared to prior art, first film transistor is synchronously made with the second thin film transistor (TFT), it is therefore not necessary to single
The second thin film transistor (TFT) being solely directed in drive circuit is individually made, and improves producing efficiency.
Further, it is smaller that the channel size of the second thin film transistor (TFT) of active layer is formed using oxide semiconductor, so as to
So that the space that thin film transistor (TFT) takes in each pixel cell reduces, the chi of viewing area in display panel is then effectively increased
It is very little and improve aperture opening ratio, and be used as in non-display area by the first film transistor of polysilicon in drivingly circuit and made
For the thin film transistor (TFT) of switch, so that scan drive circuit or data drive circuit size is smaller and fast response time,
Then so that non-display area size further reduces, so as to reach the purpose for improving screen accounting and realizing narrow frame.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is display device dimensional structure diagram in one embodiment of the invention.
Fig. 2 is the planar structure schematic diagram of array base palte in display panel shown in Fig. 1.
Fig. 3 is the side structure schematic diagram of array base palte as shown in Figure 1, 2.
Fig. 4 is side structure schematic diagram corresponding to each step in the manufacturing process of array base palte as shown in Figure 3.
Fig. 5 is the Making programme figure of array base palte as shown in Figure 3.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
Below in conjunction with the accompanying drawings, the embodiment of array base palte of the present invention is illustrated.
Referring to Fig. 1, Fig. 1 is display device dimensional structure diagram in one embodiment of the invention.As shown in figure 1, display
Device 100 includes display panel 10 and other supplementary structure (not shown), wherein, shown supplementary structure includes housing and tied with support
Structure.
Display panel 10 includes image viewing area 10a and non-display area 10b.Viewing area 10a is shown as image, non-aobvious
Show that area 10b around being arranged at around the 10a of viewing area and being used as non-outgoing area, is not used as image and shown.Wherein, display panel
10 also include array base palte 10c and opposite substrate 10d, and are located in array base palte 10c and opposite substrate 10d display Jie
Matter layer 10e.In the present embodiment, display medium is organic luminous semiconductor material (Organic Electroluminescence
Diode, OLED).Certainly, during in the present invention, other change embodiments, the display panel 10 in display device 100 can be with liquid crystal
Material is not limited thereto as display medium.For convenience of description, first define by orthogonal first direction X, second party
The three-dimensional cartesian coordinate system formed to Y and third direction Z.Wherein, display device 100 along third direction Z be its thickness side
To.
Referring to Fig. 2, it is the planar structure schematic diagram of array base palte 10c in display panel 10 shown in Fig. 1.Such as Fig. 2 institutes
Show, correspondence image viewing area 10a first area (not indicating) includes multiple m*n pictures arranged in arrays in array base palte 10c
Plain unit (Pixel) 110, m bars (Data Line) data wire (Scan Line) 120 and n bars scan line 130, m, n be more than
1 natural number.
Wherein, a plurality of data lines 120 Y intervals the first preset distance mutually insulated and arranged in parallel in the first direction, should
X is also spaced the second preset distance mutually insulated and arranged in parallel, and the multi-strip scanning to multi-strip scanning line 130 in a second direction
Line 130 and the mutually insulated of a plurality of data lines 120, the first direction X and second direction Y are mutually perpendicular to.For purposes of illustration only, institute
State m data lines 120 be respectively defined as D1, D2 ..., Dm-1, Dm；The n bars scan line 130 be respectively defined as G1,
G2 ..., Gn-1, Gn.The square that multiple pixel cells 110 are formed positioned at a plurality of data lines 120, scan line 130 respectively
In battle array, and it is electrically connected with corresponding wherein data wire 120 and scan line 130.
The non-display area 10b of corresponding display panel 10, display device 100 (Fig. 1) further comprise being arranged at non-display area
The 10b pixel cell 110 for being used to drive multiple matrix arrangements carries out control circuit 101, the data drive circuit that image is shown
(Data Driver) 102 and scan drive circuit (Scan Driver) 103, it is arranged at array base palte 11c second area
(not indicating).Wherein, data drive circuit 102 is electrically connected with a plurality of data lines 120, for by picture number to be shown
Transmitted according to by a plurality of data lines 120 in the form of data voltage to the plurality of pixel cell 110.Scan drive circuit 103
For being electrically connected with the multi-strip scanning line 130, it is used to control pixel for exporting scanning signal by the multi-strip scanning line 130
When unit 110, which receives view data progress image, shows.Control circuit 101 is driven with data drive circuit 102 and scanning respectively
Dynamic circuit 103 is electrically connected with, and for control data drive circuit 102 and the work schedule of scan drive circuit 103, that is to say defeated
Go out corresponding timing control signal to data drive circuit 102 and scan drive circuit 103.
In the present embodiment, scan drive circuit 103 is directly arranged at the non-display area 10b of display panel 10, control circuit
101 are then arranged on other bearer circuit plate plates with data drive circuit 102 independently of array base palte 10c.In the present embodiment,
Circuit element in scan drive circuit 103 is made in display panel with the 110 same processing procedure of pixel cell in display panel 10
In 10, GOA (Gate on Array) technology that is to say.
Referring to Fig. 3, its side structure schematic diagram for array base palte as shown in Figure 1, 2.
As shown in figure 3, array base palte 10c includes substrate 11, the substrate 11 is by materials such as the glass of transparent material, plastic cement
Form.Substrate 11 includes relative first surface 111 and second surface 112.It is provided with the first surface 111 along first
Direction X is spaced a predetermined distance and the first film transistor T1 and the second thin film transistor (TFT) T2 that are set up in parallel.Wherein, first direction
X and the equal place planes of parallel substrate 11 of second direction Y.
It should be noted that in the present embodiment, first film transistor T1 is the polysilicon active layer that low temperature process makes
Thin film transistor (TFT) (Low Temperature Poly-silicon, LTPS), the second thin film transistor (TFT) T2 are oxide semiconductor
Thin film transistor (TFT), for example, indium gallium zinc oxide as active layer thin film transistor (TFT) (Indium Gallium Zinc Oxide,
IGZO).First film transistor T1 is located in scan drive circuit 103 or data drive circuit 102, for for viewing area
Each pixel cell 110 in 10a is scanned or provided data-signal.Second thin film transistor (TFT) T2 is positioned at each picture
It is electrically connected with plain unit 110 and with pixel electrode Px and drives pixel electrode Px to carry out image and shows.
It is provided with cushion 12 in substrate 11, cushion 12 includes the to be cascading along third direction Z respectively
One sub- 121 and second sub- cushion 122 of cushion, that is to say that first buffer layer 121 is arranged at the first surface 111 of substrate 11,
Second sub- cushion 122 is then arranged at the first sub- surface of the cushion 121 away from first surface 111.Wherein, the first sub- cushion
121 be silica (SiOx) film layer, and the second sub- cushion is silicon nitride (SiNx) film layer.
Specifically, the thickness of the silicon nitride and silicon oxide stack is 50~100nm.And for example, silicon nitride layer and silica
The thickness proportion of layer is 1~1.5：0.8~1.6；For example, the thickness proportion of silicon nitride layer and silicon oxide layer is 1：1.For example, oxygen
The thickness of SiClx layer is 20~60nm.Wherein, the reacting gas for forming SiNx film layers is SiH4, NH3, N2 mixed gas, or
Person is SiH2Cl2, NH3, N2 mixed gas；The reacting gas for forming SiOx film layers is SiH4, N2O mixed gas, or
For SiH4, silester (TEOS) mixed gas.
First film transistor T1 folds the first active layer 131 set, the successively from the surface of cushion 12 along third direction Z
One gate insulator 132, first grid 133, the source/drain 135 of interlayer insulating film 134 and first, wherein, the first source electrode/
Drain electrode 135 is electrically connected with by first through hole H1 and the first active layer electricity 131 respectively.Specifically, in the first source/drain 135
The first source electrode 1351 and the first drain electrode 1352 respectively positioned at the X along a first direction of first grid 133 both sides, and pass through two
First through hole H1 is respectively and electrically connected to the first active layer 131 X along a first direction opposite sides.Second thin film transistor (TFT) T2
Including having from the surface of cushion 12 along the third direction Z successively folded second grid 151 set, second grid insulating barrier 152, second
Active layer 153, the source/drain 155 of etch stop layer 154 and second.Specifically, to be covered in second active for etch stop layer 154
Layer 153, and in corresponding second active layer 153 X along a first direction the second through hole H2 for setting of opposite sides.Accordingly,
Second source/drain 155 includes the second source electrode 1551 and the second drain electrode that X along a first direction is set spaced a predetermined distance
1552, it is respectively and electrically connected to the second active layer 153 by two the second through hole H2.
It is preferred that the first active layer 131 is located at same layer structure with second grid 151 and made in same processing procedure
Into, and material is the polysilicon (p-Si) made using low temperature process.It is preferred that the polycrystalline silicon material of the first active layer 131
In include channel dopants so that first film transistor T1 has shut-off special efficacy faster；Second grid 151
Include conductive dopant in polycrystalline silicon material, so that the second thin film transistor (TFT) T2 conductive characteristic is preferable.
It is preferred that first grid 133 includes the first oxide semiconductor layer I1 being disposed adjacent with the second active layer 153
With the second oxide semiconductor layer I2, wherein, the first oxide semiconductor layer I1 second oxide semiconductor layers
The direction of I2 adjacent substrates 11.In the present embodiment, the first oxide semiconductor layer I1 material is indium gallium zinc oxide (IGZO),
Second oxide semiconductor layer I2 material is tin indium oxide (ITO).
Second active layer 153 using oxide semiconductor material due to being formed, so as to form the second thin film transistor (TFT) T2 then
For IGZO/ITO thin film transistor (TFT)s, it is used as driving thin film transistor (TFT) in pixel cell 110 (Fig. 2), due to IGZO film
Transistor is smaller with dimension volume and with the higher threshold voltage vt h of stability, and then causes the second thin film transistor (TFT) T2
Stability is preferable.Interlayer insulating film 134 is located at same layer structure with etch stop layer 154 and completed in same processing procedure,
And it is silica (SiOx) material or silicon nitride (SiNx).
First source/drain 135 and the second source/drain 155 are aluminium or titanium material.Wherein, the first source electrode/
The source/drain 155 of drain electrode 135 and second is by for being formed at the layer interlayer insulating film 134, the table of etch stop layer 154
The aluminium or titanium coating in face carry out patterning formation.
It is preferred that the first active layer 131 is the polysilicon material of phosphorus (P) doping so that first film transistor T1 is formed
For top-gated pole (Top Gate) P-type TFT.Second active layer 154 is the oxide semiconductor of nitrogen (N) doping so that the
Two-transistor T2 forms bottom-gate (Bottom Gate) N-type TFT.
Compared to prior art, the first film transistor T1 that driving is used as in pixel cell 110 is non-display with being arranged on
The second thin film transistor (TFT) T2 in drive circuit in area 10b is synchronously made, it is therefore not necessary to individually in drive circuit
The second thin film transistor (TFT) T2 individually made, improve producing efficiency.
Meanwhile the channel size that the second thin film transistor (TFT) T2 of active layer is formed using oxide semiconductor is smaller, so as to
So that the space that thin film transistor (TFT) takes in each pixel cell reduces, viewing area in display panel 10 is then effectively increased
10a size and aperture opening ratio is improved, and drive is used as by the first film transistor T1 of polysilicon in non-display area 10b
As the thin film transistor (TFT) switched in dynamic ground circuit so that scan drive circuit or data drive circuit size it is smaller and
Fast response time, then non-display area 10b sizes are further reduced, so as to reach the mesh for improving screen accounting and realizing narrow frame
's.
Referring to Fig. 4, it shows for side structure corresponding to each step in array base palte 10c as shown in Figure 3 manufacturing process
It is intended to, Fig. 5 is the Making programme figure of array base palte as shown in Figure 3.Array base palte 10c system is illustrated with reference to Fig. 3-5
Make step.
Step 401, as shown in the 4a in Fig. 4, there is provided substrate 11, and the first surface 111 in the side of substrate 11 is formed
Cushion 12.
It is preferred that deposit one layer using plasma chemical vapor deposition (PECVD) on the first surface of substrate 11
Certain thickness first sub- 121 and second sub- cushion 122 of cushion, for example, the certain thickness is 50~100nm.Wherein,
Deposition materials for the first sub- cushion 121 can be silica (SiOx) film layer, for the deposition of the second sub- cushion 122
Material can be silicon nitride (SiNx) film layer.Step 402, as shown in the 4b in Fig. 4, formed on the second sub- surface of cushion 122
Polysilicon layer is simultaneously patterned, along a first direction the first active layer 131 and second grid of X-shaped preset distance at interval
151。
Specifically, after the substrate 11 for having cushion 12 for deposition is cleaned by DGH, using plasma enhancingization
Vapour deposition (PECVD) technique deposition of amorphous silicon layers on surface of the cushion 12 away from substrate is learned, irradiated followed by laser,
Quasi-molecule laser annealing (Excimer Laser Annel, ELA) and lithographic process cause the amorphous silicon layer to be changed into it
Polysilicon layer.Wherein, for depositing temperature general control below 500 DEG C, the thickness of amorphous silicon layer is 40nm~50nm.Certainly,
It can be needed to select suitable thickness according to specific technique.
Then it is doped and patterns for the polysilicon layer.Wherein, the patterning can use dry etching
(dry etching) and peel off the completion of (Strip) processing procedure.
Then, in polysilicon layer by way of boron ion injects (B implantation) using ion implantation doping
Position corresponding to (CD ion implantation doping, CD IMP) carries out channel doping, that is to say with semiconductor
The boron ion of characteristic is doped into polysilicon layer, at the polysilicon layer being directed to using NP photoetching and annealing process after doping
Reason, so as to form the first active layer 131.Thus, channel dopants are included in the polycrystalline silicon material of the first active layer 131, from
And cause first film transistor T1 that there is shut-off special efficacy faster.
(NPion by way of (B implantation) uses ion implantation doping is injected boron ion in polysilicon layer
Implantation doping, NP IMP) corresponding to position carry out conductive material doping, that is to say the material with conductor characteristics
Matter is doped into polysilicon layer, so as to form second grid 151.Thus, include in the polycrystalline silicon material of second grid 151 and lead
Electrically doped thing, so that the second thin film transistor (TFT) T2 conductive characteristic is preferable.It is described patterned by patterning processes, to more
Crystal silicon layer carries out partial etching, so as to form patterned first active layer 131 and second grid 151 on polysilicon layer.Preferably
Ground, the first active layer 131 is completed with after second grid 151, performing ashing (ashing) to it and peeling off processing procedure.This implementation
In example, the wet-etching technology of prior art or dry etch process can be used to realize the etching of polysilicon layer.
Step 403, as shown in the 4c in Fig. 4, on the first active layer 131 and the surface of second grid 151 along third direction Z
Insulating barrier is formed, the insulating barrier respectively constitutes first grid insulating barrier 132 and second grid insulating barrier 152.It that is to say correspondingly
The insulating barrier of the position of first active layer 131 forms first grid insulating barrier 132, the insulation of the corresponding position of second grid 152
Layer composition second grid insulating barrier 152.
Specifically, the surface of corresponding first active layer 131 and second grid 151 is certain thickness using CVD process deposits
Silicon nitride (SiNx) and/or membranous layer of silicon oxide (SiOx).It is preferred that formed in the first active layer 131 and the surface of second grid 151
Before insulating barrier, it has been correspondingly formed the first active layer 131 and has carried out DHF cleanings with second grid 151, and in the first active layer
131 after the surface of second grid 151 formation insulating barrier with being ashed, cleaning treatment.
Step 404, as shown in the 4d in Fig. 4, in the first grid insulating barrier 132 and the second grid insulating barrier
Oxide semiconductor material layer is set on 152 and patterned.Wherein, it is corresponding to cover the first grid insulating barrier 132
The oxide semiconductor material form first grid 133 layer by layer；It is corresponding to cover the described of the second grid insulating barrier 152
Oxide semiconductor material layer forms the second active layer 153.
In the present embodiment, it is preferred that first grid 133 aoxidizes with the second active layer 153 comprising first be disposed adjacent
Thing semiconductor layer I1 and the second oxide semiconductor layer I2, wherein, the first oxide semiconductor layer I1 second oxygen
The direction of compound semiconductor layer I2 adjacent substrates 11.In the present embodiment, the first oxide semiconductor layer I1 material is indium gallium zinc
Oxide (IGZO), the second oxide semiconductor layer I2 material is tin indium oxide (ITO)
Specifically, IGZO materials are used into splash (sputter) mode in first grid insulating barrier 132 and second grid
The surface of insulating barrier 152 forms IGZO film layers, and ITO materials then are deposited on into the IGZO film surfaces again forms ito film layer, then
Patterned by patterning processes for IGZO film layers with ito film layer, so as to form the first oxide semiconductor layer I1 and
Dioxide semiconductor layer I2.Wherein, the first oxide semiconductor layer I1 and second that includes of corresponding first active layer 131 is aoxidized
Thing semiconductor layer I2 first grid 133 is used as conductive electrode；Corresponding second grid 151 includes the first oxide semiconductor layer
I1 and the second oxide semiconductor layer I2 the second active layer 153 is used as conducting channel.
It is preferred that formed after first grid 133, by ion implanting in X pairs along a first direction of the first active layer 131
The opposite sides of first grid 133 is answered to form source-drain area respectively.
It is preferred that the patterning can be completed by dry etching (dry etching) and stripping processing procedure, and in shape
, it is necessary to carry out active annealing process (Activation after into the active layer 153 of first grid 133 and second
) and manufacturing process for cleaning Anneal.Step 405, as shown in the 4e in Fig. 4, in the first grid 133 and second active layer
Insulating barrier is formed on 153, wherein, the insulating barrier of the corresponding first grid 133 forms interlayer insulating film 134, corresponding institute
The insulating barrier for stating the second active layer 153 forms the etch stop layer 154.
Specifically, use CVD techniques first grid insulating barrier 132, first grid 133, second grid insulating barrier 152 with
And second deposit certain thickness silica (SiOx) or silicon nitride (SiNx) film on surface of the active layer 153 away from substrate 11
Layer, to be used as the insulating barrier.Certainly, the insulating barrier of the corresponding first grid 133 forms interlayer insulating film 134, right
The insulating barrier of second active layer 153 is answered to form the etch stop layer 154.
It is preferred that formed on the second active layer 153 after etch stop layer 154, it is active second by ion implanting
X corresponds to the opposite sides of second grid 151 and forms source-drain area respectively layer 154 along a first direction.
Simultaneously, it is necessary to which explanation, after forming interlayer insulating film 134, continues corresponding first active layer 131 in the first direction
The opposite sides that X corresponds to first grid 133 corresponds to the position of source-drain area to form first by dry etching or wet etching mode respectively logical
Hole H1, the through hole is through interlayer insulating film 134 and first grid insulating barrier 132, so that the first active layer of part 131 is certainly
First through hole H1 is revealed.After forming etch stop layer 154, continue the relative of corresponding second active layer 153 X in the first direction
The position that both sides correspond to source-drain area forms the second through hole H2 respectively, and the through hole runs through etch stop layer 154, so that part
Second active layer 153 reveals from the second through hole H2.
It is preferred that hydrogenation annealing process is performed after the interlayer insulating film 134 and etch stop layer 154 is formed
(Hydrogenation Anneal), with repair the defects of the first active layer 131 and polycrystalline silicon material in second grid 151 with
And solidification crystal boundary.
Step 406, as shown in the 4f in Fig. 4, in the interlayer insulating film 134 with being formed on the etch stop layer 155
Aluminium either titanium coating and carry out dry etching or etching mode patterning.Wherein, the first grid is corresponded to along first party
The first source/drain 135 is formed to the position of X both sides, and first source/drain 135 and first active layer 131 are logical
Cross first through hole H1 electric connections.Thus, first active layer 131, the first grid insulating barrier 132, the first grid
Pole 133, the interlayer insulating film 134 and first source/drain 135 form first film transistor T1.
The position of the corresponding second grid 151 X both sides along a first direction forms the second source/drain 155, and described
Second source/drain 155 is electrically connected with second active layer 153 by the second through hole H2.The second grid 151, institute
State second grid insulating barrier 152, second active layer 153, etch stop layer 154 and the structure of the second source/drain 155
Into the second thin film transistor (TFT) T2.It is appreciated that pixel electrode (not shown) subsequently is also formed with the second source/drain 135,
Wherein, the second source electrode 1351 or the second drain electrode 1352 are electrically connected with pixel electrode (not shown).
Embodiments described above, the restriction to the technical scheme protection domain is not formed.It is any in above-mentioned implementation
Modifications, equivalent substitutions and improvements made within the spirit and principle of mode etc., should be included in the protection model of the technical scheme
Within enclosing.
Claims (10)
1. a kind of array base palte, it is characterised in that the first film spaced a predetermined distance and being set up in parallel is provided with substrate
The thin film transistor (TFT) of transistor AND gate second, wherein：
The first film transistor, which includes folding successively, sets the first active layer on the substrate, first grid insulating barrier, the
One grid, interlayer insulating film and the first source/drain, first source/drain are electrically connected with first active layer；
Second thin film transistor (TFT) include being cascading second grid on the substrate, second grid insulating barrier,
Second active layer, etch stop layer and the second source/drain；
First active layer and the second grid are polycrystalline silicon material, the first grid and the second active layer bag
Oxycompound semi-conducting material.
2. array base palte according to claim 1, it is characterised in that the first grid wraps with second active layer
Containing the first oxide semiconductor layer and the second oxide semiconductor layer being disposed adjacent, first oxide semiconductor layer is compared
Second oxide semiconductor layer aoxidizes close to the substrate, the material of first oxide semiconductor layer for indium gallium zinc
Thing, the material of second oxide semiconductor layer is tin indium oxide.
3. array base palte according to claim 1, it is characterised in that the substrate surface is additionally provided with cushion, described
First active layer may be contained within surface of the cushion away from the substrate with the second grid.
4. array base palte according to claim 1, it is characterised in that first active layer is located at the second grid
Same layer structure and completed in same processing procedure, include channel doping in the polycrystalline silicon material of first active layer
Thing, include conductive dopant in the polycrystalline silicon material of the second grid.
5. array base palte according to claim 4, it is characterised in that the interlayer insulating film insulate with the second grid
Layer is silica material, and the interlayer insulating film is located at same layer structure and in same system with the second grid insulating barrier
Completed in journey.
6. array base palte according to claim 5, it is characterised in that the first grid insulating barrier insulate with second grid
Layer is set and is connected with each other with layer so as to form the insulating barrier of one layer of covering, first active layer and second grid.
7. according to the array base palte described in claim 1-6 any one, it is characterised in that the first film transistor is P
Type thin film transistor (TFT), second thin film transistor (TFT) are N-type TFT, and the second thin film transistor (TFT) of institute is shown with carrying out image
Pixel electrode be directly connected to, for drive pixel electrode carry out image show.
8. a kind of array substrate manufacturing method, it is characterised in that including step：
Substrate is provided, and cushion is formed in substrate side；
Form polysilicon layer in the buffer-layer surface and carry out patterning and form the first active layer spaced a predetermined distance and the
Two grids；
The insulating barrier for covering first active layer and second grid is formed on first active layer and the second grid,
The insulating barrier includes first grid insulating barrier and second grid insulating barrier；
In the first grid insulating barrier with setting oxide semiconductor material layer on the second grid insulating barrier and carrying out
Patterning, wherein, the corresponding oxide semiconductor material for covering the first grid insulating barrier forms first grid layer by layer；
The corresponding oxide semiconductor material layer for covering the second grid insulating barrier forms the second active layer；
Insulating barrier is formed on the first grid and second active layer, wherein, correspond to the described exhausted of the first grid
Edge layer forms interlayer insulating film, and the insulating barrier of corresponding second active layer forms the etch stop layer；And
In the interlayer insulating film with forming metal level on the etch stop layer and being patterned, wherein, described in correspondence
First grid position forms the first source/drain, and first source/drain is electrically connected with first active layer, institute
State the first active layer, the first grid insulating barrier, the first grid, the interlayer insulating film and first source electrode/
Drain electrode forms first film transistor；The position of the corresponding second grid forms the second source/drain, and second source
Pole/drain electrode and second active layer are electrically connected with, the second grid, the second grid insulating barrier, described second active
Layer, etch stop layer and second source/drain form the second thin film transistor (TFT).
9. the preparation method of array base palte according to claim 8, it is characterised in that the first grid and described second
Active layer is comprising the first oxide semiconductor layer and the second oxide semiconductor layer being disposed adjacent, first oxide half
For conductor layer compared to second oxide semiconductor layer close to the substrate, the material of first oxide semiconductor layer is indium
Gallium zinc oxide, the material of second oxide semiconductor layer is tin indium oxide.
10. the preparation method of array base palte according to claim 8, it is characterised in that first active layer with it is described
Second grid is located at same layer structure and completed in same processing procedure, is included in the polycrystalline silicon material of first active layer
Have channel dopants, include conductive dopant in the polycrystalline silicon material of the second grid, first active layer with it is described
Second grid is polycrystalline silicon material, and the interlayer insulating film and the etch stop layer are silica or silicon nitride material
Material.
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| CN201710986111.8A CN107863354A (en) | 2017-10-20 | 2017-10-20 | Array base palte and preparation method thereof |
| PCT/CN2018/073972 WO2019075950A1 (en) | 2017-10-20 | 2018-01-24 | Array substrate and manufacturing method therefor |
| US16/082,642 US10998342B2 (en) | 2017-10-20 | 2018-01-24 | Array substrate and manufacturing method thereof |
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| CN108598087A (en) * | 2018-04-26 | 2018-09-28 | 京东方科技集团股份有限公司 | Array substrate and its manufacturing method, display panel, electronic device |
| CN110098201A (en) * | 2019-05-16 | 2019-08-06 | 合肥京东方光电科技有限公司 | Transistor device and its manufacturing method, display base plate, display device |
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| CN112331678A (en) * | 2020-11-03 | 2021-02-05 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof, display panel and display device |
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| US10998342B2 (en) | 2021-05-04 |
| US20200295052A1 (en) | 2020-09-17 |
| WO2019075950A1 (en) | 2019-04-25 |
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Application publication date: 20180330 |
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