CN106992189A - The preparation method of oxide semiconductor TFT substrate structure and oxide semiconductor TFT substrate - Google Patents
The preparation method of oxide semiconductor TFT substrate structure and oxide semiconductor TFT substrate Download PDFInfo
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- CN106992189A CN106992189A CN201710261221.8A CN201710261221A CN106992189A CN 106992189 A CN106992189 A CN 106992189A CN 201710261221 A CN201710261221 A CN 201710261221A CN 106992189 A CN106992189 A CN 106992189A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 113
- 239000000758 substrate Substances 0.000 title claims abstract description 75
- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 165
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 93
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 43
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 43
- 239000011241 protective layer Substances 0.000 claims abstract description 39
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 39
- 239000010408 film Substances 0.000 claims description 89
- 239000000463 material Substances 0.000 claims description 39
- 239000000377 silicon dioxide Substances 0.000 claims description 27
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 24
- 229910052750 molybdenum Inorganic materials 0.000 claims description 24
- 239000011733 molybdenum Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 16
- 239000012212 insulator Substances 0.000 claims description 15
- 239000010409 thin film Substances 0.000 claims description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- 239000004411 aluminium Substances 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 238000009413 insulation Methods 0.000 claims description 9
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 8
- 229910052733 gallium Inorganic materials 0.000 claims description 8
- 229910052738 indium Inorganic materials 0.000 claims description 8
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 239000011787 zinc oxide Substances 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000003197 catalytic effect Effects 0.000 claims description 3
- 239000012528 membrane Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 abstract description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 10
- 238000001764 infiltration Methods 0.000 description 8
- 230000008595 infiltration Effects 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229910003978 SiClx Inorganic materials 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000007323 disproportionation reaction Methods 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
Abstract
The preparation method that the present invention provides a kind of oxide semiconductor TFT substrate structure and oxide semiconductor TFT substrate.The oxide semiconductor TFT substrate structure setting matcoveredn (5) of the present invention, the protective layer (5) at least includes the first silicon oxide film layer (51), and the silicon nitride film layer (52) of covering first silicon oxide film layer (51), silicon nitride film layer (52) has good compactness, so that the ability of protective layer (5) the isolation steam is improved, it can be permeated from the top isolation steam of TFT substrate, preferably protecting oxide semiconductor active layer (33) not invaded by steam is influenceed, the electrology characteristic of steady oxide semiconductor TFT (T).
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of oxide semiconductor TFT substrate structure and oxide half
The preparation method of conductor TFT substrate.
Background technology
Flat display apparatus has many merits such as thin fuselage, power saving, radiationless, is widely used.It is existing
Flat display apparatus mainly includes liquid crystal display device (Liquid Crystal Display, LCD) and organic electroluminescent is aobvious
Showing device (Organic Light Emitting Display, OLED).
Liquid crystal display device on existing market is largely backlight liquid crystal display device, and it includes housing, located at shell
Internal liquid crystal panel and the backlight module (Backlight Module) in housing.The structure of liquid crystal panel is color by one
Colo(u)r filter substrate (Color Filter, CF), a thin-film transistor array base-plate (Thin Film Transistor Array
Substrate, TFT Array Substrate) and one it is configured at liquid crystal layer (Liquid Crystal between two substrates
Layer) constituted, its operation principle is to control the rotation of the liquid crystal molecule of liquid crystal layer by applying driving voltage on two substrates
Turn, the light of backlight module is reflected into generation picture.
Organic electroluminescence display device and method of manufacturing same needs also exist for TFT substrate, using TFT as switch block and driving part, and
The dot structure arranged in array is produced in TFT substrate.
TFT is used as with oxide semiconductor (such as indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO))
The technology of active layer be current hot technology.Oxide semiconductor has higher electron mobility, good shut-off special
Property, and compared to low temperature polycrystalline silicon (Low Temperature Poly Silicon, LTPS), the letter of oxide semiconductor processing procedure
It is single, it is higher with non-crystalline silicon process-compatible, so oxide semiconductor is increasingly becoming the head of TFT active layer in LCD and OLED
Material selection.But, oxide semiconductor thin-film is due to its architectural characteristic, it is easy to is polluted by extraneous steam, causes TFT's
Electrology characteristic deteriorates, and causes display picture the spot (mura) of brightness disproportionation occur or other bad.
Prior art is easy by steam or other pollutant effects the problem of institute to solve oxide semiconductor active layer
The method taken is the bottom increase cushion in TFT substrate to completely cut off steam infiltration, but is due to the protection on TFT substrate top
Layer is usually silica (SiOx) film of individual layer, and compactness is poor, it is impossible to stop that steam is invaded from TFT substrate top.
The content of the invention
It is an object of the invention to provide a kind of oxide semiconductor TFT substrate structure, can from the top of TFT substrate every
Exhausted steam infiltration, preferably protecting oxide semiconductor active layer not invaded by steam is influenceed, steady oxide semiconductor TFT
Electrology characteristic.
Another object of the present invention is to provide a kind of preparation method of oxide semiconductor TFT substrate, obtained oxidation
The bottom of thing semiconductor TFT substrate can completely cut off steam infiltration with top, protect oxide semiconductor active layer not by steam
The influence of intrusion so that oxide semiconductor TFT electrology characteristic is stable.
To achieve the above object, present invention firstly provides a kind of oxide semiconductor TFT substrate structure, including substrate base
Plate, the cushion of the covering underlay substrate, the oxide semiconductor TFT being located on the cushion, the covering oxide
The protective layer of semiconductor TFT and the pixel electrode being located on the protective layer；
The protective layer at least includes the silicon nitride of the first silicon oxide film layer and covering first silicon oxide film layer
Film layer.
The protective layer also includes the second silicon oxide film layer for covering the silicon nitride film layer.
The oxide semiconductor TFT includes the grid, the covering grid and cushion being located on the cushion
Gate insulator, the oxide semiconductor active layer corresponding to being located above grid on gate insulator, the covering oxidation
Etch stop layer in the middle part of thing semiconductor active layer and source electrode and the leakage for contacting the oxide semiconductor active layer both sides respectively
Pole；
Via, leakage of the pixel electrode through the via catalytic oxidation thing semiconductor TFT are offered in the protective layer
Pole.
The thickness of first silicon oxide film layer isThe thickness of the silicon nitride film layer
ForThe thickness of second silicon oxide film layer is
The material of the cushion is the stacked combination of silica, silicon nitride or silica and silicon nitride；The grid
Material is the stacked combination or molybdenum and the stacked combination of copper of molybdenum and aluminium；The material of the gate insulator is silica, and thickness isThe material of the oxide semiconductor active layer is indium gallium zinc oxide, and thickness isThe material of the etch stop layer is silica；The source electrode and the layer that the material of drain electrode is molybdenum and aluminium
Stacked group conjunction or the stacked combination of molybdenum and copper.
The present invention also provides a kind of preparation method of oxide semiconductor TFT substrate, including：
Underlay substrate, the buffer layer on the underlay substrate are provided；
Oxide semiconductor TFT is produced on the cushion；
The first silicon oxide film layer, redeposited silicon nitride film layer, described are deposited on the oxide semiconductor TFT
Oxide film layer is collectively forming protective layer with silicon nitride film layer；Via is opened up in protective layer；
Layer of conductive film is deposited on the protective layer, and patterned process is carried out to this layer of conductive film, picture is formed
Plain electrode.
The preparation method of the oxide semiconductor TFT substrate, which is additionally included on silicon nitride film layer, deposits the second silica
Film layer；The protective layer also includes second silicon oxide film layer.
The process that oxide semiconductor TFT is produced on the cushion is in chronological sequence sequentially specifically included：
The first metal layer is deposited on the cushion, and patterned process is done to the first metal layer, grid is formed；
Deposit gate insulator；
Deposition oxide semiconductive thin film, and patterned process is done to oxide semiconductor thin-film, corresponding to the upper of grid
It is square into oxide semiconductor active layer；
One layer of insulation film is deposited, and patterned process is carried out to this layer of insulation film, is formed and covers the oxide half
Etch stop layer in the middle part of conductor active layer；
Depositing second metal layer, and patterned process is done to second metal layer, formation contacts the oxide and partly led respectively
The source electrode of body active layer both sides and drain electrode.
The thickness of first silicon oxide film layer isThe thickness of the silicon nitride film layer
ForThe thickness of second silicon oxide film layer is
The material of the cushion is the stacked combination of silica, silicon nitride or silica and silicon nitride；First gold medal
It is molybdenum and the stacked combination or molybdenum and the stacked combination of copper of aluminium to belong to the material of layer；The material of the gate insulator is silica,
Thickness isThe material of the oxide semiconductor thin-film is indium gallium zinc oxide, and thickness isThe material of the insulation film is silica；The material of the second metal layer is the stacking of molybdenum and aluminium
Combination or the stacked combination of molybdenum and copper.
Beneficial effects of the present invention：A kind of oxide semiconductor TFT substrate structure that the present invention is provided, partly leads in oxide
The top of body TFT substrate sets protective layer, and the protective layer at least includes the first silicon oxide film layer and covers first oxygen
The silicon nitride film layer of SiClx film layer, silicon nitride film layer has good compactness so that the protective layer completely cuts off steam
Ability improve, can preferably protect oxide semiconductor active layer not by water from the top of TFT substrate isolation steam infiltration
The influence of vapour intrusion, the electrology characteristic of steady oxide semiconductor TFT.A kind of oxide semiconductor TFT bases that the present invention is provided
The preparation method of plate, being made in the bottom of oxide semiconductor TFT substrate has cushion, and top, which makes, to be had at least by the first oxidation
The protective layer that silicon membrane layer is collectively forming with silicon nitride film layer, makes the bottom of final obtained oxide semiconductor TFT substrate
Steam infiltration can be completely cut off with top, protecting oxide semiconductor active layer not invaded by steam is influenceed, so that oxygen
The electrology characteristic of compound semiconductor TFT is stable.
Brief description of the drawings
In order to be able to be further understood that the feature and technology contents of the present invention, refer to below in connection with the detailed of the present invention
Illustrate and accompanying drawing, however accompanying drawing only provide with reference to and explanation use, not for being any limitation as to the present invention.
In accompanying drawing,
Fig. 1 is the schematic diagram of the first embodiment of the oxide semiconductor TFT substrate structure of the present invention；
Fig. 2 is the schematic diagram of the second embodiment of the oxide semiconductor TFT substrate structure of the present invention；
Fig. 3 is the flow chart of the preparation method of the oxide semiconductor TFT substrate of the present invention.
Embodiment
Further to illustrate the technological means and its effect of the invention taken, below in conjunction with being preferable to carry out for the present invention
Example and its accompanying drawing are described in detail.
The present invention provides a kind of oxide semiconductor TFT substrate structure.Fig. 1 show the oxide semiconductor of the present invention
The first embodiment of TFT substrate structure, including underlay substrate 1, the cushion 2 of the covering underlay substrate 1, it is located at the buffering
Oxide semiconductor TFT T, covering oxide semiconductor TFT T protective layer 5 on layer 2 and it is located at the protection
Pixel electrode 6 on layer 5.
The protective layer 5 at least includes the first silicon oxide film layer 51 and covers first silicon oxide film layer 51
Silicon nitride (SiNx) film layer 52.
Specifically：
The preferred glass substrate of the underlay substrate 1.
The material of the cushion 2 is the stacked combination of silica, silicon nitride or silica and silicon nitride.
The oxide semiconductor TFT T are including the grid 31 being located on the cushion 2, the covering grid 31 and delay
Rush the gate insulator 32 of layer 2, be located at oxide semiconductor active layer on gate insulator 32 corresponding to the top of grid 31
33rd, cover the etch stop layer 34 at the middle part of oxide semiconductor active layer 33 and contact the oxide semiconductor respectively
The source electrode 35 of the both sides of active layer 33 and drain electrode 36；Via H is offered in the protective layer 5, the pixel electrode 6 is through the via
H catalytic oxidation thing semiconductor TFTs T drain electrode 36, to form pixel electrode 6 and the connection of drain electrode 36.
The material of the grid 31 is the stacked combination (such as Mo/Al) or the stacking group of molybdenum and copper of molybdenum (Mo) and aluminium (Al)
Close (such as Mo/Cu).
The material of the gate insulator 32 is silica, and thickness is
The material of the oxide semiconductor active layer 33 is preferably indium gallium zinc oxide, and thickness is
The material of the etch stop layer 34 is silica.
The source electrode 35 and stacked combination (such as Mo/Al/Mo) or the stacking of molybdenum and copper that the material of drain electrode 36 is molybdenum and aluminium
Combine (such as Mo/Cu/Mo).
The thickness of first silicon oxide film layer 51 is
The thickness of the silicon nitride film layer 52 is
The preferred tin indium oxide of material (Indium Tin Oxide, ITO) of the pixel electrode 6.
It is worth noting that：It is different from the existing only protective layer including mono-layer oxidized silicon thin film, in the oxidation of the present invention
In thing semiconductor TFT board structure, the protective layer 5 at least includes the first silicon oxide film layer 51 and covers first oxygen
The silicon nitride film layer 52 of SiClx film layer 51, because silicon nitride film layer 52 has good compactness so that the protection
The ability that layer 5 completely cuts off steam is improved, and can be permeated on the basis of existing technology from the top isolation steam of TFT substrate, more preferably
Ground, which protects oxide semiconductor active layer 33 not invaded by steam, to be influenceed, the electrology characteristic of steady oxide semiconductor TFT.
Fig. 2 show the second embodiment of the oxide semiconductor TFT substrate structure of the present invention, and it is implemented with above-mentioned first
The difference of example is that the protective layer 5 also includes the second silicon oxide film layer 53 for covering the silicon nitride film layer 52, enters one
Step, the thickness of second silicon oxide film layer 53 is It is other identical with first embodiment, this
Place is repeated no more.
Referring to Fig. 3, with reference to Fig. 1 and Fig. 2, the present invention also provides a kind of preparation method of oxide semiconductor TFT substrate,
Comprise the following steps：
Step S1, offer underlay substrate 1, the buffer layer 2 on the underlay substrate 1.
Specifically, the preferred glass substrate of the underlay substrate 1；The material of the cushion 2 be silica, silicon nitride or
The stacked combination of silica and silicon nitride.
Step S2, oxide semiconductor TFT T are produced on the cushion 2.
The step S2 includes step in detailed below：
Step S21, the first metal layer is deposited on the cushion 2, and patterned process is done to the first metal layer, formed
Grid 31.
Specifically, the material of the first metal layer is stacked combination (such as Mo/Al) or the stacking of molybdenum and copper of molybdenum and aluminium
Combine (such as Mo/Cu).
Step S22, deposition gate insulator 32.
Specifically, the material of the gate insulator 32 is silica, and thickness is
Step S23, deposition oxide semiconductive thin film, and patterned process is done to oxide semiconductor thin-film, correspond to
The top of grid 31 forms oxide semiconductor active layer 33.
Specifically, the material of the oxide semiconductor thin-film is preferably indium gallium zinc oxide, and thickness is
Step S24, one layer of insulation film of deposition, and patterned process is carried out to this layer of insulation film, formed described in covering
The etch stop layer 34 at the middle part of oxide semiconductor active layer 33.
Specifically, the material of the insulation film is silica.
Step S25, depositing second metal layer, and patterned process is done to second metal layer, formation contacts the oxygen respectively
The source electrode 35 of the both sides of compound semiconductor active layer 33 and drain electrode 36.
Specifically, the material of the second metal layer is for the stacked combination (such as Mo/Al/Mo) or molybdenum and copper of molybdenum and aluminium
Stacked combination (such as Mo/Cu/Mo).
Step S3, can as shown in figure 1, first deposit the first silicon oxide film layer 51 on the oxide semiconductor TFT T,
Redeposited silicon nitride film layer 52, protective layer 5 is collectively forming by first silicon oxide film layer 51 and silicon nitride film layer 52；
Also can according to actual needs, as shown in Fig. 2 continuing to deposit the second silicon oxide film layer 53 on silicon nitride film layer 52, by institute
State the first silicon oxide film layer 51, silicon nitride film layer 52, be collectively forming protective layer 5 with the second silicon oxide film layer 53；Then
Via H is opened up in protective layer 5.
Specifically, the thickness of first silicon oxide film layer 51 isThe silicon nitride film
Layer 52 thickness beThe thickness of second silicon oxide film layer 53 is
Step S4, deposit layer of conductive film on the protective layer 5, and this layer of conductive film is carried out at patterning
Reason, forms pixel electrode 6.
Specifically, the preferred tin indium oxide of the material of the conductive film；The pixel electrode 6 contacts oxygen through the via H
Compound semiconductor TFT T drain electrode 36, to form pixel electrode 6 and the connection of drain electrode 36.
The preparation method of above-mentioned oxide semiconductor TFT substrate, being made in the bottom of oxide semiconductor TFT substrate has slow
Layer 2 is rushed, top, which makes, the protective layer 5 being at least collectively forming by the first silicon oxide film layer 51 with silicon nitride film layer 52, nitrogen
SiClx film layer 52 has good compactness, makes bottom and the equal energy in top of final obtained oxide semiconductor TFT substrate
Enough isolation steam infiltrations, protecting oxide semiconductor active layer 33 not invaded by steam is influenceed, so that oxide is partly led
Body TFT electrology characteristic is stable.
In summary, oxide semiconductor TFT substrate structure of the invention, on the top of oxide semiconductor TFT substrate
Protective layer is set, and the protective layer at least includes the nitrogen of the first silicon oxide film layer and covering first silicon oxide film layer
SiClx film layer, silicon nitride film layer has good compactness so that the ability of the protective layer isolation steam is improved, can
On the basis of existing technology from the top isolation steam infiltration of TFT substrate, oxide semiconductor active layer is preferably protected not
Being invaded by steam is influenceed, the electrology characteristic of steady oxide semiconductor TFT.The oxide semiconductor TFT substrate of the present invention
Preparation method, being made in the bottom of oxide semiconductor TFT substrate has cushion, and top, which makes, at least thin by the first silica
The protective layer that film layer and silicon nitride film layer are collectively forming, make the bottom of final obtained oxide semiconductor TFT substrate with it is upper
Portion can completely cut off steam infiltration, and protecting oxide semiconductor active layer not invaded by steam is influenceed, so that oxide
The electrology characteristic of semiconductor TFT is stable.
It is described above, for the person of ordinary skill of the art, can be with technique according to the invention scheme and technology
Other various corresponding changes and deformation are made in design, and all these changes and deformation should all belong to appended right of the invention
It is required that protection domain.
Claims (10)
1. a kind of oxide semiconductor TFT substrate structure, it is characterised in that including underlay substrate (1), cover the underlay substrate
(1) cushion (2), the oxide semiconductor TFT (T) being located on the cushion (2), the covering oxide semiconductor
TFT (T) protective layer (5) and the pixel electrode (6) being located on the protective layer (5)；
The protective layer (5) at least includes the first silicon oxide film layer (51) and covers first silicon oxide film layer (51)
Silicon nitride film layer (52).
2. oxide semiconductor TFT substrate structure as claimed in claim 1, it is characterised in that the protective layer (5) also includes
Cover the second silicon oxide film layer (53) of the silicon nitride film layer (52).
3. oxide semiconductor TFT substrate structure as claimed in claim 1, it is characterised in that the oxide semiconductor TFT
(T) grid (31), the covering grid (31) and the gate insulator of cushion (2) being located on the cushion (2) are included
(32), corresponding to the oxide semiconductor active layer (33), covering institute being located above grid (31) on gate insulator (32)
State the etch stop layer (34) in the middle part of oxide semiconductor active layer (33) and contact the oxide semiconductor active layer respectively
(33) source electrode (35) of both sides and drain electrode (36)；
Via (H) is offered in the protective layer (5), the pixel electrode (6) is through the via (H) catalytic oxidation thing semiconductor
TFT (T) drain electrode (36).
4. oxide semiconductor TFT substrate structure as claimed in claim 2, it is characterised in that first silicon oxide film
Layer (51) thickness beThe thickness of the silicon nitride film layer (52) is
The thickness of second silicon oxide film layer (53) is
5. oxide semiconductor TFT substrate structure as claimed in claim 3, it is characterised in that the material of the cushion (2)
For silica, silicon nitride or silica and the stacked combination of silicon nitride；The material of the grid (31) is the stacking group of molybdenum and aluminium
Conjunction or the stacked combination of molybdenum and copper；The material of the gate insulator (32) is silica, and thickness isThe material of the oxide semiconductor active layer (33) is indium gallium zinc oxide, and thickness isThe material of the etch stop layer (34) is silica；The source electrode (35) and the material of drain electrode (36)
For molybdenum and the stacked combination or molybdenum and the stacked combination of copper of aluminium.
6. a kind of preparation method of oxide semiconductor TFT substrate, it is characterised in that including：
Underlay substrate (1), the buffer layer (2) on the underlay substrate (1) are provided；
Oxide semiconductor TFT (T) is produced on the cushion (2)；
The first silicon oxide film layer (51), redeposited silicon nitride film layer are deposited on the oxide semiconductor TFT (T)
(52), first silicon oxide film layer (51) is collectively forming protective layer (5) with silicon nitride film layer (52)；In protective layer (5)
Inside open up via (H)；
Layer of conductive film is deposited on the protective layer (5), and patterned process is carried out to this layer of conductive film, pixel is formed
Electrode (6).
7. the preparation method of oxide semiconductor TFT substrate as claimed in claim 6, it is characterised in that be additionally included in nitridation
The second silicon oxide film layer (53) is deposited on silicon membrane layer (52)；The protective layer (5) also includes second silicon oxide film
Layer (53).
8. the preparation method of oxide semiconductor TFT substrate as claimed in claim 6, it is characterised in that in the cushion
(2) process that oxide semiconductor TFT (T) is produced on is in chronological sequence sequentially specifically included：
The first metal layer is deposited on the cushion (2), and patterned process is done to the first metal layer, grid (31) is formed；
Deposit gate insulator (32)；
Deposition oxide semiconductive thin film, and patterned process is done to oxide semiconductor thin-film, corresponding to the upper of grid (31)
It is square into oxide semiconductor active layer (33)；
One layer of insulation film is deposited, and patterned process is carried out to this layer of insulation film, is formed and covers the oxide semiconductor
Etch stop layer (34) in the middle part of active layer (33)；
Depositing second metal layer, and patterned process is done to second metal layer, formation contacts the oxide semiconductor respectively to be had
The source electrode (35) of active layer (33) both sides and drain electrode (36).
9. the preparation method of oxide semiconductor TFT substrate as claimed in claim 7, it is characterised in that first oxidation
The thickness of silicon membrane layer (51) isThe thickness of the silicon nitride film layer (52) isThe thickness of second silicon oxide film layer (53) is
10. the preparation method of oxide semiconductor TFT substrate as claimed in claim 8, it is characterised in that the cushion
(2) material is the stacked combination of silica, silicon nitride or silica and silicon nitride；The material of the first metal layer is molybdenum
With the stacked combination or molybdenum and the stacked combination of copper of aluminium；The material of the gate insulator (32) is silica, and thickness isThe material of the oxide semiconductor thin-film is indium gallium zinc oxide, and thickness isThe material of the insulation film is silica；The material of the second metal layer is the stacking of molybdenum and aluminium
Combination or the stacked combination of molybdenum and copper.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109887930A (en) * | 2019-02-20 | 2019-06-14 | 深圳市华星光电技术有限公司 | Display panel and preparation method thereof |
| CN113471218A (en) * | 2021-06-29 | 2021-10-01 | 合肥鑫晟光电科技有限公司 | Display panel, manufacturing method thereof and display device |
| CN115064560A (en) * | 2022-07-08 | 2022-09-16 | 福建华佳彩有限公司 | Low-stress insulating layer and oxide TFT array substrate carrying same |
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| CN104395991A (en) * | 2012-06-29 | 2015-03-04 | 株式会社半导体能源研究所 | Semiconductor device |
| CN104752514A (en) * | 2013-12-26 | 2015-07-01 | 昆山工研院新型平板显示技术中心有限公司 | Thin film transistor and preparation method and application thereof |
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| CN104395991A (en) * | 2012-06-29 | 2015-03-04 | 株式会社半导体能源研究所 | Semiconductor device |
| CN104752514A (en) * | 2013-12-26 | 2015-07-01 | 昆山工研院新型平板显示技术中心有限公司 | Thin film transistor and preparation method and application thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109887930A (en) * | 2019-02-20 | 2019-06-14 | 深圳市华星光电技术有限公司 | Display panel and preparation method thereof |
| CN113471218A (en) * | 2021-06-29 | 2021-10-01 | 合肥鑫晟光电科技有限公司 | Display panel, manufacturing method thereof and display device |
| CN113471218B (en) * | 2021-06-29 | 2023-09-19 | 合肥鑫晟光电科技有限公司 | Display panel, manufacturing method thereof and display device |
| CN115064560A (en) * | 2022-07-08 | 2022-09-16 | 福建华佳彩有限公司 | Low-stress insulating layer and oxide TFT array substrate carrying same |
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