CN115064560A - Low-stress insulating layer and oxide TFT array substrate carrying same - Google Patents
Low-stress insulating layer and oxide TFT array substrate carrying same Download PDFInfo
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- CN115064560A CN115064560A CN202210806403.XA CN202210806403A CN115064560A CN 115064560 A CN115064560 A CN 115064560A CN 202210806403 A CN202210806403 A CN 202210806403A CN 115064560 A CN115064560 A CN 115064560A
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/34—Nitrides
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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Abstract
The invention discloses a low-stress insulating layer and an oxide TFT array substrate carrying the insulating layer, which comprises an oxide active layer, a middle insulating layer and a substrate, wherein a silicon oxynitride film made of oxygen-doped silicon nitride is used as the middle insulating layer between a first electrode layer and a second electrode layer in an FFS structure, the middle insulating layer can be further divided into the first middle insulating layer and the second middle insulating layer in a structure with an embedded touch array substrate, and the low-stress oxide thin film transistor array substrate and a preparation method thereof are provided 2 O to obtain the oxygen-doped silicon nitride material, preparing the silicon oxynitride film as the intermediate insulating layer and optimizing the processTherefore, the problem of residual stress of a film layer above the thin film transistor is effectively improved, the technical problem of the degradation influence of the residual stress of the thin film on the thin film transistor below the thin film transistor is reduced, the characteristic uniformity of the thin film transistor is optimized, and the stability of bias test of the device is improved.
Description
Technical Field
The invention belongs to the technical field of oxide TFT array substrates, and particularly relates to a low-stress insulating layer and an oxide TFT array substrate carrying the insulating layer.
Background
With the diversification of consumer market demands, the demands of consumers on display devices are higher and higher, for most consumers, a display with high resolution and refresh rate can bring smoother game experience and visual experience, and in order to realize a display effect with higher specification, higher demands are put forward on the performance of a Thin Film Transistor (TFT) device displayed by a driving panel, so that a metal oxide TFT is favored by people due to the advantages of small leakage current, high field effect mobility, large area uniformity and the like.
The conventional oxide TFT device has excellent electrical characteristics, but has a plurality of difficulties for the commercial preparation of the device, such as meeting the requirements of high efficiency and low cost, ensuring the uniformity and stability of the device during the commercial large-area production, easily causing electrical change and even failure when the electrical property and the stability of the device of the oxide TFT are influenced by the stress generated by a coating process in a production process, and optimizing the electrical property of the device by carrying out stress relief annealing with a certain heating process to improve the stress influence of a thin film, but the stress generated by the coating can not be avoided due to the structural influence of the conventional array substrate.
The silicon nitride film is a semiconductor film with excellent physical and chemical properties, and has high dielectric constant, good heat resistance and corrosion resistance, excellent mechanical properties, high compactness, etc., and thus is often used as a substrate insulating layer, a surface passivation layer, a protective film, a functional layer, etc. in the field of display panels, various methods for preparing the silicon nitride film have been developed so far, such as Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), etc., but the silicon nitride film prepared by the conventional method is generally in a certain stress state, the existence of the stress causes the deterioration of the characteristics of the oxide thin film transistor device, such as threshold voltage Vth shift, bias stability, etc., and the main methods for improving the stress of the SiNx film in the prior art are to change the process parameters (such as temperature, flow ratio, etc.), Radio frequency power, air pressure, silane flow ratio and the like), but basic process changes are carried out to achieve stress reduction, the structural balance of the original substrate is changed, the effects of insulation, passivation, sealing and the like of the SiNx film can be weakened, the performance of a semiconductor device can be directly influenced, and therefore the application space of silicon nitride in actual production is restricted.
Disclosure of Invention
The present invention is directed to a low stress insulating layer and an oxide TFT array substrate having the same, so as to solve the problems of the conventional oxide TFT device, such as high efficiency, low cost, and uniformity and stability of the device during large-area commercial production, although the device has excellent electrical characteristics. The electrical property of the oxide TFT and the stability of the device are easily affected by the stress generated by a coating process in a production process to cause electrical property change and even failure, and a certain heating process is needed to carry out stress relief annealing to optimize the electrical property of the device in order to improve the influence of the film stress, but the problem of the film stress cannot be avoided due to the influence of the structure of the existing array substrate.
In order to achieve the purpose, the invention provides the following technical scheme: a low-stress insulating layer and an oxide TFT array substrate carrying the insulating layer comprise an oxide active layer, a middle insulating layer and a substrate, wherein a silicon oxynitride film made of silicon nitride doped with oxygen is used as an insulating layer between a first electrode layer and a second electrode layer in an FFS structure, the middle insulating layer can be further divided into a first middle insulating layer and a second middle insulating layer in an embedded touch array substrate structure, a grid electrode is arranged at the top of the substrate, a grid electrode insulating layer is arranged at the top of the grid electrode, an oxide active layer is arranged at the projection position of the top of the grid electrode insulating layer, second metal layers are arranged at two ends of the oxide active layer at the top of the grid electrode insulating layer, each second metal layer comprises a source electrode, a drain electrode and a common electrode overlapping region, a passivation layer is arranged at the top of each second metal layer, and a flat layer is arranged at the top of each passivation layer, the flat layer is provided with a first electrode layer at the first via hole, the flat layer and the surface of the first electrode layer are provided with an intermediate insulating layer, a silicon oxynitride film is used as the intermediate insulating layer of the two ITO layers in the FFS structure, the intermediate insulating layer is provided with a second via hole, the top of the intermediate insulating layer is provided with a second electrode layer, and the second electrode layer is in contact with the second metal layer through the second via hole.
Optionally, the planarization layer may not be independently disposed, and a planarization effect can be achieved by increasing the thickness of the passivation layer
Optionally, when the intermediate insulating layer is a stacked structure of silicon nitride and silicon oxynitride, the silicon nitride layer may contact with the upper surface of the first electrode layer or contact with the lower surface of the second electrode layer, that is, the silicon oxynitride may be above or below the silicon nitride layer.
Preferably, when the intermediate insulating layer is a stacked structure of silicon oxide and silicon oxynitride, the silicon oxide is located above the silicon oxynitride.
The oxygen content in the silicon oxynitride film can be changed discontinuously, and the silicon oxynitride film can be divided into a single layer or multiple layers of silicon oxynitride according to the difference of the oxygen content, or a silicon nitride-silicon oxynitride lamination, or a silicon oxynitride-silicon oxide lamination, or a silicon nitride-silicon oxynitride-silicon oxide lamination, wherein the silicon oxynitride material is formed by introducing N in the process of forming the silicon nitride film 2 O gas is formed, the thickness of the silicon oxynitride layer can be 100-6000A, and the SiH serving as the reaction gas 4 /NF 3 /N 2 /N 2 The O gas flow ratio may preferably be: 1/3/12/7, N can be further introduced after the main reaction stage of the silicon oxynitride film formation 2 And performing surface modification by using O gas.
The solar cell comprises an intermediate insulating layer, a first via hole and a substrate, wherein a first metal layer is arranged on the top of the substrate and is used as a grid electrode, a grid electrode insulating layer is arranged on the top of the grid electrode, an oxide active layer is arranged on the top of the grid electrode insulating layer and is positioned at the projection of the grid electrode, second metal layers are arranged on the top of the grid electrode insulating layer and are positioned at two ends of the oxide active layer, a passivation layer is arranged on the top of each second metal layer, a flat layer is arranged on the top of each passivation layer, the intermediate insulating layer comprises a first intermediate insulating layer and a second intermediate insulating layer, a third metal layer is arranged at one end of the top of the flat layer, first intermediate insulating layers are arranged on the surfaces of the flat layer and the third metal layer, a first via hole is arranged on the position of the first intermediate insulating layer and is exposed out of the surface of the third metal layer, the top of the first intermediate insulating layer is provided with a first electrode layer, the first electrode layer is in contact with the third metal layer through a first via hole, the top of the first electrode layer and the top of the first intermediate insulating layer are provided with a second intermediate insulating layer, the second intermediate insulating layer is provided with a second via hole in a drain region of the second metal layer to expose the surface of the second metal layer, the top of the second intermediate insulating layer is provided with a second electrode layer, and the bottom of the second electrode layer is attached to the surface of the second metal layer through the second via hole.
According to the invention, both the first electrode and the second electrode can be used as pixel electrodes or common electrodes according to the design.
Compared with the prior art, the invention has the beneficial effects that: the oxide thin film transistor array substrate and the preparation method thereof are provided by arranging that N is introduced in a silicon nitride film forming process 2 And O, obtaining the oxygen-doped silicon nitride material to prepare a silicon oxynitride film serving as a middle insulating layer and optimizing the process, so that the problem of residual stress of a film layer above the thin film transistor is effectively solved, the technical problem of the degradation influence of the residual stress of the film on the thin film transistor below the thin film transistor is reduced, the characteristic uniformity of the thin film transistor is optimized, and the stability of bias test of the device is improved.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a schematic structural diagram of a second embodiment of the present invention;
in the figure: 1. a gate insulating layer; 2. a passivation layer; 3. a planarization layer; 4. an intermediate insulating layer; 4.1, a first intermediate insulating layer; 4.2, a second intermediate insulating layer; 5. a second metal layer; 6. a first electrode layer; 7. a first via hole; 8. a second electrode layer; 9. a second via hole; 10. a substrate; 11. a gate electrode; 12. an oxide active layer; 13. and a third metal layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
Referring to fig. 1, the present invention provides a technical solution: a low stress insulating layer and an oxide TFT array substrate carrying the insulating layer comprise an oxide active layer 12, an intermediate insulating layer 4 and a substrate 10, and further comprise a first via hole 7 and a second via hole 9, wherein the first via hole 7 comprises a passivation layer via hole and a flat layer via hole, the second via hole 9 comprises a passivation layer via hole, a flat layer via hole and an intermediate layer via hole, a first metal layer is arranged on the top of the substrate 10 and is used as a grid electrode 11, a grid insulating layer 1 is arranged on the top of the grid electrode 11, the oxide active layer 12 is arranged on the top of the grid insulating layer 1 at the projection position of the grid electrode 11, second metal layers 5 are arranged on the top of the grid insulating layer 1 and are arranged at two ends of the oxide active layer 12, the second metal layers 5 comprise a source electrode, a drain electrode and a common electrode overlapping region, the passivation layer 2 is arranged on the top of the second metal layer 5, a flat layer 3 is arranged on the top of the passivation layer 2, a first electrode layer 6 is arranged on the flat layer 3 at the position of the first via hole 7, the surfaces of the flat layer 3 and the first electrode layer 6 are provided with an intermediate insulating layer 4, a silicon oxynitride film doped with silicon oxide is used as an insulating layer between the first electrode layer 6 and the second electrode layer 8 in the FFS structure, the intermediate insulating layer 4 is provided with a second through hole 9, the top of the intermediate insulating layer 4 is provided with the second electrode layer 8, and the second electrode layer 8 is in contact with the second metal layer 5 through the second through hole 9. When the intermediate insulating layer 4 is a stacked structure of silicon nitride and silicon oxynitride, the silicon nitride layer may contact the upper surface of the first electrode layer 6 or contact the lower surface of the second electrode layer 8, i.e. the silicon oxynitride may be above or below the silicon nitride.
The reaction formula of silicon nitride is: SiH 4 ＋NH 3 ＋N 2 →SiN X ＋H 2
The reaction formula of silicon oxynitride is: SiH 4 ＋NH 3 ＋N 2 ＋N 2 O→SiO y N x ＋H 2
The working principle and the using flow of the embodiment are as follows: a first metal layer, i.e. a gate 11, is formed on a substrate 10, wherein the metal layer is made of one or more of aluminum, molybdenum, titanium, nickel, copper, silver, tungsten, and other metals with excellent conductivity and alloys; the first metal layer may be formed on the gate electrode 11 by using a sandwich structure such as, but not limited to, Ti/Al/Ti, Al/Mo, Mo/Al/Mo, etc., a gate protection layer, i.e., a gate insulating layer 1, made of an inorganic oxide or a compound having an insulating property, e.g., SiO, may be formed on the gate electrode 11 X 、SiN x A single layer or a plurality of layers of titanium oxide, aluminum oxide, or the like to form a first insulating layer; an active layer (semiconductor layer), i.e., an oxide active layer 12, is formed on the gate insulating layer 1, and the optional material is a metal oxide semiconductor material, such as, but not limited to, ZnO, IGZO, IGZTO, ITZO, Pr-IZO, etc., and it should be noted that after the oxide active layer 12 is processed and prepared, a via hole is further formed on the gate insulating layer 1 outside the oxide active layer 12 by using a photomask, and the via hole leaks out of the surface of the first metal layer, i.e., the gate 11, so as to achieve the effect of connecting the first metal layer with the second metal layer 5, i.e., the second metal layer; preparing a second metal layer 5 on the active layer, wherein the first metal layer is selected by a process and materials, and the second metal layer 5 can be designed into common electrode lap joint areas such as a touch sensing signal line, a common electrode signal line, a TFT signal input end source electrode, a drain electrode, a panel data line and the like according to circuit design; forming a second insulating layer, i.e. a passivation layer 2, of the same material as the first insulating layer, SiO, on the second metal layer 5 X 、SiN x Single-layer or multi-layer of titanium oxide, aluminum oxide, or the like; preparing a flat layer 3 on the passivation layer 2 by adopting an organic material, forming a third insulating layer, preparing a flat layer through hole in a TFT drain electrode region, preparing a flat layer through hole in a common electrode lap joint region, further preparing a passivation layer through hole on the surface of the drain electrode region, leaking out of the upper surface of the second metal layer 5, and forming a first through hole 7 by the flat layer through hole and the passivation layer through hole; further, a pixel electrode in the FFS display system is prepared by using the ITO transparent conductive material and is connected with the drain electrode through a passivation layer through hole to form a first electrodeAn electrode layer 6; preparing a fourth insulating layer, namely the intermediate insulating layer 4, preferably silicon oxynitride on the first electrode layer 6, preparing an intermediate layer through hole in a common electrode lap joint area, and leaking out of the surface of the second metal layer to form the fourth insulating layer, namely the intermediate insulating layer 4; the common electrode is prepared by ITO transparent conductive material, the common electrode is connected with the common electrode signal line through the flat layer via hole and the middle layer via hole to form a second electrode layer 8, the oxygen content in the silicon oxynitride film can be discontinuously changed, and the silicon oxynitride film can be divided into single-layer or multi-layer silicon oxynitride film according to the difference of oxygen content, or laminated silicon nitride and silicon oxynitride film, or laminated silicon oxynitride and silicon oxide film, or laminated silicon nitride, silicon oxynitride and silicon oxide film, wherein the silicon oxynitride material is formed by introducing N in the process of forming the silicon nitride film 2 O gas is formed, the thickness of the silicon oxynitride layer can be 100-6000A, and the SiH serving as the reaction gas 4 /NF 3 /N 2 /N 2 The O gas flow ratio may preferably be: 1/3/12/7, N can be further introduced after the main reaction stage of the silicon oxynitride film formation 2 And performing surface modification by using O gas.
Example 2
Referring to fig. 2, the present invention provides a technical solution: a low-stress insulating layer and an oxide TFT array substrate carrying the insulating layer comprise an oxide active layer 12, an intermediate insulating layer 4, a third metal layer 13 and a substrate 10, wherein the intermediate insulating layer 4 comprises a first intermediate insulating layer 4.1 and a second intermediate insulating layer 4.2, and further comprises a first via hole 7 and a metal layer via hole, the first via hole 7 comprises a passivation layer via hole, a flat layer via hole and an intermediate insulating layer via hole, the first metal layer is arranged on the top of the substrate 10 and used as a grid electrode 11, a grid insulating layer 1 is arranged on the top of the grid electrode 11, the top of the grid insulating layer 1 is provided with the oxide active layer 12 at the projection position of the grid electrode 11, the top of the grid insulating layer 1 is provided with the second metal layer 5 at two ends of the oxide active layer 12, the second metal layer 5 comprises a source electrode, a drain electrode and a common electrode lap joint area, the top of the second metal layer 5 is provided with the passivation layer 2, the top of the passivation layer 2 is provided with a flat layer 3, one end of the top of the flat layer 3 is provided with a third metal layer 13, the surfaces of the flat layer 3 and the third metal layer 13 are provided with a first intermediate insulating layer, the first intermediate insulating layer 4.1 is provided with a metal layer via hole at the position of the third metal layer 13 and exposes out of the surface of the third metal layer 13, the top of the first intermediate insulating layer 4.1 is provided with a first electrode layer 6, the first electrode layer 6 contacts with the third metal layer through the metal layer via hole, the top of the first electrode layer 6 and the first intermediate insulating layer is provided with a second intermediate insulating layer 4.2, the second intermediate insulating layer 4.2 is provided with a first via hole 7 at the drain electrode region of the second metal layer 5 and exposes out of the surface of the second metal layer 5, the top of the second intermediate insulating layer 4.2 is provided with a second electrode layer 8, and the bottom of the second electrode layer 8 is attached to the surface of the second metal layer 5 through the first via hole 7, when the middle insulating layer 4 is a laminated structure of silicon nitride and silicon oxynitride, the silicon nitride layer can be in contact with the upper surface of the first electrode layer 6 or in contact with the lower surface of the second electrode layer 8, that is, the silicon oxynitride can be arranged above or below the silicon nitride, and the middle insulating layer 4 comprises two layers with the same structure.
The working principle and the using flow of the embodiment are as follows: a first metal layer, i.e. a gate 11, is formed on a substrate 10, wherein the metal layer is made of one or more of aluminum, molybdenum, titanium, nickel, copper, silver, tungsten, and other metals with excellent conductivity and alloys; the first metal layer may be formed by forming a gate protection layer, i.e., a gate insulating layer 1, of a material selected from inorganic oxides or compounds having insulating properties, such as SiO, on the gate electrode 11 using a sandwich structure, such as Ti/Al/Ti, Al/Mo, Mo/Al/Mo, etc., but not limited thereto X 、SiN x A single layer or a plurality of layers of titanium oxide, aluminum oxide, or the like to form a first insulating layer; an active layer (semiconductor layer), i.e., an oxide active layer 12, is formed on the gate insulating layer 1, and the optional material is a metal oxide semiconductor material, such as, but not limited to, ZnO, IGZO, IGZTO, ITZO, Pr-IZO, etc., it should be noted that after the oxide active layer 12 is processed and prepared, a through hole is further formed on the gate insulating layer 1 outside the oxide active layer 12 by using a photomask, and the through hole leaks out of the surface of the first metal layer, i.e., the gate electrode 11, thereby achieving the effect of connecting the first metal layer with the second metal layer 5, i.e., the second metal layer; preparing a second metal layer 5 on the active layer, and selecting the first metal layer by process and material, wherein the second metal layer is the second metal layer5 according to circuit design, the TFT can be designed as a source electrode and a drain electrode of a TFT signal input end, a panel data line and the like; forming a second insulating layer, i.e. a passivation layer 2, of the same material as the first insulating layer, SiO, on the second metal layer 5 X 、SiN x Single-layer or multi-layer of titanium oxide, aluminum oxide, or the like; preparing a third insulating layer on the passivation layer 2 by adopting an organic material to serve as a flat layer 3, and preparing a flat layer through hole in a TFT drain electrode region to expose the surface of the passivation layer; a third metal layer 13 is manufactured on the flat layer 3, the process and material selection are the same as those of the first metal layer, and the third metal layer 13 is overlapped with the projection surface of the data signal line of the second metal layer or the projection area of the driving signal of the first metal layer in the panel display area; preparing a fourth insulating layer, namely a first intermediate insulating layer 4.1, preferably a silicon oxynitride material on the third metal layer 13, preparing an intermediate via hole in a common electrode lap joint region, and leaking out of the surface of the third metal layer 13; further, a common electrode in the FFS display system is prepared by using an ITO transparent conductive material, and is connected with the third metal layer 13 through a first intermediate insulating layer via hole to prepare a first electrode layer 6; preparing a fifth insulating layer, namely a second intermediate insulating layer, preferably a silicon oxynitride material on the first electrode layer 6, and preparing via holes of the second intermediate insulating layer 4.2, the first intermediate insulating layer 4.1 and the passivation layer 2 in a drain lap joint area, wherein the via holes are superposed with the via holes of the flat layer, and the via holes form a first via hole 7 and leak out of the surface of the second metal layer 5; and preparing a pixel electrode by using an ITO transparent conductive material, and connecting the pixel electrode with the drain electrode lap joint region through the first through hole 7 to form a second electrode layer 8.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (7)
1. A low stress insulating layer and an oxide TFT array substrate carrying the insulating layer, comprising an oxide active layer (12), an intermediate insulating layer (4) and a substrate (10), characterized in that: the top of the substrate (10) is provided with a first metal layer serving as a grid electrode (11), the top of the grid electrode (11) is covered with a grid electrode insulating layer (1), the top of the grid electrode insulating layer (1) is provided with an oxide active layer (12) at the projection position of the grid electrode (11), the top of the grid electrode insulating layer (1) is provided with second metal layers (5) at the two ends of the oxide active layer (12), the top of the second metal layer (5) is provided with a passivation layer (2), the top of the passivation layer (2) is provided with a flat layer (3), a first electrode layer (6) is arranged on the flat layer (3) at the first via hole (7), the surfaces of the flat layer (3) and the first electrode layer (6) are provided with an intermediate insulating layer (4), and a silicon oxynitride film made of an oxygen-doped silicon nitride material is used as an intermediate insulating layer (4) of two ITO layers in an FFS structure, the middle insulating layer (4) is provided with a second through hole (9), the top of the middle insulating layer (4) is provided with a second electrode layer (8), and the second electrode layer (8) is in contact with the second metal layer (5) through the second through hole (9).
2. A low stress insulating layer and an oxide TFT array substrate carrying the insulating layer comprise an oxide active layer (12), an intermediate insulating layer (4), a third metal layer (13) and a substrate (10), and are characterized in that; the top of base plate (10) is equipped with first metal layer as grid (11), the top of grid (11) is equipped with grid insulating layer (1), the top of grid insulating layer (1) is located the projection department of grid (11) and is provided with oxide active layer (12), the both ends that the top of grid insulating layer (1) is located oxide active layer (12) are equipped with second metal layer (5), the top of second metal layer (5) is equipped with passivation layer (2), the top of passivation layer (2) is equipped with flat layer (3), middle insulating layer (4) include first middle insulating layer (4.1) and second middle insulating layer (4.2), the top one end of flat layer (3) is equipped with third metal layer (13), the surface of flat layer (3) and third metal layer (13) is equipped with first middle insulating layer (4.1), first middle insulating layer (4.1) are located third metal layer (13) and are equipped with the metal layer through-hole and expose the third metal layer A first electrode layer (6) is arranged on the top of the first intermediate insulating layer (4.1) on the surface of the metal layer (13), the first electrode layer (6) is in contact with the third metal layer (13) through a metal layer via hole, a second intermediate insulating layer (4.2) is arranged on the top of the first electrode layer (6) and the first intermediate insulating layer (4.1), the second intermediate insulating layer (4.2) is provided with a first through hole (7) in the drain region of the second metal layer (5) to expose the surface of the second metal layer (5), a second electrode layer (8) is arranged on the top of the second intermediate insulating layer (4.2), the bottom of the second electrode layer (8) is attached to the surface of the second metal layer (5) through a first through hole (7), the density of oxygen atoms of the silicon oxynitride film in the first intermediate insulating layer (4.1) and the second intermediate insulating layer (4.2) can be gradually and continuously increased or continuously decreased from the upper surface of the first electrode layer (6) to the lower surface of the second electrode layer (8).
3. The low stress insulation layer and the oxide TFT array substrate having the same as claimed in claim 1, wherein: and a silicon oxynitride film made of oxygen-doped silicon nitride is used as an insulating layer between the first electrode layer (6) and the second electrode layer (8) in the FFS structure.
4. The low stress insulation layer and the oxide TFT array substrate having the same as claimed in claim 3, wherein: the oxygen content in the silicon oxynitride film can be changed discontinuously, and the silicon oxynitride film can be divided into a silicon oxynitride single layer or a plurality of layers according to the difference of the oxygen content, or a silicon nitride and silicon oxynitride laminated layer, or a silicon oxynitride and silicon oxide laminated layer, or a silicon nitride, silicon oxynitride and silicon oxide laminated layer.
5. The low stress insulation layer and the oxide TFT array substrate having the same as claimed in claim 4, wherein: when the middle insulating layer (4) is a laminated structure of silicon nitride and silicon oxynitride, the silicon nitride can be in contact with the upper surface of the first electrode layer (6) or in contact with the lower surface of the second electrode layer (8), and the silicon oxynitride is arranged above or below the silicon nitride.
6. The low stress insulating layer and the oxide TFT array substrate having the same as claimed in claims 2 and 4, wherein: the first intermediate insulating layer (4.1) is made of silicon nitride and silicon oxynitride, wherein the silicon nitride is positioned below the silicon oxynitride, and the second intermediate insulating layer (4.2) is made of silicon oxide.
7. The low stress insulation layer and the oxide TFT array substrate having the same as claimed in claim 3, wherein: the silicon oxynitride material is prepared by introducing N into the process of forming silicon nitride film 2 O gas is formed, the thickness of the silicon oxynitride layer can be 100-6000A, and the SiH serving as the reaction gas 4 /NF 3 /N 2 /N 2 The O gas flow ratio may preferably be: 1/3/12/7, N can be further introduced after the main reaction stage of silicon oxynitride film formation 2 And performing surface modification by using O gas.
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