CN218769536U - High-stability oxide thin film transistor array substrate - Google Patents
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- CN218769536U CN218769536U CN202221907646.4U CN202221907646U CN218769536U CN 218769536 U CN218769536 U CN 218769536U CN 202221907646 U CN202221907646 U CN 202221907646U CN 218769536 U CN218769536 U CN 218769536U
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Abstract
The utility model provides an oxide thin film transistor array substrate of high stability, include: a substrate; a first metal layer; a first insulating layer; an active layer; a second metal layer; a second insulating layer; a third insulating layer; a third metal layer; a fourth insulating layer; a first ITO layer; the fifth insulating layer is arranged on the first ITO layer; the fifth insulating layer is also provided with a groove area in the invalid area above the TFT, and a partition area is arranged between the TFT and the TFT; and the second ITO layer is arranged at the third through hole and is connected with the second metal layer of the drain region through the third through hole. The groove region and the partition region are arranged in the invalid region in the fifth insulating layer and the fourth insulating layer, so that the problem of residual stress of large-area film forming of the insulating layers is solved, the threshold voltage uniformity of the device and the mechanical test reliability of the panel can be effectively improved, and the basic stability of the array is improved.
Description
Technical Field
The utility model relates to a display device field, especially a high stability's oxide thin film transistor array substrate.
Background
With the diversification of consumer market demands, the demands of consumers on display devices are higher and higher, and for most consumers, a high-resolution and refresh-rate display can bring smoother game experience and visual experience. In order to achieve a higher specification of display effect, higher requirements are put forward on the performance of a TFT device of a thin film transistor for driving a panel display, and therefore, a metal oxide TFT is favored because it has advantages of small leakage current, high field effect mobility, large area uniformity, and the like.
The oxide TFT device has excellent electrical characteristics, but has many difficulties in commercial production of the device, such as meeting the requirements of high efficiency, low cost, and ensuring uniformity and stability of the device in commercial large-area production. The electrical property of the oxide TFT and the stability of the device are easily affected by the stress generated by a coating process in a production process to cause electrical property change and even failure, and a certain heating process is needed to carry out stress relief annealing to optimize the electrical property of the device in order to improve the stress influence of the thin film, but the stress generated by the coating can not be avoided due to the structural influence of the existing array substrate.
The FFS-LCD technology, which is called "Fringe Field Switching" (FFS) technology for short, is a wide viewing angle technology developed in the liquid crystal industry for large-size, high-definition desktop displays and LCD televisions, that is, a hard screen technology commonly known at present. In the FFS technology, fringe electric fields are generated by the electrodes between pixels in the same plane, so that the oriented liquid crystal molecules between the electrodes and right above the electrodes can be rotated and converted in the plane direction (parallel to the substrate), and the light transmission efficiency of a liquid crystal layer is improved. To realize the FFS structure, two transparent conductive layers and an intermediate insulating layer between the two conductive layers are required.
The silicon nitride and silicon oxide film is a semiconductor film with excellent physical and chemical properties, and has high dielectric constant, good heat resistance and corrosion resistance, excellent mechanical properties, high density and the like. Silicon nitride has a higher dielectric constant than silicon oxide, is denser, but also more prone to H + ion retention and residual stress. Therefore, in the field of display panels, silicon nitride and silicon oxide are often used in combination in an insulating layer, a surface passivation layer, a protective film, a functional layer, and the like. The silicon nitride and silicon oxide films prepared by the existing process method are generally in a certain stress state, the existence of the stress can cause glass fragmentation when the glass deformation is serious on a macroscopic level, and the residual stress of the film can cause the energy band transition of the film material of the oxide film transistor device on a microscopic level, so that the device characteristics are deteriorated, such as threshold voltage Vth deviation, bias voltage stability deterioration and the like. The main method for improving the film stress in the prior art is to change process parameters (such as temperature, flow ratio, radio frequency power, air pressure, gas flow ratio and the like), but the basic process change for reducing the stress is achieved, the structural balance of the original substrate is changed, the effects of insulation, passivation, sealing and the like of the film can be weakened, and the performance of a semiconductor device can be directly influenced, so that the application space of the film material in the actual production is restricted.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model lies in providing an oxide thin film transistor array substrate of high stability recess district and partition district are seted up to invalid region in fifth insulating layer and the fourth insulating layer, have reduced the residual stress problem of insulating layer large tracts of land film formation, can effectively improve the threshold voltage homogeneity and the panel mechanical test reliability of device to improve the basic stability of array.
The utility model discloses a realize like this: a high-stability oxide thin film transistor array substrate includes:
a substrate;
the first metal layer is arranged on the substrate;
the first insulating layer is arranged on the first metal layer; the first insulating layer is also provided with a first through hole, and the upper surface of the first metal layer is exposed from the first through hole;
an active layer disposed on the first insulating layer;
the second metal layer is arranged on the active layer and is connected with the first metal layer through the first through hole;
the second insulating layer is arranged on the second metal layer;
the third insulating layer is arranged on the second insulating layer;
the third metal layer is arranged on the third insulating layer and corresponds to a common electrode lap joint area of the TFT;
the fourth insulating layer is arranged above the third metal layer, a second through hole is formed in the common electrode overlapping area, and the upper surface of the third metal layer is exposed out of the second through hole;
the first ITO layer is arranged on the fourth insulating layer and is connected with the third metal layer through the second through hole;
the fifth insulating layer is arranged on the first ITO layer; the fifth insulating layer is also provided with a third through hole at the drain electrode region of the TFT, and the upper surface of the second metal layer is exposed from the third through hole; a groove region is further formed in the invalid region, above the TFT, of the fifth insulating layer, and the groove region penetrates through the fourth insulating layer downwards to expose the upper surface of the third insulating layer; a partition region is formed between the TFT and the fifth insulating layer, and the partition region penetrates through the fourth insulating layer downwards to expose the upper surface of the third insulating layer;
and the second ITO layer is arranged at the third through hole and is connected with the second metal layer of the drain region through the third through hole.
Further, the bottom of the groove area and the bottom of the partition area are respectively provided with a cushion layer, and the cushion layer and the third metal layer are located on the same horizontal plane.
Further, the first metal layer is made of one or more of aluminum, molybdenum, titanium, nickel, copper, silver or tungsten, or an alloy;
the second metal layer and the first metal layer are made of the same material.
Further, the first metal layer adopts a sandwich structure as follows: ti/Al/Ti, al/Mo, or Mo/Al/Mo.
Further, the first insulating layer is made of silicon nitride, silicon oxide, silicon oxynitride, titanium oxide or aluminum oxide;
the second insulating layer, the fourth insulating layer, the fifth insulating layer and the first insulating layer are made of the same material.
Further, the active layer is made of a metal oxide semiconductor material.
Further, the third insulating layer is made of an organic polymer material.
The utility model has the advantages of as follows: the utility model provides an oxide thin film transistor array substrate of high stability, include: a substrate; a first metal layer; a first insulating layer; an active layer; a second metal layer; a second insulating layer; a third insulating layer; a third metal layer; a fourth insulating layer; a first ITO layer; the fifth insulating layer is arranged on the first ITO layer; the fifth insulating layer is also provided with a groove area in the invalid area above the TFT, and a partition area is arranged between the TFT and the TFT; and the second ITO layer is arranged at the third through hole and is connected with the second metal layer of the drain region through the third through hole. The groove region and the partition region are arranged in the invalid region in the fifth insulating layer and the fourth insulating layer, so that the problem of residual stress of large-area film forming of the insulating layers is solved, the threshold voltage uniformity of the device and the mechanical test reliability of the panel can be effectively improved, and the basic stability of the array is improved. The third metal layer is arranged so that the array substrate can integrate an in-cell touch function.
Drawings
The present invention will be further described with reference to the following examples and drawings.
Fig. 1 is a schematic structural diagram of an oxide thin film transistor array substrate with high stability according to the present invention.
Fig. 2 is a process flow chart of a method for manufacturing a high-stability oxide thin film transistor array substrate according to the present invention.
Description of the reference numerals:
a substrate 1;
a first metal layer 2, a gate 21;
a first insulating layer 3, a first via hole 31;
an active layer 4;
a second metal layer 5, a common electrode signal line 51, a source electrode 52, a drain electrode 53;
a second insulating layer 6;
a third insulating layer 7;
a third metal layer 8;
a fourth insulating layer 9, a second via hole 91;
a first ITO layer 10;
a fifth insulating layer 20, a third through hole 201, a groove area 202, and a partition area 203;
a second ITO layer 30;
a cushion layer 40;
a driving circuit region 100;
the area 200 is displayed.
Detailed Description
In the description of the present invention, it should be understood that the description indicating the orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the scope of the present invention.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "disposed", "connected" and "connected" are to be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the utility model can be understood as a specific case by a person of ordinary skill in the art.
Word interpretation: the stress of the utility model refers to the internal stress.
In the liquid crystal panel array substrate, the liquid crystal panel array substrate may be generally divided into a display area 200, a signal wiring area, a driving circuit area (GIP) 100, a Switch area, a diagonal wiring area, an IC bonding area, an anti-static area, and the like, and among these areas, an area provided with a semiconductor thin film structure generally includes the display area 200, the driving circuit area 100, the Switch area, the anti-static design area, and the like.
The utility model discloses a design as follows:
(1) In the prior art, the array substrate is easily affected by the stress generated by the coating process in the production process to cause electrical property change and even failure, so the prior art often adopts the annealing heat treatment process to eliminate the stress, but because the thermal expansion coefficients of all film layers of the array substrate are different, new internal stress can be generated between the film layers after annealing treatment, and whether the stress of the array substrate is reduced or not can not be ensured in the actual production.
Therefore, the utility model discloses recess district 202 or cut off district 203 have been added in the innovation in array substrate structure, dig the insulating layer at array substrate's invalid area promptly and thin or dig absolutely, carry out the fragmentation with array substrate holistic stress, at first recess district 202 and cut off the stress of district 203 and reduced, secondly with the stress differentiation of monoblock array substrate to each littleer block on, thereby the residual stress problem of insulating layer large tracts of land film formation has been reduced, can effectively improve the threshold voltage homogeneity and the panel mechanical testing reliability of device, thereby improve the basic stability of array.
(2) The third metal layer 8 is disposed to enable the array substrate to integrate an in-cell touch function, and in order to increase the panel aperture ratio, the third metal layer 8 may be disposed as a capacitive touch sensing unit and a common signal line, and at this time, the third metal layer 8 is disposed as a touch signal line and a common signal line, and a projection plane of the second metal layer 5 disposed below the touch signal line coincides with a projection plane of the second metal layer on the substrate 1.
Please refer to fig. 1 and fig. 2.
The utility model discloses an oxide thin film transistor array substrate of high stability, include:
a substrate 1;
the first metal layer 2 is used as a driving circuit wire or a grid 21 of a TFT and is arranged on the substrate 1;
a first insulating layer 3 as a gate insulating layer disposed on the first metal layer 2; the first insulating layer 3 is further provided with a first through hole 31, and the upper surface of the first metal layer 2 is exposed from the first through hole 31; in a specific implementation, the first through holes 31 may be formed in the driving circuit region 100, the sector region, the IC bonding region, and the like of the array substrate, so as to expose the surface of the first metal layer 2, thereby achieving the effect of connecting the first metal layer 2 and the second metal layer 5.
An active layer 4, also called a semiconductor layer, provided on the first insulating layer 3;
a second metal layer 5 disposed on the active layer 4 and connected to the first metal layer 2 through the first via hole 31; the second metal layer 5 may be designed as a touch sensing signal line, a common electrode signal line 51, a TFT signal input terminal source 52/drain 53, or a data signal line (i.e., the common electrode signal line 51) according to requirements.
The second insulating layer 6 is used as a passivation layer to protect the TFT device from being invaded by external water and oxygen and is arranged on the second metal layer 5;
a third insulating layer 7 as a flat layer provided on the second insulating layer 6;
a third metal layer 8 disposed on the third insulating layer 7 and corresponding to a common electrode overlapping region of the TFT; an embedded touch function can be integrated, and in order to increase the aperture ratio of the panel, a third metal layer 8 can be provided as a capacitive touch sensing unit and a common electrode signal line, so as to meet the requirement of more complicated wiring, at this time, the third metal layer 8 is used as a touch signal line and a common electrode signal line and is superposed with the projection surface of the second metal layer 5 which is used as a data signal line below on the substrate 1, that is, when the third metal layer 8 is used as a touch signal line and a common electrode signal line, the second metal layer 5 in the common electrode overlapping area is used as a common electrode signal line 51 as a data signal line. The third metal layer 8 can be one or more of aluminum, molybdenum, titanium, nickel, copper, silver, tungsten and other metals with excellent conductivity or alloy; further, the third metal layer 8 may use a sandwich-type structure such as Ti/Al/Ti, al/Mo, mo/Al/Mo, etc.;
a fourth insulating layer 9, serving as a first intermediate insulating layer, disposed above the third metal layer 8, and having a second via hole 91 in the common electrode overlapping region, wherein the upper surface of the third metal layer 8 is exposed from the second via hole 91;
the first ITO layer 10, as a common electrode, is disposed on the fourth insulating layer 9, and is connected to the third metal layer 8 in the common electrode overlapping area through the second via hole 91;
a fifth insulating layer 20 as a second intermediate insulating layer disposed on the first ITO layer 10; a third via 201 is further formed in the fifth insulating layer 20 at the drain region of the TFT, and the upper surface of the second metal layer 5 is exposed from the third via 201; the fifth insulating layer 20 is further provided with a groove region 202 in the inactive area above the TFT, and the groove region 202 penetrates the fourth insulating layer 9 downward to expose the upper surface of the third insulating layer 7; the fifth insulating layer 20 is provided with a partition region 203 between the TFTs, and the partition region 203 penetrates the fourth insulating layer 9 downwards to expose the upper surface of the third insulating layer 7; the groove region 202 and the partition region 203 are arranged in the invalid region in the fifth insulating layer 20, so that the problem of residual stress of large-area film formation of the insulating layer is solved, the threshold voltage uniformity of a device and the mechanical test reliability of a panel can be effectively improved, and the basic stability of the array is improved.
The second ITO layer 30, as a pixel electrode, is disposed at the third via 201, and is connected to the drain electrode 53 through the third via 201 and the second metal layer 5 of the drain region, that is, through the third via 201.
The bottom of the groove region 202 and the bottom of the isolation region 203 are respectively provided with a pad layer 40, the pad layer 40 and the third metal layer 8 are located at the same horizontal plane and can be made of ITO material, and in specific implementation, for example, the groove region 202 and the isolation region 203 are prepared by etching, so that the third insulating layer 7 can be protected by the pad layer 40, and the groove region 202 and the isolation region 203 are prevented from being damaged in the etching process.
The first metal layer 2 is made of one or more of aluminum, molybdenum, titanium, nickel, copper, silver or tungsten or an alloy;
the second metal layer 5 and the first metal layer 2 are made of the same material.
The first metal layer 2 adopts a sandwich structure as follows: ti/Al/Ti, al/Mo, or Mo/Al/Mo.
The first insulating layer 3 is made of silicon nitride, silicon oxide, silicon oxynitride, titanium oxide or aluminum oxide;
the second insulating layer 6, the fourth insulating layer 9, the fifth insulating layer 20 and the first insulating layer 3 are made of the same material.
The active layer 4 is made of a metal oxide semiconductor material.
The third insulating layer 7 is made of an organic polymer material, that is, the third insulating layer 7 is used as an organic flat layer.
The utility model discloses a preparation method of oxide thin film transistor array substrate of high stability, preparation method of low stress oxide thin film transistor array substrate include following step:
s1, forming a film on a substrate 1 to manufacture a first metal layer 2 which is used as a drive circuit wiring or a grid 21 of a TFT, wherein the first metal layer 2 can be one or more of metals with excellent conductivity, such as aluminum, molybdenum, titanium, nickel, copper, silver, tungsten and the like, or an alloy; further, the first metal layer 2 may also use a sandwich-type structure such as Ti/Al/Ti, al/Mo, mo/Al/Mo, etc., but is not limited thereto;
s2, manufacturing a first insulating layer 3 on the first metal layer 2, wherein the first insulating layer is used as a gate insulating layer, and the material can be inorganic oxide or compound with insulating property, such as silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide and the like, and can be single-layer or multi-layer;
s3, manufacturing an active layer 4 on the first insulating layer 3, and then manufacturing a first through hole 31 on the first insulating layer 3 to expose the upper surface of the first metal layer 2;
the active layer 4 may be made of a metal oxide semiconductor material, such as ZnO, IGZO, IGZTO, ITZO, pr-IZO, or the like. After the active layer is prepared, namely after the active layer is patterned, a photomask is further used for preparing a first through hole 31 in the driving circuit area 100, the fan-shaped area, the IC bonding area and the like, so that the surface of the first metal layer 2 is exposed, and the effect of connecting the first metal layer 2 with the second metal layer 5 is achieved;
s4, forming a film on the active layer 4 to manufacture a second metal layer 5, wherein the process and material selection are the same as those of the first metal layer 2, the second metal layer 5 can be designed into a touch sensing signal line, a common electrode signal line 51, a TFT signal input end source 52/drain 53, a data signal line and the like according to requirements, and the second metal layer 5 is connected with the first metal layer 2 through the first through hole 31;
s5, manufacturing a second insulating layer 6 on the second metal layer 5, wherein the second insulating layer is used as a passivation layer to protect the TFT device from being invaded by external water and oxygen, and the material is selected from the first insulating layer 3, such as silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide and the like, and can be a single layer or multiple layers;
s6, preparing a third insulating layer 7 on the second insulating layer 6, wherein the third insulating layer is used as a flat layer and can be prepared by adopting an organic high polymer material;
then, a first through hole is prepared on the third insulating layer 7 corresponding to the drain region of the TFT by using a photomask, and the upper surface of the second insulating layer 6 of the drain region is exposed;
s7, manufacturing a third metal layer 8 on the third insulating layer 7 corresponding to the common electrode lap joint area to serve as a touch signal induction line and a common electrode signal line, wherein the third metal layer 8 can be one or more of aluminum, molybdenum, titanium, nickel, copper, silver, tungsten and other metals with excellent conductivity or alloy; further, the third metal layer 8 may also use a sandwich-type structure such as Ti/Al/Ti, al/Mo, mo/Al/Mo, etc.; and the same material as said third metal layer 8, make the cushion layer 40 between TFT device in the inactive area above TFT; wherein, the cushion layer 40 and the third metal layer 8 are located at the same horizontal plane;
s8, manufacturing a fourth insulating layer 9 on the third metal layer 8, wherein the fourth insulating layer is used as a first intermediate insulating layer, the material of the fourth insulating layer is selected from the first insulating layer 3, such as silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide and the like, and a single-layer or multi-layer structure and the like can be adopted; then, preparing a second through hole 91 in the common electrode overlapping area by etching, and exposing the upper surface of the third metal layer 8;
s9, preparing a first ITO layer 10 serving as a common electrode on the fourth insulating layer 9 by using a transparent conductive material ITO, and connecting the first ITO layer with a third metal layer 8 in a common electrode lap joint area through a second through hole 91, namely connecting the first ITO layer with a common electrode signal wire through the second through hole 91;
s10, preparing a fifth insulating layer 20 on the first ITO layer 10 to serve as an intermediate insulating layer, selecting materials such as the first insulating layer 3, silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide and the like which can be single-layer or multi-layer, further preparing a second through hole above the first through hole through an etching process, enabling the second through hole to downwards penetrate through the second insulating layer 6 to expose the upper surface of the second metal layer 5, and forming a third through hole 201, namely preparing the third through hole 201 step by step; simultaneously, a groove region 202 and an isolation region 203 are etched at the position of the cushion layer 40, the groove region 202 and the isolation region 203 penetrate through the fourth insulating layer 9 to expose the upper surface of the third insulating layer 7, the cushion layer 40 protects the third insulating layer 7, and the third insulating layer 7 is prevented from being damaged in the etching process;
s11, preparing a second ITO layer 30 as a pixel electrode by using an ITO transparent conductive material, and connecting the second ITO layer with the second metal layer 5 of the drain region through the third through hole 201, namely connecting the second ITO layer with the drain 53 through the third through hole 201.
The utility model has the advantages that: the groove region 202 and the partition region 203 are formed in the fifth insulating layer 20 and penetrate through the fourth insulating layer 9, so that the integral internal stress of the fifth insulating layer 20 and the fourth insulating layer 9 is fragmented, the problem of residual stress of large-area film forming of the insulating layers is solved, and the threshold voltage uniformity of a device and the mechanical test reliability of a panel can be effectively improved.
Although specific embodiments of the present invention have been described, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the claims appended hereto.
Claims (6)
1. A high-stability oxide thin film transistor array substrate is characterized in that: the method comprises the following steps:
a substrate;
the first metal layer is arranged on the substrate;
the first insulating layer is arranged on the first metal layer; the first insulating layer is also provided with a first through hole, and the upper surface of the first metal layer is exposed from the first through hole;
an active layer disposed on the first insulating layer;
the second metal layer is arranged on the active layer and is connected with the first metal layer through the first through hole;
the second insulating layer is arranged on the second metal layer;
the third insulating layer is arranged on the second insulating layer;
the third metal layer is arranged on the third insulating layer and corresponds to a common electrode lap joint area of the TFT;
the fourth insulating layer is arranged above the third metal layer, a second through hole is formed in the common electrode overlapping area, and the upper surface of the third metal layer is exposed out of the second through hole;
the first ITO layer is arranged on the fourth insulating layer and is connected with the third metal layer through the second through hole;
the fifth insulating layer is arranged on the first ITO layer; the fifth insulating layer is also provided with a third through hole at the drain electrode region of the TFT, and the upper surface of the second metal layer is exposed from the third through hole; a groove region is further formed in the invalid region of the fifth insulating layer above the TFT, and the groove region penetrates through the fourth insulating layer downwards to expose the upper surface of the third insulating layer; a partition region is formed between the TFT and the fifth insulating layer and penetrates through the fourth insulating layer downwards to expose the upper surface of the third insulating layer;
and the second ITO layer is arranged at the third through hole and is connected with the second metal layer of the drain region through the third through hole.
2. The high-stability oxide thin film transistor array substrate of claim 1, wherein: and cushion layers are respectively arranged at the bottom of the groove area and the bottom of the partition area, and the cushion layers and the third metal layer are positioned on the same horizontal plane.
3. The high-stability oxide thin film transistor array substrate of claim 1, wherein: the first metal layer adopts a sandwich structure as follows: ti/Al/Ti, al/Mo, or Mo/Al/Mo.
4. The high-stability oxide thin film transistor array substrate of claim 1 or 2, wherein: the first insulating layer is made of silicon nitride, silicon oxide, silicon oxynitride, titanium oxide or aluminum oxide;
the second insulating layer, the fourth insulating layer, the fifth insulating layer and the first insulating layer are made of the same material.
5. The high-stability oxide thin film transistor array substrate of claim 1 or 2, wherein: the active layer is made of metal oxide semiconductor material.
6. The high-stability oxide thin film transistor array substrate of claim 1 or 2, wherein: the third insulating layer is made of an organic polymer material.
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