CN114488638A - Array substrate capable of avoiding active layer opening over-etching and manufacturing method thereof - Google Patents
Array substrate capable of avoiding active layer opening over-etching and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 238000005530 etching Methods 0.000 title claims description 35
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims description 32
- 239000002184 metal Substances 0.000 claims description 32
- 230000004888 barrier function Effects 0.000 claims description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 230000008569 process Effects 0.000 claims description 7
- DNAUJKZXPLKYLD-UHFFFAOYSA-N alumane;molybdenum Chemical compound [AlH3].[Mo].[Mo] DNAUJKZXPLKYLD-UHFFFAOYSA-N 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000011161 development Methods 0.000 claims description 4
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- HKBLLJHFVVWMTK-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti].[Ti] HKBLLJHFVVWMTK-UHFFFAOYSA-N 0.000 claims description 3
- FAHBNUUHRFUEAI-UHFFFAOYSA-M hydroxidooxidoaluminium Chemical compound O[Al]=O FAHBNUUHRFUEAI-UHFFFAOYSA-M 0.000 claims description 3
- 239000011787 zinc oxide Substances 0.000 claims description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052733 gallium Inorganic materials 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
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- 239000004973 liquid crystal related substance Substances 0.000 abstract description 4
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
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- HLLICFJUWSZHRJ-UHFFFAOYSA-N tioxidazole Chemical compound CCCOC1=CC=C2N=C(NC(=O)OC)SC2=C1 HLLICFJUWSZHRJ-UHFFFAOYSA-N 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
Abstract
The invention relates to the technical field of liquid crystal display, in particular to an array substrate capable of reducing CH hole contact impedance and a manufacturing method thereof. According to the array substrate capable of reducing the CH hole contact impedance, an additional pure molybdenum metal layer is added after a third insulating layer hole is formed in a third insulating layer and before a pixel electrode layer is formed into a film, the pure molybdenum metal layer is arranged between a source drain electrode and the pixel electrode layer by using a method of matching a third insulating layer photomask with a negative photoresist to play a bridging role, so that the contact impedance between the pixel electrode layer and the source drain electrode is reduced, and the normal display of a display screen picture is ensured.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to an array substrate capable of reducing CH hole contact impedance and a manufacturing method thereof.
Background
Currently, amorphous metal oxide semiconductors are rapidly developing. The amorphous InGaZnO (IGZO) is an ideal material for preparing the TFT by virtue of a simple preparation process and excellent photoelectric properties, and the TFT prepared by the amorphous InGaZnO (IGZO) has the characteristics of high mobility, high on-off ratio and the like and has the potential of replacing a-Si. Compared with an a-Si TFT, the carrier mobility of the IGZO-TFT can reach 10-30 cm 2/V.S, and the charge-discharge efficiency and the response speed of the TFT on a pixel electrode are greatly improved. More importantly, the IGZO process has good compatibility with the existing a-Si production line, and has lower investment cost compared with the Low Temperature Polysilicon (LTPS) which has more complex production process and higher equipment investment.
The conventional In-Cell technology is a method of embedding a touch panel function into a liquid crystal pixel, thereby realizing an integrated design of a touch panel component and a liquid crystal panel. In the aspect of Array process, transparent materials such as ITO are used as a common electrode and a film layer of a pixel electrode, and a source drain metal layer is overlapped through a CH hole to carry out pixel charging and discharging. In the actual mass production process, the charging and discharging efficiency is often affected by the lap impedance between the ITO and the metal layer, and a serious person directly affects the normal display of the display screen, and uneven display of the screen or other Mura-type defects occur. Most of the existing SD source and drain materials are mainly TiAlTi three-layer composite metal, wherein Al is a main conductive film layer, and Ti is mainly used as a buffer layer to improve a contact interface between Al and an inorganic film layer and protect Al from being oxidized. However, in the process of manufacturing actual products, it is found that the contact resistance between Ti and ITO is far beyond the design value and reaches 105 Ω, thereby causing the above-mentioned problems of pixel charging and discharging and uneven picture display, according to the deep research, it is found that this is mainly because the oxygen atoms of the ITO target in the Sputter process can cause Ti oxidation on the TiAlTi source and drain metal surface, forming high-resistance TiOx, thereby affecting the lap joint resistance, and the direct improvement method is to change the transparent electrode material or the source and drain metal material.
At present, the selectable metals in the market comprise Mo/Al/Mo, Cu and Ag, however, the cost of Ag is too high, Mo and Cu have poor contact with an inorganic film SiOx although the cost is low, particularly, the phenomenon of floating film or peeling can occur on some inorganic films at high temperature, the selection of the film quality of the inorganic film is greatly limited, and other Issue types are poor. Although the Mo/Al/Mo metal layer as the conductive layer has requirements and limits on the inorganic film layer, the contact resistance between Mo and ITO is very small, and the contact resistance accords with the existing design specification value and is about 103 omega.
Therefore, an array substrate and a method for manufacturing the same are provided to reduce the contact resistance of the CH hole.
Disclosure of Invention
The present invention is directed to an array substrate capable of reducing CH contact resistance and a method for manufacturing the same, so as to solve the problems of the related art.
In order to achieve the purpose, the invention provides the following technical scheme: an array substrate capable of reducing CH hole contact impedance comprises a substrate, wherein a grid electrode is formed at the upper end of the substrate, grid electrode insulating layers are formed at the upper end of the substrate and the upper end of the grid electrode, an active layer is formed at the upper end of the grid electrode insulating layer and positioned at the right side of the grid electrode, etching barrier layers are formed at the upper end of the grid electrode insulating layer and the upper end of the active layer, etching barrier layer holes and power jacks are etched in the etching barrier layers, an active drain electrode is formed at the upper end of the etching barrier layers, a first insulating layer covers the upper end of the source drain electrode, an organic flat layer is coated at the upper end of the first insulating layer, the organic flat layer is mainly made of organic materials and covers the first insulating layer, organic flat layer holes are formed in the organic flat layer, a touch metal layer is formed at the upper end of the organic flat layer, and second insulating layers are deposited at the upper end of the organic flat layer and the touch metal layer, second insulating layer hole is carved with futilely on the second insulating layer and be located touch-control metal level department, second insulating layer upper end and be located second insulating layer hole department deposit has public electrode layer, public electrode layer passes through second insulating layer hole and touch-control metal level overlap joint, second insulating layer upper end and public electrode layer upper end all deposit have the third insulating layer, be formed with the third insulating layer hole on the third insulating layer, third insulating layer upper end deposit has pure molybdenum metal layer, third insulating layer upper end and pure molybdenum metal layer upper end all are formed with the pixel electrode layer.
The grid electrode is a molybdenum aluminum molybdenum layer or a titanium aluminum titanium layer.
The gate insulating layer is a silicon oxide layer.
The active layer is an indium gallium zinc oxide layer.
The etching barrier layer and the first insulating layer are both silicon oxide layers. The etching barrier layer is an insulating layer with a large dielectric constant and protects the active layer from being etched by source and drain electrode etching liquid or gas; the first insulating layer is an insulating layer with a larger dielectric constant, and can block water and oxygen, so that the influence of the first insulating layer on the stability of a device on the upper end of the substrate is avoided.
The touch metal layer is a molybdenum-aluminum-molybdenum layer.
The second insulating layer and the third insulating layer are both silicon oxide layers or silicon nitride layers. The third insulating layer is an insulating layer with a larger dielectric constant, so that the pixel electrode layer is conveniently connected with the source drain electrode.
The common electrode layer and the pixel electrode layer are both indium tin oxide layers.
The pure molybdenum metal layer is arranged between the pixel electrode layer and the source drain electrode, so that a bridging effect is achieved, and the problem that the third insulating layer is large in impedance due to the fact that the pixel electrode layer is directly overlapped with the source drain electrode is solved.
A manufacturing method of an array substrate capable of reducing CH hole contact impedance specifically comprises the following steps:
s1, sequentially forming a grid electrode and a grid electrode insulating layer on the substrate;
s2, forming an active layer on the upper end of the gate insulation layer corresponding to the right gate;
s3, forming an etching barrier layer at the upper end of the gate insulation layer and the upper end of the active layer, and etching an etching barrier layer hole and a power supply jack;
s4, forming a source drain electrode at the upper end of the etching barrier layer;
s5, covering a first insulating layer on the source and drain electrodes;
s6, coating an organic flat layer on the upper end of the first insulating layer and forming an organic flat layer hole;
s7, forming a touch metal layer on the upper end of the organic flat layer;
s8, depositing a second insulating layer on the touch metal layer, and forming a second insulating layer hole;
s9, depositing a common electrode layer at the upper end of the second insulating layer and at the position of the second insulating layer hole, wherein the common electrode layer is in lap joint with the touch metal layer through the second insulating layer hole;
s10, depositing a third insulating layer on the upper end of the common electrode layer and forming a third insulating layer hole;
s11, depositing a pure molybdenum metal layer on the upper end of the third insulating layer;
s12, coating a negative photoresist layer on the pure molybdenum metal layer, and exposing and developing with a third insulating layer mask;
s13, according to the characteristics of the negative photoresist, after the photoresist at the hole position of the third insulating layer is exposed and developed by the photomask of the third insulating layer, the photoresist at the hole position of the third insulating layer is remained;
s14, wet etching the developed substrate, wherein the pure molybdenum metal layer which is not covered by the photoresist is etched away by using aluminic acid;
s15, performing a film stripping process to remove the negative photoresist layer on the residual pure molybdenum metal layer;
and S16, forming a pixel electrode layer on the upper end of the third insulating layer and the upper end of the pure molybdenum metal layer.
Compared with the prior art, the invention has the beneficial effects that:
1. according to the array substrate capable of reducing the CH hole contact impedance, an additional pure molybdenum metal layer is added after a third insulating layer hole is formed in a third insulating layer and before a pixel electrode layer is formed into a film, and the pure molybdenum metal layer is arranged between a source drain electrode and the pixel electrode layer by using a method of matching a third insulating layer photomask with a negative photoresist to play a role of bridging, so that the contact impedance between the pixel electrode layer and the source drain electrode is reduced, and the normal display of a display screen picture is ensured;
2. the manufacturing method of the array substrate capable of reducing the CH hole contact impedance adds an additional pure molybdenum metal layer after the third insulating layer hole is formed on the third insulating layer and before the pixel electrode layer is formed into a film, coats a negative photoresist layer on the pure molybdenum metal layer, uses a third insulating layer photomask to perform exposure and development, and then performs wet etching, thereby not only effectively improving the impedance problem, but also being beneficial to mass production.
Drawings
FIG. 1 is a schematic view of an array substrate with reduced CH contact resistance according to the present invention;
FIG. 2 is a schematic structural diagram of step S1 of the manufacturing method of an array substrate for reducing CH via contact resistance according to the present invention;
FIG. 3 is a schematic structural diagram of step S2 of the manufacturing method of an array substrate for reducing CH via contact resistance according to the present invention;
FIG. 4 is a schematic structural diagram of step S3 of the manufacturing method of an array substrate for reducing the CH contact resistance according to the present invention;
FIG. 5 is a schematic structural diagram of step S4 of the manufacturing method of an array substrate for reducing the CH contact resistance according to the present invention;
FIG. 6 is a schematic structural diagram of step S5 of the manufacturing method of an array substrate for reducing the CH contact resistance according to the present invention;
FIG. 7 is a schematic structural diagram of step S6 of the method for manufacturing an array substrate capable of reducing the CH contact resistance according to the present invention;
FIG. 8 is a schematic structural diagram of step S7 of the method for manufacturing an array substrate with reduced CH contact resistance according to the present invention;
FIG. 9 is a schematic structural diagram of step S8 of the method for manufacturing an array substrate with reduced CH contact resistance according to the present invention;
FIG. 10 is a schematic structural diagram of step S9 of the method for manufacturing an array substrate with reduced CH contact resistance according to the present invention;
FIG. 11 is a schematic structural diagram of step S10 of the method for manufacturing an array substrate with reduced CH contact resistance according to the present invention;
FIG. 12 is a schematic structural diagram of step S11 of the method for manufacturing an array substrate with reduced CH contact resistance according to the present invention;
FIG. 13 is a schematic structural diagram of step S12 of the method for manufacturing an array substrate with reduced CH contact resistance according to the present invention;
FIG. 14 is a schematic structural diagram of step S13 of the method for manufacturing an array substrate with reduced CH contact resistance according to the present invention;
FIG. 15 is a schematic structural diagram of step S14 of the method for manufacturing an array substrate with reduced CH contact resistance according to the present invention;
FIG. 16 is a schematic structural diagram illustrating a step S15 of the method for manufacturing an array substrate with reduced CH contact resistance according to the present invention;
fig. 17 is a schematic structural diagram of step S16 of the method for manufacturing an array substrate capable of reducing CH hole contact resistance according to the present invention.
In the figure: 1. a substrate; 2. a gate electrode; 3. a gate insulating layer; 4. an active layer; 5. etching the barrier layer; 6. a source and a drain; 7. a first insulating layer; 8. an organic planarization layer; 9. touch-controlling the metal layer; 10. a second insulating layer; 11. a common electrode layer; 12. a third insulating layer; 13. a pure molybdenum metal layer; 14. and a pixel electrode layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the present invention provides a technical solution: an array substrate capable of reducing CH hole contact impedance comprises a substrate 1, wherein the substrate 1 is a basic component of a display device, a grid electrode 2 is formed at the upper end of the substrate 1, the grid electrode 2 is a molybdenum-aluminum-molybdenum layer or a titanium-aluminum-titanium layer, grid insulating layers 3 are formed at the upper end of the substrate 1 and the upper end of the grid electrode 2 respectively, the grid insulating layers 3 are silicon oxide layers, an active layer 4 is formed at the upper end of the grid insulating layer 3 and positioned at the right side of the grid electrode 2, the active layer 4 is an indium-gallium-zinc oxide layer, etching barrier layers 5 are formed at the upper end of the grid insulating layer 3 and the upper end of the active layer 4 respectively, the etching barrier layers 5 are silicon oxide layers, the etching barrier layers 5 are insulating layers with large dielectric constants and protect the active layer 4 from being etched by etching liquid or gas of a source drain electrode 6, etching barrier layer holes and power jacks are etched in the etching barrier layers 5, an active drain electrode 6 is formed at the upper end of the etching barrier layer 5, a first insulating layer 7 covers the upper end of the source drain electrode 6, the first insulating layer 7 is a silicon oxide layer, the first insulating layer 7 is an insulating layer with a large dielectric constant and is used for blocking water and oxygen to avoid the influence on the stability of a device at the upper end of the substrate 1, an organic flat layer 8 is coated at the upper end of the first insulating layer 7, the organic flat layer 8 mainly comprises organic materials and covers the first insulating layer 7, an organic flat layer hole is formed in the organic flat layer 8, a touch metal layer 9 is formed at the upper end of the organic flat layer 8, the touch metal layer 9 is a molybdenum-aluminum-molybdenum layer, a second insulating layer 10 is deposited at the upper end of the organic flat layer 8 and the upper end of the touch metal layer 9, the second insulating layer 10 is a silicon oxide layer or a silicon nitride layer, and a second insulating layer hole is dry-etched in the position, which is positioned on the second insulating layer 10 and is positioned at the touch metal layer 9, a common electrode layer 11 is deposited at the upper end of the second insulating layer 10 and at the position of the second insulating layer hole, the common electrode layer 11 is an indium tin oxide layer, the common electrode layer 11 is in lap joint with the touch metal layer 9 through the second insulating layer hole, third insulating layers 12 are deposited at the upper end of the second insulating layer 10 and the upper end of the common electrode layer 11, the third insulating layer 12 is a silicon oxide layer or a silicon nitride layer, the third insulating layer 12 is an insulating layer with a large dielectric constant, so that the pixel electrode layer 14 is conveniently connected with the source and drain electrodes 6, a third insulating layer hole is formed on the third insulating layer 12, a pure molybdenum metal layer 13 is deposited at the upper end of the third insulating layer 12, the pure molybdenum metal layer 13 is arranged between the pixel electrode layer 14 and the source and drain electrodes 6 to play a role in bridging, and the problem that the impedance of the third insulating layer 12 is large due to the direct lap joint of the pixel electrode layer 14 and the source and drain electrodes 6 is avoided, a pixel electrode layer 14 is formed on the upper end of the third insulating layer 12 and the upper end of the pure molybdenum metal layer 13, and the pixel electrode layer 14 is an indium tin oxide layer.
Referring to fig. 2-17, a method for manufacturing an array substrate capable of reducing CH hole contact resistance includes the following steps:
s1, sequentially forming a gate 2 and a gate insulating layer 3 on the substrate 1;
s2, forming an active layer 4 on the upper end of the gate insulation layer 3 corresponding to the right side gate 2;
s3, forming an etching barrier layer 5 on the upper end of the gate insulating layer 3 and the upper end of the active layer 4, and etching an etching barrier layer hole and a power supply jack;
s4, forming a source drain electrode 6 at the upper end of the etching barrier layer 5;
s5, covering a first insulating layer 7 on the source drain electrode 6;
s6, coating an organic flat layer 8 on the upper end of the first insulating layer 7 and forming an organic flat layer hole;
s7, forming a touch metal layer 9 on the upper end of the organic flat layer 8;
s8, depositing a second insulating layer 10 on the touch metal layer 9, and forming a second insulating layer hole;
s9, depositing a common electrode layer 11 at the upper end of the second insulating layer 10 and at the position of the second insulating layer hole, wherein the common electrode layer 11 is in lap joint with the touch metal layer 9 through the second insulating layer hole;
s10, depositing a third insulating layer 12 on the upper end of the common electrode layer 11 and forming a third insulating layer hole;
s11, depositing a pure molybdenum metal layer 13 on the upper end of the third insulating layer 12;
s12, coating a negative photoresist layer on the pure molybdenum metal layer 13, and performing exposure development by using a third insulating layer photomask;
s13, according to the characteristics of the negative photoresist, after the photoresist at the hole position of the third insulating layer is exposed and developed by the photomask of the third insulating layer, the photoresist at the hole position of the third insulating layer is remained;
s14, wet etching the developed substrate 1, wherein the pure molybdenum metal layer 13 which is not covered by the photoresist is etched away by using aluminic acid;
s15, performing a film stripping process to remove the negative photoresist layer on the residual pure molybdenum metal layer 13;
and S16, forming a pixel electrode layer 14 on the upper end of the third insulating layer 12 and the upper end of the pure molybdenum metal layer 13.
To sum up, compared with the prior art:
1. according to the array substrate capable of reducing the CH hole contact impedance, an additional pure molybdenum metal layer 13 is added after a third insulating layer hole is formed in a third insulating layer 12 and before a pixel electrode layer 14 is formed into a film, the pure molybdenum metal layer 13 is arranged between a source drain electrode 6 and the pixel electrode layer 14 by using a method of matching a third insulating layer photomask with a negative photoresist, so that a bridging effect is achieved, the contact impedance between the pixel electrode layer 14 and the source drain electrode 6 is reduced, and normal display of a display screen picture is guaranteed;
2. the manufacturing method of the array substrate capable of reducing the CH hole contact impedance of the invention adds an additional pure molybdenum metal layer 13 after the third insulating layer hole is opened on the third insulating layer 12 and before the pixel electrode layer 14 is formed into a film, coats a negative photoresist layer on the pure molybdenum metal layer 13, uses the third insulating layer photomask to perform exposure and development, and then performs wet etching, thereby not only effectively improving the impedance problem, but also being beneficial to being applied to mass production.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. An array substrate capable of reducing CH hole contact impedance comprises a substrate (1), and is characterized in that: the organic light-emitting diode display panel is characterized in that a grid electrode (2) is formed at the upper end of a substrate (1), a grid electrode insulating layer (3) is formed at the upper end of the substrate (1) and the upper end of the grid electrode (2), an active layer (4) is formed at the position of the grid electrode (2) and is located at the upper end of the grid electrode (3), an etching barrier layer (5) is formed at the upper end of the grid electrode insulating layer (3) and the upper end of the active layer (4), an etching barrier layer hole and a power jack are etched in the etching barrier layer (5), an active drain electrode (6) is formed at the upper end of the etching barrier layer (5), a first insulating layer (7) covers the upper end of the source drain electrode (6), an organic flat layer (8) is coated at the upper end of the first insulating layer (7), an organic flat layer hole is formed in the organic flat layer (8), a touch metal layer (9) is formed at the upper end of the organic flat layer (8), and a second insulating layer (a touch layer (8) (9) is deposited at the upper end of the touch metal layer 10) The utility model discloses a touch-control metal layer (9) on the first insulating layer (10) and be located the dry etching of touch-control metal layer (9) department and have the second insulating layer hole, second insulating layer (10) upper end and be located second insulating layer hole department deposit and have public electrode layer (11), public electrode layer (11) are through second insulating layer hole and touch-control metal layer (9) overlap joint, second insulating layer (10) upper end and public electrode layer (11) upper end all deposit have third insulating layer (12), be formed with the third insulating layer hole on third insulating layer (12), third insulating layer (12) upper end deposit has pure molybdenum metal layer (13), third insulating layer (12) upper end and pure molybdenum metal layer (13) upper end all are formed with pixel electrode layer (14).
2. The array substrate of claim 1, wherein the array substrate is capable of reducing the contact resistance of the CH hole, and comprises: the grid (2) is a molybdenum aluminum molybdenum layer or a titanium aluminum titanium layer.
3. The array substrate of claim 1, wherein the array substrate is capable of reducing the contact resistance of the CH hole, and comprises: the gate insulating layer (3) is a silicon oxide layer.
4. The array substrate of claim 1, wherein the array substrate is capable of reducing contact resistance of the CH hole, and comprises: the active layer (4) is an indium gallium zinc oxide layer.
5. The array substrate of claim 1, wherein the array substrate is capable of reducing the contact resistance of the CH hole, and comprises: the etching barrier layer (5) and the first insulating layer (7) are both silicon oxide layers.
6. The array substrate of claim 1, wherein the array substrate is capable of reducing the contact resistance of the CH hole, and comprises: the touch metal layer (9) is a molybdenum aluminum molybdenum layer.
7. The array substrate of claim 1, wherein the array substrate is capable of reducing the contact resistance of the CH hole, and comprises: the second insulating layer (10) and the third insulating layer (12) are both silicon oxide layers or silicon nitride layers.
8. The array substrate of claim 1, wherein the array substrate is capable of reducing the contact resistance of the CH hole, and comprises: the common electrode layer (11) and the pixel electrode layer (14) are both indium tin oxide layers.
9. The array substrate of claim 1, wherein the array substrate is capable of reducing the contact resistance of the CH hole, and comprises: the pure molybdenum metal layer (13) is arranged between the pixel electrode layer (14) and the source drain electrode (6).
10. A method for manufacturing an array substrate capable of reducing CH hole contact resistance according to any one of claims 1 to 9, wherein: the method specifically comprises the following steps:
s1, sequentially forming a gate (2) and a gate insulating layer (3) on the substrate (1);
s2, forming an active layer (4) at the position, corresponding to the right side grid (2), of the upper end of the grid insulation layer (3);
s3, forming an etching barrier layer (5) on the upper end of the gate insulating layer (3) and the upper end of the active layer (4), and etching an etching barrier layer hole and a power supply jack;
s4, forming a source drain electrode (6) at the upper end of the etching barrier layer (5);
s5, covering a first insulating layer (7) on the source drain electrode (6);
s6, coating an organic flat layer (8) on the upper end of the first insulating layer (7) and forming an organic flat layer hole;
s7, forming a touch metal layer (9) on the upper end of the organic flat layer (8);
s8, depositing a second insulating layer (10) on the touch metal layer (9) and forming a second insulating layer hole;
s9, depositing a common electrode layer (11) at the upper end of the second insulating layer (10) and at the position of the second insulating layer hole, wherein the common electrode layer (11) is overlapped with the touch metal layer (9) through the second insulating layer hole;
s10, depositing a third insulating layer (12) on the upper end of the common electrode layer (11) and forming a third insulating layer hole;
s11, depositing a pure molybdenum metal layer (13) on the upper end of the third insulating layer (12);
s12, coating a negative photoresist layer on the pure molybdenum metal layer (13), and performing exposure and development by using a third insulating layer photomask;
s13, according to the characteristics of the negative photoresist, after the photoresist at the hole position of the third insulating layer is exposed and developed by the photomask of the third insulating layer, the photoresist at the hole position of the third insulating layer is remained;
s14, wet etching the developed substrate (1), wherein the etching adopts aluminic acid, and the pure molybdenum metal layer (13) which is not covered by the photoresist is etched;
s15, performing a film stripping process to remove the negative photoresist layer on the residual pure molybdenum metal layer (13);
and S16, forming a pixel electrode layer (14) on the upper end of the third insulating layer (12) and the upper end of the pure molybdenum metal layer (13).
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