CN113421887A - Array substrate, preparation method of array substrate and display panel - Google Patents
Array substrate, preparation method of array substrate and display panel Download PDFInfo
- Publication number
- CN113421887A CN113421887A CN202110662072.2A CN202110662072A CN113421887A CN 113421887 A CN113421887 A CN 113421887A CN 202110662072 A CN202110662072 A CN 202110662072A CN 113421887 A CN113421887 A CN 113421887A
- Authority
- CN
- China
- Prior art keywords
- functional layer
- source
- array substrate
- drain
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 164
- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 239000002346 layers by function Substances 0.000 claims abstract description 116
- 239000010409 thin film Substances 0.000 claims abstract description 97
- 238000000034 method Methods 0.000 claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 claims abstract description 38
- 239000010410 layer Substances 0.000 claims description 116
- 239000004065 semiconductor Substances 0.000 claims description 52
- 239000000463 material Substances 0.000 claims description 37
- 229910044991 metal oxide Inorganic materials 0.000 claims description 32
- 150000004706 metal oxides Chemical class 0.000 claims description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 239000004020 conductor Substances 0.000 claims description 18
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 14
- 238000000059 patterning Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 239000011787 zinc oxide Substances 0.000 claims description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 5
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 3
- 229910001887 tin oxide Inorganic materials 0.000 claims description 3
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 21
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 230000000149 penetrating effect Effects 0.000 description 5
- 230000009471 action Effects 0.000 description 3
- 238000005265 energy consumption Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Images
Classifications
-
- H01L27/1214—
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
-
- H01L27/1222—
-
- H01L27/124—
-
- H01L27/1259—
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The embodiment of the application provides an array substrate, a preparation method of the array substrate and a display panel. A first aspect of an embodiment of the present application provides an array substrate, including: a first thin film transistor including a first active structure and a first gate electrode stacked and insulated; and the second thin film transistor comprises a second active structure and a second grid electrode which are stacked and arranged in an insulating mode, wherein the second grid electrode and the first active structure are arranged on the first functional layer, and the first grid electrode and the second active structure are arranged on the second functional layer. The number of mask plates required in the preparation process of the array substrate is reduced, the process in the preparation process of the array substrate is simplified, the production efficiency of the array substrate is improved, and the production cost of the array substrate is reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate and a display panel.
Background
In the field of display technology, it is becoming a research focus to integrate and apply different semiconductor materials as thin film transistors of active structures on the same array substrate to realize low frequency display. However, the integration of different tfts on the same array substrate generally has the problem of complicated process steps, so that the production efficiency of the array substrate and even the display panel including the array substrate is low and the production cost is high.
Therefore, an array substrate, a method for manufacturing the array substrate, and a display panel are urgently needed.
Disclosure of Invention
The embodiment of the application provides an array substrate, a preparation method of the array substrate and a display panel.
A first aspect of an embodiment of the present application provides an array substrate, including:
a first thin film transistor including a first active structure and a first gate electrode stacked and insulated;
a second thin film transistor including a second active structure and a second gate electrode stacked and insulated,
the second grid and the first active structure are arranged on the first functional layer, and the first grid and the second active structure are arranged on the second functional layer.
In the array substrate provided by the first aspect of the embodiment of the application, the first active structure of the first thin film transistor and the second gate of the second thin film transistor are arranged on the same layer of the first functional layer, and the first gate of the first thin film transistor and the second active structure of the second thin film transistor are arranged on the same layer of the second functional layer, so that the number of functional layer required by integrating the array substrate provided with different thin film transistors is reduced, the number of mask plates required in the preparation process of the array substrate is reduced, the process in the preparation process of the array substrate is simplified, the production efficiency of the array substrate is improved, and the production cost of the array substrate is reduced.
The preparation method of the array substrate provided by the second aspect of the embodiment of the present application includes:
providing a semiconductor device substrate with a first functional layer and a second functional layer which are stacked and arranged in an insulating mode, wherein the first functional layer comprises a plurality of second grid electrodes and a plurality of first active structures, and the second functional layer comprises a plurality of first grid electrodes and a plurality of second active structures;
and forming an interlayer insulating layer and a third functional layer on one side of the second functional layer, which faces away from the first functional layer, wherein the third functional layer comprises a plurality of first source drain layers connected with the first active structure through via holes and a plurality of second source drain layers connected with the second active structure through via holes, the first source drain layers, the first grid electrodes and the first active structure which correspond to each other form a first thin film transistor, and the second source drain layers, the second grid electrodes and the second active structure which correspond to each other form a second thin film transistor.
The array substrate manufacturing method provided by the second aspect of the embodiment of the application simplifies the process of the array substrate which needs to integrate different thin film transistors, reduces the number of functional layers of the array substrate, improves the production efficiency of the array substrate, and reduces the production cost of the array substrate.
The display panel provided by the third aspect of the embodiments of the present application has the array substrate of the first aspect of the present application.
The array substrate integrates two thin film transistors in the display panel of the third aspect of the embodiment of the application, so that the display panel is favorable for low-frequency display, and the production efficiency and the production cost of the display panel are improved.
Drawings
Other features, objects and advantages of the invention will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.
Fig. 1 is a schematic view of a partial layered structure of an array substrate according to an embodiment of the array substrate provided in the first aspect of the present application;
fig. 2 is a schematic view of a partial layered structure of an array substrate in another embodiment of the array substrate provided in the first aspect of the present application;
fig. 3 is a schematic view of a partial layered structure of an array substrate in yet another embodiment of the array substrate provided by the first aspect of the present application;
fig. 4 is a schematic diagram of a partial layer structure of an array substrate in still another embodiment of the array substrate provided by the first aspect of the present application;
fig. 5 is a schematic view of a partial layered structure of an array substrate according to still another embodiment of the array substrate provided in the first aspect of the present application;
fig. 6 is a schematic view of a partial layered structure of an array substrate according to still another embodiment of the array substrate provided in the first aspect of the present application;
FIG. 7 is a flowchart illustrating steps of one embodiment of a method for fabricating an array substrate provided in the second aspect of the present application;
FIG. 8 is a flowchart illustrating a step of another embodiment of a method for manufacturing an array substrate according to a second aspect of the present application;
FIG. 9 is a flowchart illustrating steps of one embodiment of a method for fabricating an array substrate provided by a second aspect of the present application;
FIG. 10 is a flowchart illustrating a step of another embodiment of a method for manufacturing an array substrate according to a second aspect of the present application;
FIG. 11 is a flowchart illustrating a step of another embodiment of a method for manufacturing an array substrate according to a second aspect of the present application;
FIG. 12 is a flowchart illustrating a step of a further embodiment of a method for manufacturing an array substrate according to the second aspect of the present application;
fig. 13 is a flowchart illustrating a step of another embodiment of a method for manufacturing an array substrate according to a second aspect of the present application.
In the figure:
a first thin film transistor-1; a first active structure-11; a first gate-12; a first gate link-121; a first source-13; a first drain electrode-14;
a second thin film transistor-2; a second active structure-21; a second gate-22; a second gate link-221; a second source-23; a second drain-24;
a substrate-31; a first functional layer-32; a first insulating layer-33; a second functional layer-34; a second insulating layer-35; a third functional layer-36;
drain connector-41; source connection-42; channel structure-43;
a source region-A; a drain region-B; channel region-C.
Detailed Description
Features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Materials for integrating active structures on the same array substrate are respectively from different thin film transistors of silicon-based semiconductor materials and Metal oxides (Metal oxides), so that low frequency display is becoming a research hotspot. However, the inventors of the present invention have found in intensive studies that a difficulty in integrating a thin film transistor using a silicon-based semiconductor material and a thin film transistor using a metal oxide as a semiconductor material on the same array substrate is that different active structure materials of the thin film transistors cause different process steps, and thus, the process for preparing the array substrate is complicated and requires a large number of mask plates, resulting in low production efficiency and high production cost of the array substrate.
The present application has been made in view of the finding of the above-mentioned technical problems.
As shown in fig. 1, a first aspect of the present application provides an array substrate, which includes a first thin film transistor 1 and a second thin film transistor 2. The first thin film transistor 1 includes a first active structure 11 and a first gate 12 that are stacked and insulated, and the second thin film transistor 2 includes a second active structure and a second gate 22 that are stacked and insulated, where the second gate 22 and the first active structure 11 are located in the first functional layer 32, and the first gate 12 and the second active structure are located in the second functional layer 34. The first functional layer 32 and the second functional layer 34 are insulated from each other by a first insulating layer 33.
In the array substrate provided by the first aspect of the embodiment of the application, the first active structure of the first thin film transistor and the second gate of the second thin film transistor are arranged on the same layer of the first functional layer, and the first gate of the first thin film transistor and the second active structure of the second thin film transistor are arranged on the same layer of the second functional layer, so that the number of functional layer required by integrating the array substrate provided with different thin film transistors is reduced, the number of mask plates required in the preparation process of the array substrate is reduced, the process in the preparation process of the array substrate is simplified, the production efficiency of the array substrate is improved, and the production cost of the array substrate is reduced.
As shown in fig. 2, in some optional embodiments, the array substrate further includes a substrate 31, the first thin film transistor 1 and the second thin film transistor 2 are disposed on the substrate 31, and the first functional layer 32 is disposed close to the substrate 31 relative to the second functional layer 34. The first thin film transistor 1 and the second thin film transistor 2 both include a source drain layer, the source drain layer of the first thin film transistor 1 and the source drain layer of the second thin film transistor 2 are located on the third functional layer 36, and the third functional layer 36 is disposed on a side of the second functional layer 34 facing away from the first functional layer 32.
In some alternative embodiments, the first functional layer 32, the second functional layer 34, and the third functional layer 36 are all insulated by an interlayer insulating layer.
In some examples, the first functional layer 32 is provided insulated from the second functional layer 34 by the first insulating layer 33. The second functional layer 34 and the third functional layer 36 are insulated from each other by a second insulating layer 35. The source-drain layers of the first thin film transistor 1 located at the third functional layer 36 include the first source electrode 13 and the first drain electrode 14. The first source electrode 13 and the first drain electrode 14 are connected to the first active structure 11 of the first thin film transistor 1 through a via hole penetrating the first insulating layer 33 and the second insulating layer 35. The source-drain layer of the second thin film transistor 2 located at the third functional layer 36 includes the second source electrode 23 and the second drain electrode 24. The second source electrode 23 and the second drain electrode 24 are connected to the second active structure 21 of the second thin film transistor 2 through a via hole penetrating the second insulating layer 35. The third functional layer 36 further includes a first gate line 121, and the first gate line 121 is connected to the first gate electrode 12 of the first thin film transistor 1 through a via hole penetrating the second insulating layer 35. The third functional layer 36 further includes a second gate line 221, and the second gate line 221 is connected to the second gate electrode of the second thin film transistor 2 through a via hole penetrating the first and second insulating layers 33 and 35.
As shown in fig. 3, in some alternative embodiments, the second active structure 21 of the second thin film transistor 2 includes a source connection member 42, a drain connection member 41 and a channel structure 43, the source connection member 42 and the drain connection member 41 are connected to the channel structure 43, the first gate 12, the source connection member 42 and the drain connection member 41 are located on the same metal layer, and the first active structure 11 and the second gate 22 both include a body material, which is a silicon-based semiconductor material. In some embodiments, the Silicon-based semiconductor material includes Low Temperature polysilicon ("LTPS") and Amorphous Silicon (a-Si). In some embodiments, the silicon-based semiconductor material is low temperature polysilicon. The low-temperature polysilicon has high electron mobility which is hundreds times of that of amorphous silicon materials, shortens the corresponding time of the display panel and enables the area ratio of a pixel circuit to be smaller. In some examples, the first active structure 11 includes a conductive source region a and drain region B obtained by partially conducing a body material, and a semiconductive channel region C composed of a body material that has not been subjected to the conductimerization process. The source connection 42 and the drain connection 41 of the first gate 12 and the second thin film transistor 2 are located in the same metal layer, the source connection 42 and the drain connection 41 of the first gate 12 and the second thin film transistor 2 are formed simultaneously by the same process, and the source connection 42 and the drain connection 41 of the first gate 12 and the second thin film transistor 2 are made of the same conductive material.
In some embodiments, the channel structure 43 is a metal oxide layer including any one of indium zinc oxide, indium gallium zinc oxide, and tin oxide. In some examples, the metal oxide layer is comprised of indium gallium zinc oxide. In some examples, two types of thin film transistors are integrated on the same array substrate at the same time, one of the two types of thin film transistors adopts a metal oxide semiconductor material to manufacture an active structure of the thin film transistor, and a switch responsible for a pixel circuit can enable a pixel to keep a longer on-time under the condition of ensuring less electric leakage, so that a lower refresh rate of a display panel is realized; the other of the two thin film transistors adopts a silicon-based semiconductor material to manufacture an active structure of the thin film transistor, and can realize smaller driving current and lower driving voltage when used for driving the pixel circuit. The display panel comprising the array substrate can realize low-frequency display, and the energy consumption of the display panel is saved by reducing the refresh rate.
In some alternative embodiments, the orthographic projection of the channel structure 43 on the substrate 31 partially overlaps the orthographic projection of the source connection 42 on the substrate 31, and/or the orthographic projection of the channel structure 43 on the substrate 31 partially overlaps the orthographic projection of the drain connection 41 on the substrate 31.
In some embodiments, a portion of the channel structure 43 is located between the source connection 42 and the drain connection 41, and another portion of the channel structure 43 is disposed in a stack with the source connection 42 and the drain connection 41.
In some embodiments, the array substrate further includes a fourth functional layer located on a side of the third functional layer opposite to the substrate, the fourth functional layer includes a plurality of signal lines, and at least a portion of the signal lines are connected to the third functional layer through via holes. In some examples, the signal line in the fourth functional layer includes a power supply voltage signal line (Vdd line), a data signal line (Vdata), and the like. In these embodiments, the third functional layer includes signal lines such as gate lines. Different signal lines are respectively arranged on the third functional layer and the fourth functional layer in the array substrate, so that the wiring space of the signal lines is increased, the line width and the line distance between the signal lines can be increased, and the simplification of the wiring structure of the array substrate is facilitated.
As shown in fig. 3, in some examples, a portion of the channel structure 43 of the second thin film transistor 2 is located between the source connection 42 and the drain connection 41. Another part of the channel structure 43 is arranged in a layer with the source connection 42 and the drain connection 41, and this other part of the channel structure 43 is located on the side of the source connection 42 and the drain connection 41 facing away from the first functional layer 32.
As shown in fig. 4, in some examples, a portion of the channel structure 43 of the second thin film transistor 2 is located between the source connection 42 and the drain connection 41. Another portion of the channel structure 43 is disposed in a stack with the source and drain connections 42 and 41. The source connection 42 of the second thin film transistor 2 comprises a portion extending towards the drain connection 41, a portion of the source connection 42 extending towards the drain connection 41 being located on a side of another portion of the channel structure 43 facing away from the first functional layer 32. The drain connection 41 of the second thin film transistor 2 comprises a portion extending towards the source connection 42, the portion of the drain connection 41 extending towards the source connection 42 being located on a side of the other portion of the channel structure 43 facing away from the first functional layer 32.
As shown in fig. 5, in some alternative embodiments, the first active structure 11 of the first thin film transistor 1 includes a source connection 42, a drain connection 41 and a channel structure 43, the source connection 42 and the drain connection 41 are connected to the channel structure 43, the second gate 22, the source connection 42 and the drain connection 41 are located in the same metal layer, and the second active structure 21 and the first gate 12 both include a body material, which is a silicon-based semiconductor material. In some embodiments, the Silicon-based semiconductor material includes Low Temperature polysilicon ("LTPS") and Amorphous Silicon (a-Si). In some embodiments, the silicon-based semiconductor material is low temperature polysilicon. The low-temperature polysilicon has high electron mobility which is hundreds times of that of amorphous silicon materials, shortens the corresponding time of the display panel and enables the area ratio of a pixel circuit to be smaller. In some examples, the second active structure 21 includes a conductive source region a and drain region B obtained by partially conducting a body material, and a semiconductive channel region C composed of a body material that has not been subjected to the conducting process. The second gate 22 and the source connection 42 and the drain connection 41 of the first thin film transistor 1 are located in the same metal layer, the second gate 22 and the source connection 42 and the drain connection 41 of the first thin film transistor 1 are formed simultaneously by the same process, and the second gate 22 and the source connection 42 and the drain connection 41 of the first thin film transistor 1 are made of the same conductive material.
In some embodiments, the channel structure 43 is a metal oxide layer including any one of indium zinc oxide, indium gallium zinc oxide, and tin oxide. In some examples, the metal oxide layer is comprised of indium gallium zinc oxide. In some examples, two types of thin film transistors are integrated on the same array substrate at the same time, one of the two types of thin film transistors adopts a metal oxide semiconductor material to manufacture an active structure of the thin film transistor, and a switch responsible for a pixel circuit can enable a pixel to keep a longer on-time under the condition of ensuring less electric leakage, so that a lower refresh rate of a display panel is realized; the other of the two thin film transistors adopts a silicon-based semiconductor material to manufacture an active structure of the thin film transistor, and can realize smaller driving current and lower driving voltage when used for driving the pixel circuit. The display panel comprising the array substrate can realize low-frequency display, and the energy consumption of the display panel is saved by reducing the refresh rate.
In some alternative embodiments, the orthographic projection of the channel structure 43 on the substrate 31 partially overlaps the orthographic projection of the source connection 42 on the substrate 31, and/or the orthographic projection of the channel structure 43 on the substrate 31 partially overlaps the orthographic projection of the drain connection 41 on the substrate 31.
In some embodiments, a portion of the channel structure 43 is located between the source connection 42 and the drain connection 41, and another portion of the channel structure 43 is disposed in a stack with the source connection 42 and the drain connection 41.
Referring also to fig. 5, in some examples, a portion of the channel structure 43 of the first thin film transistor 1 is located between the source connection 42 and the drain connection 41. Another portion of the channel structure 43 is disposed in a stacked relationship with the source and drain contacts 42 and 41, and the other portion of the channel structure 43 is located on a side of the source and drain contacts 42 and 41 facing the second functional layer 34.
As shown in fig. 6, in some examples, a portion of the channel structure 43 of the first thin film transistor 1 is located between the source connector 42 and the drain connector 41. Another portion of the channel structure 43 is disposed in a stack with the source and drain connections 42 and 41. The source connection 42 of the first thin film transistor 1 comprises a portion extending towards the drain connection 41, a portion of the source connection 42 extending towards the drain connection 41 being located on a side of another portion of the channel structure 43 facing the second functional layer 34. The drain contact 41 of the first thin film transistor 1 comprises a portion extending towards the source contact 42, and a portion of the drain contact 41 extending towards the source contact 42 is located on a side of another portion of the channel structure 43 facing the second functional layer 34.
As shown in fig. 7, a second aspect of the embodiments of the present application provides a method for manufacturing an array substrate, including:
and S10, providing a semiconductor device substrate with a first functional layer and a second functional layer which are stacked and insulated, wherein the first functional layer comprises a plurality of second grid electrodes and a plurality of first active structures, and the second functional layer comprises a plurality of first grid electrodes and a plurality of second active structures.
And S20, forming an interlayer insulating layer and a third functional layer on one side of the second functional layer, which faces away from the first functional layer, wherein the third functional layer comprises a plurality of first source drain layers connected with the first active structure through via holes and a plurality of second source drain layers connected with the second active structure through via holes, the first source drain layers, the first grid electrodes and the first active structure which correspond to each other form a first thin film transistor, and the second source drain layers, the second grid electrodes and the second active structure which correspond to each other form a second thin film transistor.
As shown in fig. 8, in some alternative embodiments, step S10 includes:
s11, providing a substrate.
And S12, forming a first functional layer on one side of the substrate, wherein a patterned semiconductor layer is formed by silicon-based semiconductor materials, the semiconductor layer comprises a plurality of semiconductor units, a part of the semiconductor units are subjected to complete conductor processing to form a second grid, and the other part of the semiconductor units are subjected to partial conductor processing to form a first active structure with a source region, a drain region and a channel region.
S13, a first insulating layer is formed on the side of the first functional layer facing away from the substrate.
S14, forming a second functional layer on a side of the first insulating layer opposite to the substrate, wherein a metal layer is formed by using a conductive material and is patterned to form a plurality of first gates and a plurality of pairs of spaced source and drain connectors, a plurality of channel structures are formed by using a metal oxide, and each channel structure is connected to a corresponding pair of source and drain connectors to form a plurality of second active structures.
In these embodiments, in step S12, the silicon-based semiconductor material is used in combination with a conductor treatment on the silicon-based semiconductor material during the process of forming the first functional layer on the array substrate, so that the first active structure of the first thin film transistor and the second gate of the second thin film transistor are formed simultaneously during the same process. Step S13 is to insulate the first functional layer from the second functional layer through a first insulating layer, so as to further reduce the number of insulating layers required by the array substrate, thereby reducing the thickness of the array substrate and simplifying the process. In step S14, the first gate of the first tft and the source and drain connectors of the second tft are formed simultaneously in the same process using the same conductive material. The method has the advantages that the process steps of conducting treatment on the semiconductor unit formed by the metal oxide to form the conducting source region and the conducting drain region in the second active structure of the second thin film transistor are reduced, the preparation steps of the array substrate integrating different thin film transistors are simplified, the number of mask plates in the process of preparing the array substrate is reduced, the production efficiency of the array substrate is improved, and the production cost of the array substrate is reduced.
As shown in fig. 9, in some examples, step S14 includes:
s141a, forming a metal layer on a side of the first insulating layer opposite to the substrate using a conductive material, and patterning the metal layer to form a plurality of first gates and a plurality of pairs of spaced source and drain connectors.
S142a, after step S141 is completed, forming a metal oxide layer on a side of the patterned metal layer opposite to the substrate using a metal oxide, patterning the metal oxide layer to form a plurality of channel structures, and disposing each channel structure in connection with a corresponding pair of source and drain connectors to form a plurality of second active structures.
In these examples, in the array substrate manufactured by the method for manufacturing an array substrate according to the second aspect of the embodiments of the present application, a portion of the channel structure of the second thin film transistor is located between the source connection member and the drain connection member. Another part of the channel structure is arranged in a layer with the source and drain connections and is located on a side of the source and drain connections facing away from the first functional layer.
As shown in fig. 10, in other examples, step S14 includes:
s141b, forming a metal oxide layer on a side of the first insulating layer opposite to the substrate using a metal oxide, and patterning the metal oxide layer to form a plurality of channel structures.
S142b, forming a metal layer on the side of the patterned metal oxide layer opposite to the substrate, patterning the metal layer to form a plurality of first gates and a plurality of pairs of spaced source and drain connectors, and connecting each channel structure to a corresponding pair of source and drain connectors to form a plurality of second active structures.
In these examples, in the array substrate manufactured by the method for manufacturing an array substrate according to the second aspect of the embodiments of the present application, a portion of the channel structure of the second thin film transistor is located between the source connection member and the drain connection member. Another portion of the channel structure is disposed in a stack with the source and drain connections. The source connection of the second thin film transistor comprises a portion extending towards the drain connection, the portion of the source connection extending towards the drain connection being located on a side of the other portion of the channel structure facing away from the first functional layer. The drain connection of the second thin film transistor comprises a portion extending towards the source connection, the portion of the drain connection extending towards the source connection being located on a side of the other portion of the channel structure facing away from the first functional layer.
As shown in fig. 11, in some alternative embodiments, step S10 includes:
s11', providing a substrate.
S12', forming a first functional layer on one side of the substrate, wherein a metal layer is formed using a conductive material and patterned to form a plurality of second gates and a plurality of pairs of spaced source and drain connectors, a plurality of channel structures are formed using a metal oxide, and each channel structure is connected to a corresponding pair of source and drain connectors to form a plurality of first active structures.
S13', forming a first insulating layer on a side of the first functional layer facing away from the substrate;
s14', forming a second functional layer on a side of the first insulating layer opposite to the substrate, wherein a patterned semiconductor layer is formed using a silicon-based semiconductor material, the semiconductor layer includes a plurality of semiconductor cells, a portion of the semiconductor cells is fully conductively processed to form a plurality of first gates, and another portion of the semiconductor cells is partially conductively processed to form a plurality of second active structures having source, drain and channel regions.
In these embodiments, step S12' allows the second gate of the second tft and the source and drain connectors of the first tft to be formed simultaneously in the same process using the same conductive material. The method has the advantages that the process steps of conducting treatment on the semiconductor unit formed by the metal oxide to form the conducting source region and the conducting drain region in the first active structure of the first thin film transistor are reduced, the preparation steps of the array substrate integrating different thin film transistors are simplified, the number of mask plates in the process of preparing the array substrate is reduced, the production efficiency of the array substrate is improved, and the production cost of the array substrate is reduced. Step S13' allows the first functional layer and the second functional layer to be isolated by a first insulating layer, which further reduces the number of insulating layers required by the array substrate, and realizes the reduction of the thickness of the array substrate and the simplification of the process. In step S14', a silicon-based semiconductor material is used in combination with a conductor processing means for the silicon-based semiconductor material in the process of forming the second functional layer on the array substrate, so that the second active structure of the second thin film transistor and the second gate of the first thin film transistor are formed simultaneously in the same process, thereby further simplifying the preparation process of the array substrate integrating different thin film transistors.
As shown in fig. 12, in some examples, step S12 includes:
s121a, a metal layer is formed on one side of the substrate using a conductive material, and the metal layer is patterned to form a plurality of second gates and a plurality of pairs of spaced source and drain connectors.
S122a, after step S121a is completed, a metal oxide layer is formed on a side of the patterned metal layer opposite to the substrate by using a metal oxide, the metal oxide layer is patterned to form a plurality of channel structures, and each channel structure is connected to a corresponding pair of source and drain connectors to form a plurality of second active structures.
In these examples, in the array substrate manufactured by the method for manufacturing an array substrate according to the second aspect of the embodiments of the present application, a portion of the channel structure of the first thin film transistor is located between the source connection member and the drain connection member. Another portion of the channel structure is disposed in a stacked relationship with the source and drain connectors, and the other portion of the channel structure is located on a side of the source and drain connectors facing the second functional layer.
As shown in fig. 13, in some examples, step S12 includes:
s121b, a metal oxide layer is formed on one side of the substrate using a metal oxide, and the metal oxide layer is patterned to form a plurality of channel structures.
S122b, forming a metal layer on the side of the patterned metal oxide layer opposite to the substrate, and patterning the metal layer to form a plurality of second gates and a plurality of pairs of spaced source and drain connectors, and connecting each channel structure to a corresponding pair of source and drain connectors to form a first active structure of a plurality of first tfts.
In these examples, as shown in fig. 6, in the array substrate manufactured by the method for manufacturing an array substrate according to the second aspect of the embodiment of the present application, a portion of the channel structure of the first thin film transistor is located between the source connection member and the drain connection member. Another portion of the channel structure is disposed in a stack with the source and drain connections. The source connection of the first thin film transistor comprises a portion extending towards the drain connection, a portion of the source connection extending towards the drain connection being located at a side of another portion of the channel structure facing the second functional layer. The drain connection of the first thin film transistor comprises a portion extending towards the source connection, the portion of the drain connection extending towards the source connection being located on a side of the other portion of the channel structure facing the second functional layer.
The display panel provided by the third aspect of the embodiments of the present application has the array substrate of the first aspect of the present application.
In some embodiments, the display panel of the third aspect of embodiments of the present application includes a light emitting device layer. The light-emitting device layer is arranged on one side of the array substrate and comprises a plurality of sub-pixels distributed in an array mode, and the sub-pixels comprise a first electrode layer, a light-emitting layer and a second electrode layer which are arranged in a stacked mode. In some examples, the first electrode layer is an anode layer, and the first electrode layer is disposed closer to a third functional layer of the array substrate than the second electrode layer, and the first electrode layer is connected to the third functional layer. A planarization layer is arranged between the light emitting device layer and the array substrate, and the first electrode layer is arranged on one side, back to the array substrate, of the planarization layer. In some examples, the planarization layer is formed using an organic material. The first electrode layer is connected with the third functional layer through a via hole penetrating through the planarization layer.
The array substrate integrates two thin film transistors in the display panel of the third aspect of the embodiment of the application, so that the display panel is favorable for low-frequency display, and the production efficiency and the production cost of the display panel are improved.
In accordance with the above-described embodiments of the present invention, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. An array substrate, comprising:
a first thin film transistor including a first active structure and a first gate electrode stacked and insulated;
a second thin film transistor including a second active structure and a second gate electrode stacked and insulated,
the second grid and the first active structure are arranged on a first functional layer, and the first grid and the second active structure are arranged on a second functional layer.
2. The array substrate of claim 1, further comprising a substrate, wherein the first thin film transistor and the second thin film transistor are disposed on the substrate, and wherein the first functional layer is disposed adjacent to the substrate relative to the second functional layer;
the first thin film transistor and the second thin film transistor both comprise source drain layers, the source drain layers of the first thin film transistor and the source drain layers of the second thin film transistor are located on a third functional layer, and the third functional layer is arranged on one side, back to the first functional layer, of the second functional layer.
3. The array substrate of claim 2, wherein the first functional layer, the second functional layer and the third functional layer are all insulated by an interlayer insulating layer;
preferably, the array substrate further includes a fourth functional layer located on a side of the third functional layer opposite to the substrate, the fourth functional layer includes a plurality of signal lines, and at least a portion of the signal lines are connected to the third functional layer through via holes.
4. The array substrate of any one of claims 1 to 3, wherein the second active structure comprises a source connection member, a drain connection member and a channel structure, the source connection member and the drain connection member are connected to the channel structure, the first gate, the source connection member and the drain connection member are located on a same metal layer, the first active structure and the second gate both comprise a body material, and the body material is a silicon-based semiconductor material; or,
the first active structure comprises a source electrode connecting piece, a drain electrode connecting piece and a channel structure, the source electrode connecting piece and the drain electrode connecting piece are connected with the channel structure, the second grid electrode, the source electrode connecting piece and the drain electrode connecting piece are located on the same metal layer, the second active structure and the first grid electrode both comprise main body materials, and the main body materials are silicon-based semiconductor materials;
preferably, the silicon-based semiconductor material is low-temperature polysilicon.
5. The array substrate of claim 4,
the channel structure is a metal oxide layer, and the metal oxide layer comprises any one of indium zinc oxide, indium gallium zinc oxide, zinc oxide and tin oxide;
preferably, the metal oxide layer is made of indium gallium zinc oxide.
6. The array substrate of claim 4, wherein an orthographic projection of the channel structure on the substrate partially overlaps with an orthographic projection of the source connector on the substrate, and/or an orthographic projection of the channel structure on the substrate partially overlaps with an orthographic projection of the drain connector on the substrate.
7. The array substrate of claim 6, wherein a portion of the channel structure is between the source structure and the drain structure and another portion of the channel structure is stacked with the source connection and the drain connection.
8. A preparation method of an array substrate is characterized by comprising the following steps:
providing a semiconductor device substrate with a first functional layer and a second functional layer which are stacked and arranged in an insulating mode, wherein the first functional layer comprises a plurality of second grid electrodes and a plurality of first active structures, and the second functional layer comprises a plurality of first grid electrodes and a plurality of second active structures;
and forming an interlayer insulating layer and a third functional layer on one side of the second functional layer, which faces away from the first functional layer, wherein the third functional layer comprises a plurality of first source drain layers connected with the first active structure through via holes and a plurality of second source drain layers connected with the second active structure through via holes, the first source drain layers, the first grid and the first active structure which correspond to each other form a first thin film transistor, and the second source drain layers, the second grid and the second active structure which correspond to each other form a second thin film transistor.
9. The method for manufacturing an array substrate according to claim 8, wherein the step of providing a semiconductor device substrate having a first functional layer and a second functional layer stacked and insulated from each other comprises:
providing a substrate;
forming the first functional layer on one side of a substrate, wherein a patterned semiconductor layer is formed by using a silicon-based semiconductor material, the semiconductor layer comprises a plurality of semiconductor units, a part of the semiconductor units are subjected to complete conductor processing to form the second grid, and another part of the semiconductor units are subjected to partial conductor processing to form the first active structure with a source region, a drain region and a channel region;
forming a first insulating layer on one side of the first functional layer, which faces away from the substrate;
forming a second functional layer on a side of the first insulating layer opposite to the substrate, wherein a metal layer is formed by using a conductive material and is subjected to patterning treatment to form a plurality of first gates and a plurality of pairs of spaced source and drain connectors, a plurality of channel structures are formed by using a metal oxide, and each channel structure is connected with each corresponding pair of the source and drain connectors to form a plurality of second active structures;
preferably, the step of providing a semiconductor device substrate having a first functional layer and a second functional layer stacked and insulated from each other includes:
providing a substrate;
forming the first functional layer on one side of a substrate, wherein a metal layer is formed by using a conductive material and is subjected to patterning treatment to form a plurality of second gates and a plurality of pairs of source and drain connectors arranged at intervals, a plurality of channel structures are formed by using a metal oxide, and each channel structure is connected with each corresponding pair of the source and drain connectors to form a plurality of first active structures;
forming a first insulating layer on one side of the first functional layer, which faces away from the substrate;
and forming the second functional layer on the side, opposite to the substrate, of the first insulating layer, wherein a patterned semiconductor layer is formed by using a silicon-based semiconductor material, the semiconductor layer comprises a plurality of semiconductor units, a part of the semiconductor units are subjected to complete conductor processing to form a plurality of first grid electrodes, and another part of the semiconductor units are subjected to partial conductor processing to form a plurality of second active structures with source regions, drain regions and channel regions.
10. A display panel comprising the array substrate according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110662072.2A CN113421887A (en) | 2021-06-15 | 2021-06-15 | Array substrate, preparation method of array substrate and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110662072.2A CN113421887A (en) | 2021-06-15 | 2021-06-15 | Array substrate, preparation method of array substrate and display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113421887A true CN113421887A (en) | 2021-09-21 |
Family
ID=77788544
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110662072.2A Pending CN113421887A (en) | 2021-06-15 | 2021-06-15 | Array substrate, preparation method of array substrate and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113421887A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106057825A (en) * | 2016-08-03 | 2016-10-26 | 深圳市华星光电技术有限公司 | Array substrate of OLED display device and manufacture method of array substrate |
| CN106558592A (en) * | 2015-09-18 | 2017-04-05 | 鸿富锦精密工业（深圳）有限公司 | The preparation method of array base palte, display device and array base palte |
| CN107452808A (en) * | 2017-07-04 | 2017-12-08 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte and display device |
| CN107863354A (en) * | 2017-10-20 | 2018-03-30 | 武汉华星光电技术有限公司 | Array base palte and preparation method thereof |
| CN110491887A (en) * | 2019-08-23 | 2019-11-22 | 上海中航光电子有限公司 | A kind of production method of array substrate, display panel and array substrate |
| CN110649043A (en) * | 2019-09-30 | 2020-01-03 | 厦门天马微电子有限公司 | Array substrate, display panel, display device and preparation method of array substrate |
-
2021
- 2021-06-15 CN CN202110662072.2A patent/CN113421887A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106558592A (en) * | 2015-09-18 | 2017-04-05 | 鸿富锦精密工业（深圳）有限公司 | The preparation method of array base palte, display device and array base palte |
| CN106057825A (en) * | 2016-08-03 | 2016-10-26 | 深圳市华星光电技术有限公司 | Array substrate of OLED display device and manufacture method of array substrate |
| CN107452808A (en) * | 2017-07-04 | 2017-12-08 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte and display device |
| CN107863354A (en) * | 2017-10-20 | 2018-03-30 | 武汉华星光电技术有限公司 | Array base palte and preparation method thereof |
| CN110491887A (en) * | 2019-08-23 | 2019-11-22 | 上海中航光电子有限公司 | A kind of production method of array substrate, display panel and array substrate |
| CN110649043A (en) * | 2019-09-30 | 2020-01-03 | 厦门天马微电子有限公司 | Array substrate, display panel, display device and preparation method of array substrate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110649043B (en) | Array substrate, display panel, display device and preparation method of array substrate | |
| KR102519087B1 (en) | Display device and method for manufacturing the same | |
| KR100491141B1 (en) | TFT and Method for Fabricating the Same and Active Matrix display device and Method for fabricating the Same using the TFT | |
| TWI425634B (en) | Organic light emitting display device and fabricating method thereof | |
| CN107170764B (en) | Array substrate, manufacturing method of array substrate, display panel and display device | |
| CN1873989B (en) | Thin film transistor and method of fabricating thin film transistor substrate | |
| JP6125155B2 (en) | Semiconductor device and flat panel display device including the same | |
| CN105702744B (en) | Thin film transistor, manufacturing method thereof, array substrate and display device | |
| US20020149710A1 (en) | Flat panel display device and method of manufacturing the same | |
| CN105280137A (en) | Organic light emitting display and method of fabricating the same | |
| CN111710685B (en) | Display panel, manufacturing method thereof and display device | |
| CN109427820B (en) | Substrate for display device, preparation method of substrate and display panel | |
| US6805602B2 (en) | Method of manufacturing flat panel display device | |
| KR20050052305A (en) | Flat panel display and fabrication method of the same | |
| CN109037343B (en) | Double-layer channel thin film transistor, preparation method thereof and display panel | |
| CN112992936A (en) | Display back plate manufacturing method, display back plate and display device | |
| US6635504B2 (en) | Method of manufacturing organic EL display | |
| US8610126B2 (en) | Flat panel display device with simplified efficient structure and method of manufacturing the same | |
| KR20040092916A (en) | TFT and Flat panel device using the same | |
| US20080054268A1 (en) | Display device and method of manufacturing the display device | |
| KR102449066B1 (en) | Array Substrate For Display Device And Method Of Fabricating The Same | |
| CN113421887A (en) | Array substrate, preparation method of array substrate and display panel | |
| CN112397527B (en) | Array substrate and manufacturing method thereof | |
| JP2007535164A (en) | Coplanar thin film transistor with additional source and drain insulation layers | |
| CN107797344A (en) | Array base palte, display panel and its manufacture method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |