CN112397527B - Array substrate and manufacturing method thereof - Google Patents
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- CN112397527B CN112397527B CN202011269221.0A CN202011269221A CN112397527B CN 112397527 B CN112397527 B CN 112397527B CN 202011269221 A CN202011269221 A CN 202011269221A CN 112397527 B CN112397527 B CN 112397527B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The invention discloses an array substrate and a manufacturing method thereof. The array substrate comprises a substrate, a first metal layer, a grid electrode insulating layer, an active layer, a second metal layer, a grid electrode layer, a passivation layer and an electrode routing layer. According to the invention, the plurality of transistor units are arranged on the array substrate, so that two channel switches or one channel switch and one capacitor can be formed in each transistor unit, and the gate layer is longitudinally arranged, so that the bending flexibility is improved, and the condition that the threshold voltage of the transistor units drifts is reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a manufacturing method thereof.
Background
Organic Light Emitting Diodes (OLEDs) have a series of advantages such as wide viewing angle, wide color gamut, high contrast, low power consumption, and foldable/flexible characteristics, and have a competitive power and a development prospect in new generation display technologies, wherein an Active Matrix Organic Light Emitting Diode (AMOLED) technology is one of the key development directions of the current display technologies.
Indium Gallium Zinc Oxide (IGZO) is used as an amorphous oxide semiconductor thin film in a substrate transistor (TFT), the carrier mobility of the IGZO is 20-30 times that of amorphous silicon, the charge and discharge rate of the TFT to a pixel electrode can be greatly improved, the response speed of the pixel is improved, the higher refresh rate is realized, the higher response also greatly improves the row scanning rate of the pixel, and the large-size ultrahigh-resolution panel becomes possible. In addition, the indium gallium zinc oxide display has a higher energy efficiency level and higher efficiency due to the reduced number of transistors and the improved light transmittance per pixel. In addition, the indium gallium zinc oxide can be produced by using the existing amorphous silicon production line, and only needs to be slightly modified, so that the cost is more competitive in the field of active matrix organic electroluminescent diodes (AMOLED) than that of low-temperature polycrystalline silicon.
However, the indium gallium zinc oxide still has a certain disadvantage compared to low temperature polysilicon, and especially, the mobility of the current indium gallium zinc oxide is lower than that of Low Temperature Polysilicon (LTPS), so a larger transistor size is often required to achieve the required current, which is a very unfavorable aspect for narrow bezel panel design.
As shown in fig. 1, the basic pixel driving circuit of the conventional active matrix organic electroluminescent diode 90 at least includes a switching transistor (Switch TFT, STFT)91, a driving transistor (Driver TFT, DTFT)92, a storage capacitor (Cst)93 and an Organic Light Emitting Diode (OLED) 94. The threshold voltage (Vth) of the driving transistor 92 is subject to drift due to the limitations of the uniformity of the process and the attenuation of the driving transistor with the use time, so that the driving current of the organic light emitting diode 94 is subject to change, the image displayed by the organic light emitting diode 94 is not uniform, and the image quality is affected. Therefore, the influence of leakage current on the pixel circuit is usually suppressed by a circuit design having a compensation function, such as a dual gate structure, but such a design affects the flexibility of the active matrix organic electroluminescent diode display.
Disclosure of Invention
The invention provides an array substrate and a manufacturing method thereof, which are used for solving the technical problem that the flexibility is reduced due to the fact that the influence of leakage current on a pixel circuit is inhibited by using circuit designs with compensation functions such as a double-gate structure and the like of the conventional active matrix organic light-emitting diode display.
The invention provides an array substrate, which comprises a substrate, a first metal layer, a grid insulating layer, an active layer, a second metal layer, a grid layer, a passivation layer and an electrode wiring layer, wherein the first metal layer is arranged on the substrate; specifically, the first metal layer comprises a plurality of first electrodes arranged at intervals and arranged on the substrate base plate; the grid electrode insulating layer is arranged on the substrate and completely covers the first metal layer; the active layer comprises a plurality of active units and is arranged on the gate insulating layer; each active unit is arranged corresponding to each first electrode and is electrically connected with the first electrode; the second metal layer comprises a plurality of second electrodes arranged at intervals and is arranged on the active layer; each second electrode is arranged on each active unit and is electrically connected with the active unit; the grid electrode layer is arranged in a grid electrode insulating layer between two adjacent active units along the direction vertical to the substrate; the passivation layer is arranged on the grid electrode insulating layer and covers the second metal layer and the grid electrode layer; the electrode routing layer is arranged on the passivation layer and is electrically connected with the two second electrodes positioned on two sides of the grid layer.
Further, the array substrate further comprises an ohmic contact layer, the ohmic contact layer comprises a plurality of control units arranged at intervals, one end of each control unit is connected with the corresponding first electrode, and the other end of each control unit is connected with the corresponding active unit.
Furthermore, the ohmic contact layer is arranged on the substrate base plate, the first metal layer is arranged on the ohmic contact layer, the first electrode covers one end of the control unit, and the active unit and the first electrode are arranged at intervals and connected with the upper surface of the control unit.
Furthermore, a plurality of transistor units are arranged on the array substrate, and each transistor unit comprises two control units, two first electrodes, two active units, one gate layer and two second electrodes.
Further, one of the two control units is a conductor, and the other control unit is a semiconductor, and is used for forming a channel switch and a capacitor in each transistor unit; or wherein both of said control units are conductors for forming two channel switches in each of said transistor units.
Further, the grid layer is cuboid or cylindrical; the height of the gate layer is the same as the height of the active cell.
Furthermore, the second electrode is arranged corresponding to the first electrode, and the active unit is arranged between the second electrode and the first electrode; the array substrate is provided with a plurality of transistor units, and each transistor unit comprises two first electrodes, two active units, a grid layer and two second electrodes.
Furthermore, a plurality of protrusions are arranged on connection surfaces of the first electrode, the second electrode and the active unit, and are used for increasing contact areas of the first electrode, the second electrode and the active unit.
The invention also provides a manufacturing method of the array substrate, which comprises the following steps:
manufacturing a first metal layer on a substrate, and patterning the first metal layer to form a plurality of first electrodes arranged at intervals;
manufacturing a grid electrode insulating layer on the substrate base plate, wherein the grid electrode insulating layer completely covers the first metal layer;
manufacturing an active layer on the gate insulating layer, wherein the active layer comprises a plurality of active units, and each active unit is arranged corresponding to each first electrode and is electrically connected with each first electrode;
manufacturing a second metal layer on the active layer, wherein the second metal layer comprises a plurality of second electrodes which are arranged at intervals; each second electrode is arranged on each active unit and is electrically connected with the active unit;
manufacturing a gate layer in a gate insulating layer between two adjacent active units, wherein the gate layer is arranged along a direction vertical to the substrate;
manufacturing a passivation layer on the grid electrode insulating layer, wherein the passivation layer covers the second metal layer and the grid electrode layer; and
and manufacturing an electrode wiring layer on the passivation layer, wherein the electrode wiring layer is electrically connected with the two second electrodes positioned on two sides of the grid layer.
The method further comprises the steps of manufacturing an ohmic contact layer on the substrate base plate, wherein the ohmic contact layer comprises a plurality of control units arranged at intervals, one end of each control unit is connected with the first electrode, and the other end of each control unit is connected with the active unit; the height of the gate layer is the same as the height of the active cell.
The array substrate and the manufacturing method thereof have the advantages that the array substrate is provided with the plurality of transistor units, each transistor unit comprises the two control units, the two first electrodes, the two active units, the gate layer and the two second electrodes, or each transistor unit comprises the two first electrodes, the two active units, the gate layer and the two second electrodes, two channel switches or a channel switch and a capacitor can be formed in each transistor unit, the gate layers are longitudinally arranged, bending flexibility is improved, and the condition that threshold voltages of the transistor units drift is reduced.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a schematic structural diagram of a basic pixel driving circuit of a conventional active matrix organic electroluminescent diode.
Fig. 2 is a schematic structural diagram of an array substrate in embodiment 1 of the present invention.
Fig. 3 is a flowchart of a method for manufacturing an array substrate according to embodiment 1 of the present invention.
Fig. 4 is a schematic structural diagram of the first metal layer manufactured in embodiment 1 of the present invention.
Fig. 5 is a schematic structural diagram of the gate insulating layer manufactured in embodiment 1 of the present invention.
Fig. 6 is a schematic structural diagram of the completed gate layer in embodiment 1 of the present invention.
Fig. 7 is a schematic structural diagram of the passivation layer manufactured in embodiment 1 of the present invention.
Fig. 8 is a schematic structural diagram of an array substrate in embodiment 2 of the invention.
Fig. 9 is a flowchart of a method for manufacturing an array substrate according to embodiment 2 of the present invention.
Fig. 10 is a schematic structural diagram of the completed first metal layer in embodiment 2 of the present invention.
Fig. 11 is a schematic structural diagram of the gate insulating layer manufactured in embodiment 2 of the present invention.
Fig. 12 is a schematic structural diagram of the completed gate layer in embodiment 2 of the present invention.
Fig. 13 is a schematic structural diagram of the passivation layer manufactured in embodiment 2 of the present invention.
The designations in the drawings are as follows:
1. a substrate base plate, 2, an ohmic contact layer, 3, a first metal layer, 4, a grid insulation layer,
5. an active layer, 6, a second metal layer, 7, a gate layer, 8, a passivation layer,
9. an electrode wiring layer 10, a transistor unit 21, a control unit 31, a first electrode,
41. via hole 51, active unit 61, second electrode 100, array substrate.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Example 1
Referring to fig. 2, an array substrate 100 according to embodiment 1 of the present invention includes a substrate 1, an ohmic contact layer 2, a first metal layer 3, a gate insulating layer 4, an active layer 5, a second metal layer 6, a gate layer 7, a passivation layer 8, and an electrode routing layer 9.
Specifically, the first metal layer 3 includes a plurality of first electrodes 31 disposed at intervals, and is disposed on the substrate 1; the gate insulating layer 4 is arranged on the substrate base plate 1 and completely covers the first metal layer 3; the active layer 5 comprises a plurality of active cells 51 arranged on the gate insulating layer 4; each active unit 51 is disposed corresponding to and electrically connected to each first electrode 31; the second metal layer 6 comprises a plurality of second electrodes 61 arranged at intervals and arranged on the active layer 5; each second electrode 61 is disposed on each active unit 51 and electrically connected thereto; the gate electrode layer 7 is arranged in the gate insulating layer 4 between two adjacent active units 51 along the direction vertical to the substrate base plate 1; the gate layer 7 has a rectangular parallelepiped shape or a cylindrical shape, and the height of the gate layer 7 is the same as that of the active unit 51; the passivation layer 8 is arranged on the gate insulating layer 4 and covers the second metal layer 6 and the gate layer 7; the electrode routing layer 9 is disposed on the passivation layer 8 and electrically connected to the two second electrodes 61 on two sides of the gate layer 7.
In this embodiment, the ohmic contact layer 2 is disposed on the substrate base plate 1, the first metal layer 3 is disposed on the ohmic contact layer 2, the ohmic contact layer 2 includes a plurality of control units 21 disposed at intervals, one end of each control unit 21 is connected to the first electrode 31, and the other end of each control unit 21 is connected to the active unit 51.
In this embodiment, the first electrode 31 covers one end of the control unit 21, and the active unit 51 is disposed at an interval from the first electrode 31 and connected to the upper surface of the control unit 21.
In this embodiment, a plurality of transistor units 10 are disposed on the array substrate 100, and each transistor unit 10 includes two control units 21, two first electrodes 31, two active units 51, one gate layer 7, and two second electrodes 61.
In the embodiment, one of the two control units 21 is a conductor, and the other is a semiconductor, so as to form a channel switch and a capacitor in each transistor unit 10; or both of the control units 21 are conductors for forming two channel switches in each of the transistor cells 10.
In this embodiment, the first metal layer 3 and the second metal layer 6 may be fabricated into a plurality of first electrodes 31 and second electrodes 61, the first electrodes 31 and the second electrodes 61 are respectively used as Source electrodes or Drain electrodes (Source/Drain), and the active layer 5 is respectively overlapped with the surfaces of the first electrodes 31 and the second electrodes 61 to connect two or more transistor units 10 in parallel, so as to form a dual-channel or multi-channel transistor unit 10 structure. The transistor unit 10 with double channels or multiple channels is designed, one or more active layers 5 can be set as capacitors, and leakage current is reduced; the parallel transistor unit 10 may also be formed with double channels or multiple channels, so as to increase the current between the source and the drain of the transistor unit 10, reduce the size of the transistor unit 10, and after a certain channel fails, the other channels can still function as switches, thereby improving the reliability of the device. Moreover, through the structural design of the vertical lapping transistor unit 10, a plurality of channels are manufactured, a light shielding layer does not need to be manufactured, and a Mask plate (Mask) procedure does not need to be additionally added in parallel connection, so that the Mask plate procedure is reduced, the manufacturing procedure is simplified, and the cost is reduced.
The beneficial effect of this embodiment lies in: on one hand, the current between the source and the drain of the transistor unit 10 is increased, the size of the transistor unit 10 is reduced, and the design of a narrow-frame panel is facilitated; on the other hand, the influence of the leakage current on the pixel circuit is suppressed by a circuit design having a compensation function such as a double-channel or multi-channel structure, and the image quality and flexibility of the display manufactured by the array substrate 100 are improved.
As shown in fig. 3, in the present embodiment, a method for manufacturing an array substrate 100 is further provided, which includes the following steps S11-S18.
S11, manufacturing an ohmic contact layer 2 on a substrate 1, wherein the ohmic contact layer 2 comprises a plurality of spaced control units 21. The ohmic contact layer 2 is made of Indium Gallium Zinc Oxide (IGZO) and can reduce contact resistance after conductor treatment. The control unit 21 may be indium gallium zinc oxide subjected to conductor treatment, so as to realize a channel function; the control unit 21 may also be indium gallium zinc oxide without conducting treatment, so as to achieve the function of breaking circuit. The ohmic contact layer 2 has a function that one end is connected with a source electrode or a drain electrode, and the other end is connected with the active layer 5, so that the active layer 5 corresponding to the control unit 21 formed by the indium gallium zinc oxide which is subjected to the conductor treatment is used as a channel switch, and the active layer 5 corresponding to the control unit 21 formed by the indium gallium zinc oxide which is not subjected to the conductor treatment and the grid electrode are jointly used as a capacitor. As shown in fig. 4, metal oxides such as indium gallium zinc oxide are deposited by physical vapor sputtering, the indium gallium zinc oxide is patterned by a photolithography process, the control unit 21 is made by forming a pattern of the indium gallium zinc oxide by wet etching, and an oxalic acid-based chemical solution can be used as an etchant; after the photoresist is stripped, the control unit 21 conducts indium gallium zinc oxide by plasma (plasma) processing.
S12, forming a first metal layer 3 on the substrate 1, and patterning the first metal layer 3 to form a plurality of first electrodes 31 disposed at intervals. Wherein one end of the control unit 21 is connected to the first electrode 31, and the other end of the control unit 21 is connected to the active unit 51; the height of the gate layer 7 is the same as that of the active cell 51. As shown in fig. 4, a metal layer is deposited on the ohmic contact layer 2 by a physical vapor deposition method, the material may be Cu, MoTi or an alloy material of MoTi/Cu, a pattern of source/drain electrodes is formed by a photolithography process, and a hydrogen peroxide solution is used as an etchant for the metal material.
And S13, manufacturing a gate insulating layer 4 on the substrate base plate 1, wherein the gate insulating layer 4 completely covers the first metal layer 3. As shown in fig. 5, the gate insulating layer 4 is deposited by a chemical vapor deposition method on the basis of fig. 4, the gate insulating layer 4 is patterned by a photolithography process, and a via hole 41 for accommodating the active layer 5 and the gate electrode layer 7 is formed by etching using an oxidizing gas such as fluorine (F) -based gas as a dry etchant.
S14, fabricating an active layer 5 on the gate insulating layer 4, where the active layer 5 includes a plurality of active cells 51, and each active cell 51 is disposed corresponding to and electrically connected to each of the first electrodes 31. As shown in fig. 6, a metal oxide such as indium gallium zinc oxide is deposited by a physical vapor deposition method on the basis of fig. 5, and the active layer 5 is formed after the indium gallium zinc oxide is subjected to a conductor forming process by a plasma (plasma) process.
S15, forming a second metal layer 6 on the active layer 5, where the second metal layer 6 includes a plurality of second electrodes 61 arranged at intervals; each second electrode 61 is disposed on and electrically connected to each active unit 51. As shown in fig. 6, a metal layer is physically vapor-deposited on the active layer 5, the metal layer may be made of Cu, MoTi, or an alloy material of MoTi/Cu, the source/drain electrodes and the active layer 5 are patterned by a photolithography process, the hydrogen peroxide solution is used as an etchant for the metal material, and the oxalic acid solution is used as an etchant for the active layer 5.
S16, forming a gate electrode layer 7 in the gate insulating layer 4 between two adjacent active units 51, wherein the gate electrode layer 7 is arranged along a direction perpendicular to the substrate 1; the gate layer 7 has a rectangular parallelepiped shape or a cylindrical shape, and the height of the gate layer 7 is the same as the height of the active cell 51. As shown in fig. 5, the depth of the via hole 41 for forming the active layer 5 and the gate layer 7 is the same, so that the heights of the two are ensured to be the same. As shown in fig. 6, the gate layer 7 and the second metal layer 6 are formed simultaneously.
S17, fabricating a passivation layer 8 on the gate insulating layer 4, wherein the passivation layer 8 covers the second metal layer 6 and the gate layer 7. As shown in fig. 7, a passivation layer 8(PV) is deposited by a chemical vapor deposition method on the basis of fig. 6, and the material may be an inorganic non-metallic film material of SiNx, SiOx or an interlayer of SiNx and SiOx, and a pattern of the passivation layer 8 is formed by a photolithography process, and a trace via hole for accommodating the electrode trace layer 9 is formed by etching using an oxidizing gas such as fluorine (F) based gas as a dry etchant.
And S18, manufacturing an electrode wiring layer 9 on the passivation layer 8, wherein the electrode wiring layer 9 is electrically connected with the two second electrodes 61 positioned on the two sides of the gate layer 7. As shown in fig. 2, an electrode is deposited by physical vapor deposition on the basis of fig. 7, which may be Indium Tin Oxide (ITO), and a pattern of a pixel electrode is formed by photolithography, and an oxalic acid-based chemical solution is used as an etchant for the metal layer.
Example 2
As shown in fig. 8, most of the technical features of embodiment 1 are included in embodiment 2, except that the ohmic contact layer 2 of embodiment 1 is not provided in embodiment 2.
As shown in fig. 8, in the present embodiment, the second electrode 61 is disposed corresponding to the first electrode 31, and the active unit 51 is disposed between the second electrode 61 and the first electrode 31; a plurality of transistor units 10 are disposed on the array substrate, and each transistor unit 10 includes two first electrodes 31, two active units 51, one gate layer 7, and two second electrodes 61.
In this embodiment, a plurality of protrusions are disposed on connection surfaces of the first electrode 31, the second electrode 61, and the active cell 51, so as to increase contact areas between the first electrode 31, the second electrode 61, and the active cell 51.
In this embodiment, the first metal layer 3 and the second metal layer 6 may be fabricated into a plurality of first electrodes 31 and second electrodes 61, the first electrodes 31 and the second electrodes 61 are respectively used as Source electrodes and Drain electrodes (Source/Drain), and the active layer 5 is respectively overlapped with the surfaces of the first electrodes 31 and the second electrodes 61 to connect two or more transistor units 10 in parallel, so as to form a dual-channel or multi-channel transistor unit 10 structure. The transistor unit 10 with double channels or multiple channels is designed, one or more active layers 5 can be set as capacitors, and leakage current is reduced; the parallel transistor unit 10 may also be formed with double channels or multiple channels, so as to increase the current between the source and the drain of the transistor unit 10, reduce the size of the transistor unit 10, and after a certain channel fails, the other channels can still function as switches, thereby improving the reliability of the device. Moreover, through the structural design of the vertical lapping transistor unit 10, a plurality of channels are manufactured, a light shielding layer does not need to be manufactured, and a Mask plate (Mask) procedure does not need to be additionally added in parallel connection, so that the Mask plate procedure is reduced, the manufacturing procedure is simplified, and the cost is reduced.
The beneficial effect of this embodiment lies in: on one hand, the current between the source and the drain of the transistor unit 10 is increased, the size of the transistor unit 10 is reduced, and the design of a narrow-frame panel is facilitated; on the other hand, the influence of leakage current on a pixel circuit is suppressed by a circuit design with a compensation function such as a double-channel or multi-channel structure, and the image quality and the flexibility of a display manufactured by the array substrate are improved.
As shown in fig. 9, in the present embodiment, a method for manufacturing an array substrate is further provided, which includes the following steps S21-S27.
S21, forming a first metal layer 3 on a substrate 1, and patterning the first metal layer 3 to form a plurality of first electrodes 31 disposed at intervals. As shown in fig. 10, a metal layer, which may be a Cu, MoTi, or MoTi/Cu alloy material, is deposited on a substrate 1 by a physical vapor deposition method, a source/drain pattern is formed by a photolithography process, and a small protrusion is formed on the surface of the metal layer by a Half tone (Half tone) process, thereby increasing the surface contact between the active layer 5 and the first metal layer 3, and a hydrogen peroxide solution is used as an etchant for the metal material.
And S22, manufacturing a gate insulating layer 4 on the substrate base plate 1, wherein the gate insulating layer 4 completely covers the first metal layer 3. As shown in fig. 11, a gate insulating layer 4 is deposited by a chemical vapor deposition method on the basis of fig. 10, a pattern of the gate insulating layer 4 is formed by a photolithography process, a small protrusion is formed on the surface of the gate insulating layer 4 at a position where an opening of the active layer 5 is to be formed by a halftone (Half tone) process, thereby increasing the contact between the active layer 5 and the metal layer, and a via hole 41 for accommodating the active layer 5 and the gate layer 7 is formed by etching using an oxidizing gas such as fluorine (F) based gas as a dry etchant.
S23, fabricating an active layer 5 on the gate insulating layer 4, where the active layer 5 includes a plurality of active cells 51, and each active cell 51 is disposed corresponding to and electrically connected to each first electrode 31. As shown in fig. 12, a metal oxide such as indium gallium zinc oxide is deposited by a physical vapor deposition method on the basis of fig. 11 to form the active layer 5.
S24, forming a second metal layer 6 on the active layer 5, where the second metal layer 6 includes a plurality of second electrodes 61 arranged at intervals; each second electrode 61 is disposed on and electrically connected to each active unit 51. As shown in fig. 12, a metal layer is deposited by a physical vapor deposition method on the basis of fig. 11, the material of the metal layer may be Cu, MoTi, or an alloy material of MoTi/Cu, the source/drain electrodes and the gate electrode layer 7 are patterned by a photolithography process, the hydrogen peroxide solution is used as an etchant for the metal material, and the oxalic acid solution is used as an etchant for the active layer 5.
S25, forming a gate electrode layer 7 in the gate insulating layer 4 between two adjacent active units 51, wherein the gate electrode layer 7 is arranged along a direction perpendicular to the substrate 1; the gate layer 7 has a rectangular parallelepiped shape or a cylindrical shape, and the height of the gate layer 7 is the same as the height of the active cell 51. As shown in fig. 11, the depth of the via hole 41 for forming the active layer 5 and the gate layer 7 is the same, so that the heights of the two are ensured to be the same. As shown in fig. 12, the gate layer 7 and the second metal layer 6 are formed simultaneously.
S26, fabricating a passivation layer 8 on the gate insulating layer 4, wherein the passivation layer 8 covers the second metal layer 6 and the gate layer 7. As shown in fig. 13, a passivation layer 8(PV) is deposited by a chemical vapor deposition method on the basis of fig. 12, and the material may be an inorganic non-metallic film material of SiNx, SiOx or an interlayer of SiNx and SiOx, and a pattern of the passivation layer 8 is formed by a photolithography process, and a trace via hole for accommodating the electrode trace layer 9 is formed by etching using an oxidizing gas such as fluorine (F) based gas as a dry etchant.
And S27, manufacturing an electrode wiring layer 9 on the passivation layer 8, wherein the electrode wiring layer 9 is electrically connected with the two second electrodes 61 positioned on the two sides of the gate layer 7. As shown in fig. 8, an electrode is deposited by physical vapor deposition on the basis of fig. 13, which may be Indium Tin Oxide (ITO), and a pattern of a pixel electrode is formed by a photolithography process, and an oxalic acid-based chemical solution is used as an etchant for the metal layer.
The array substrate and the manufacturing method thereof have the advantages that the array substrate is provided with the plurality of transistor units, each transistor unit comprises the two control units, the two first electrodes, the two active units, the gate layer and the two second electrodes, or each transistor unit comprises the two first electrodes, the two active units, the gate layer and the two second electrodes, two channel switches or a channel switch and a capacitor can be formed in each transistor unit, the gate layers are longitudinally arranged, bending flexibility is improved, and the condition that threshold voltages of the transistor units drift is reduced.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The array substrate and the manufacturing method thereof provided by the embodiments of the present invention are described in detail above, and the principle and the implementation manner of the present invention are explained in the present document by applying specific examples, and the description of the embodiments above is only used to help understanding the technical scheme and the core idea of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (9)
1. An array substrate, comprising:
a substrate base plate;
the first metal layer comprises a plurality of first electrodes arranged at intervals and is arranged on the substrate base plate;
the grid insulation layer is arranged on the substrate base plate and completely covers the first metal layer;
an active layer including a plurality of active cells disposed on the gate insulating layer; each active unit is arranged corresponding to each first electrode and is electrically connected with the first electrode;
the second metal layer comprises a plurality of second electrodes arranged at intervals and is arranged on the active layer; each second electrode is arranged on each active unit and is electrically connected with the active unit;
the grid layer is arranged in the grid insulating layer between every two adjacent active units along the direction vertical to the substrate;
the passivation layer is arranged on the grid electrode insulating layer and covers the second metal layer and the grid electrode layer; and
the electrode routing layer is arranged on the passivation layer and is electrically connected with the two second electrodes positioned on the two sides of the grid layer;
the array substrate is provided with a plurality of transistor units, and each transistor unit comprises two control units, two first electrodes, two active units, one gate layer and two second electrodes.
2. The array substrate of claim 1, further comprising:
and the ohmic contact layer comprises a plurality of control units arranged at intervals, one end of each control unit is connected with the first electrode, and the other end of each control unit is connected with the active unit.
3. The array substrate of claim 2, wherein the ohmic contact layer is disposed on the substrate, the first metal layer is disposed on the ohmic contact layer, the first electrode covers one end of the control unit, and the active unit is spaced apart from the first electrode and connected to an upper surface of the control unit.
4. The array substrate of claim 1, wherein one of the two control units is a conductor and the other is a semiconductor for forming a channel switch and a capacitor in each of the transistor units; or
Wherein both of said control units are conductors for forming two channel switches in each of said transistor cells.
5. The array substrate of claim 1, wherein the gate layer is rectangular parallelepiped or cylindrical; the height of the gate layer is the same as the height of the active cell.
6. The array substrate of claim 1, wherein the second electrode is disposed opposite to the first electrode, and the active unit is disposed between the second electrode and the first electrode; the array substrate is provided with a plurality of transistor units, and each transistor unit comprises two first electrodes, two active units, a grid layer and two second electrodes.
7. The array substrate of claim 1, wherein a plurality of protrusions are formed on connection surfaces of the first electrode, the second electrode and the active cell to increase contact areas of the first electrode, the second electrode and the active cell.
8. A manufacturing method of an array substrate is characterized by comprising the following steps:
manufacturing a first metal layer on a substrate, and patterning the first metal layer to form a plurality of first electrodes arranged at intervals;
manufacturing a grid electrode insulating layer on the substrate base plate, wherein the grid electrode insulating layer completely covers the first metal layer;
manufacturing an active layer on the gate insulating layer, wherein the active layer comprises a plurality of active units, and each active unit is arranged corresponding to each first electrode and is electrically connected with each first electrode;
manufacturing a second metal layer on the active layer, wherein the second metal layer comprises a plurality of second electrodes which are arranged at intervals; each second electrode is arranged on each active unit and is electrically connected with the active unit;
manufacturing a gate layer in a gate insulating layer between two adjacent active units, wherein the gate layer is arranged along a direction vertical to the substrate;
manufacturing a passivation layer on the grid electrode insulating layer, wherein the passivation layer covers the second metal layer and the grid electrode layer; and
manufacturing an electrode wiring layer on the passivation layer, wherein the electrode wiring layer is electrically connected with two second electrodes positioned on two sides of the gate layer;
the array substrate is provided with a plurality of transistor units, and each transistor unit comprises two control units, two first electrodes, two active units, one gate layer and two second electrodes.
9. The method for fabricating an array substrate according to claim 8, further comprising, before fabricating the first metal layer on the substrate base plate:
manufacturing an ohmic contact layer on the substrate, wherein the ohmic contact layer comprises a plurality of control units arranged at intervals, one end of each control unit is connected with the first electrode, and the other end of each control unit is connected with the active unit; the height of the gate layer is the same as the height of the active cell.
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| CN107342328A (en) * | 2017-07-19 | 2017-11-10 | 京东方科技集团股份有限公司 | A kind of heterotype film transistor and preparation method thereof, array base palte |
| KR102551998B1 (en) * | 2018-11-20 | 2023-07-06 | 엘지디스플레이 주식회사 | Vertical structure transistor and electronic device |
| US11222904B2 (en) * | 2019-01-07 | 2022-01-11 | Chongqing Boe Optoelectronics Technology Co., Ltd. | Thin film transistor and manufacturing method thereof, array substrate and manufacturing method thereof, and display device |
| KR20200115753A (en) * | 2019-03-25 | 2020-10-08 | 삼성디스플레이 주식회사 | Thin film transistor substrate, display apparatus and method of manufacturing the same |
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| CN101013725A (en) * | 2006-07-10 | 2007-08-08 | 友达光电股份有限公司 | Bigrid transistor and pixel structure using the same |
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