CN101013725A - Bigrid transistor and pixel structure using the same - Google Patents
Bigrid transistor and pixel structure using the same Download PDFInfo
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- CN101013725A CN101013725A CN 200610168651 CN200610168651A CN101013725A CN 101013725 A CN101013725 A CN 101013725A CN 200610168651 CN200610168651 CN 200610168651 CN 200610168651 A CN200610168651 A CN 200610168651A CN 101013725 A CN101013725 A CN 101013725A
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Abstract
The invention provides one pixel structure, which comprises double grating electrode transistor tube, capacitor and signal line to connect double grating electrode transistor tube, wherein, signal wire comprises scan line and data line; double grating transistor comprises first grating electrode on baseboard; first dielectric layer covers one first grating layer and baseboard; semi-conductive layer is between first dielectric layer and first grating layer; the first and second electrodes are formed on semi-conductive layer with isolation for two electrodes; the second dielectric layer covers on first and second electrodes; the second grating electrode is on second dielectric layer.
Description
Technical field
The present invention is about the structural design of a kind of transistor (transistor), particularly about a kind of transistor with double-grid structure (dual-gate structures).
Background technology
Along with the progress that shows science and technology, compare with traditional CRT monitor, Thin Film Transistor-LCD (thin film transistor liquid crystal display, TFT-LCD) owing to have the little and advantage that do not take up space of light, thin, low radiation and volume, become at present main force's product of monitor market, be the fast development of reply liquid crystal display product, the inter-industry competition of liquid crystal panel manufacturer increases day by day.How to promote usefulness, reliability and the reduction cost of manufacture of thin-film transistor, be all important developing goal.
Amorphous silicon film transistor (amorphous silicon thin film transistor) has the function of Control current conducting, therefore often be used as LCD (liquid crystal display, LCD) or Organic Light Emitting Diode (organic light emitting diode, OLED) pixel of display (pixel) switch.
In order to promote the current lead-through ability of thin-film transistor, a kind of thin-film transistor with double-grid structure also is subjected to the attention of industry gradually in recent years.Please refer to Fig. 1, it shows known thin-film transistor profile with double-grid structure.As shown in Figure 1, this thin-film transistor is made on the substrate 10, and its structure has mainly comprised first grid 11, second grid 16, semiconductor layer 13, drain electrode 14 and source electrode 15.
In addition, this double-gate film transistor has more first dielectric layer 12 and second dielectric layer 17.First dielectric layer 12 is formed on the substrate 10, and covers first grid 11.17 of second dielectric layers are to be covered on drain electrode 14 and the source electrode 15, and are positioned under the second grid 16.
This double-gate film transistor arrangement has better conducting current capacity than the thin-film transistor of the single grid of tradition, and can effectively lower the electric field crowding effect, for the problem of element light leakage current sizable improvement is arranged.
Yet, in known double-gate film transistor arrangement, because the edge of second grid 16 overlaps with the edge part of drain electrode 14 and source electrode 15, therefore in the driving process of LCD, second grid 16 causes parasitic capacitance Cgs to increase with the part that source electrode 14 overlaps easily.What specify is that the increase of parasitic capacitance Cgs can cause feed voltage (feed through voltage) to strengthen, and then influences the operating voltage of pixel electrode, the related correctness that has influence on the GTG demonstration.
In sum, the inventor is very big to the quality influence of display thoughts on existing its parasitic capacitance of double-gate film transistor arrangement Cgs, so attempt proposing a kind of structural design of double gate transistor,, and then overcome above-mentioned problem of deriving so that effectively reduce the generation of parasitic capacitance.
Summary of the invention
The object of the present invention is to provide a kind of transistor with double-grid structure, the upright projection position of its second grid does not overlap with second electrode, reduce issuable parasitic capacitance between the second grid and second electrode by this, and the minimizing feed voltage is to promote the usefulness and the reliability of double gate transistor.
Another object of the present invention is to provide a kind of transistor with double-grid structure, wherein one of them person's of second grid and first grid upright projection overlap with second electrode (or second electrode electrically connected first doped region) overlap.So, in the driving process of LCD, the part that (or second electrode electrically connected first doped region) do not overlap because one of them person of second grid and first grid and second electrode reduces much so the parasitic capacitance that double gate transistor produced will be relative.
Another object of the present invention is to provide a kind of dot structure with above-mentioned double gate transistor.By dot structure design of the present invention, can make the pixel electrode in the liquid crystal panel have more stable operating voltage, and it is correct more and stable that GTG is shown.
The disclosed double gate transistor of the present invention comprises first grid, is formed on the substrate.First dielectric layer is covered on first grid and the substrate.Semiconductor layer is positioned at first dielectric layer and first grid top.First electrode and second electrode lay respectively on the semiconductor layer, and have between second electrode and first electrode at interval, in order to two electrodes disconnected from each other.Second dielectric layer is covered in first electrode, second electrode and semiconductor layer partly.Second grid is positioned on second dielectric layer, and wherein one of them person of second grid and first grid does not overlap with second electrode.
The disclosed double gate transistor of the present invention comprises first grid, is positioned on the substrate.First dielectric layer is covered on first grid and the substrate.Semiconductor layer be positioned at first dielectric layer and first grid top, and two ends of semiconductor layer has first doped region respectively.Second dielectric layer is covered on semiconductor layer and the substrate.Second grid is positioned on second dielectric layer.The 3rd dielectric layer is covered on second grid and the substrate.
First electrode and second electrode lay respectively on the 3rd dielectric layer and are electrically connected at first doped region of two ends of semiconductor layer respectively.Wherein, have between second electrode and first electrode at interval, in order to disconnected from each other.Wherein, one of them person of first grid and second grid is not with one of them overlapping of this first doped region.
The disclosed dot structure of the present invention comprises the double gate transistor of above-mentioned exposure, the holding wire that at least one electric capacity and at least one is electrically connected at double gate transistor.Wherein, holding wire comprises at least one scan line (gate line) and at least one data wire (data line).
In order further to understand feature of the present invention and content, see also following about detailed description of the present invention and accompanying drawing.
Description of drawings
Fig. 1 is the generalized section of known middle double gate transistor;
Fig. 2 is the generalized section of double gate transistor of the present invention;
Fig. 3 is the generalized section of the embodiment of double gate transistor of the present invention;
Fig. 4 is the generalized section of the embodiment of double gate transistor of the present invention;
Fig. 5 A to Fig. 5 H is the various aspects of semiconductor layer in the double gate transistor;
Fig. 6 is the generalized section of the embodiment of double gate transistor of the present invention;
Fig. 7 is the generalized section of the embodiment of double gate transistor of the present invention;
Fig. 8 A to Fig. 8 D is the structure vertical view of double gate transistor;
Fig. 9 A is the circuit diagram with first kind of dot structure of double gate transistor of the present invention;
Fig. 9 B is the circuit diagram with second kind of dot structure of double gate transistor of the present invention; And
Figure 10 be single gridistor, known double gate transistor and double gate transistor of the present invention in applying the process of bias voltage, the test curve that the parasitic capacitance value that is produced is described to form.
[main element symbol description]
10,200,300,400,600,700: substrate
900: double gate transistor
11,210,310,410,610,710,910: first grid
12,220,320,420,620,720: the first dielectric layers
13,230,330,430,630,730,830: semiconductor layer
14,240,340,440,640,740,840,940: the first electrodes
15,250,350,450,650,750,850,950: the second electrodes
255,355,455,655,755: at interval
16,260,360,460,660,760,860,960: second grid
17,270,370,470,670,770: the second dielectric layers
132,232,332,432,5312: doping semiconductor layer
390: isolate block
131,231,331,431,5311: channel layer
5311a: the first shallow doped layer
5311b: the second shallow doped layer
5321,5331,5341,5351,5361,5371,5381,631,731: the first doped regions
5323,5333,5343,5353,5363,5373,5383,633,734: non-doped region
5342,5352,5362,5372,5382,732: the second doped regions
733: the three doped regions
675,775: the three dielectric layers
680,780: the four dielectric layers
92: electric capacity
94: holding wire
94a: scan line
94b: data wire
96: lead
Embodiment
Please refer to Fig. 2, it has the transistor arrangement profile of double-grid structure for the present invention.This double gate transistor is made on the substrate 200, and its primary structure has comprised first grid 210, first dielectric layer 220, semiconductor layer 230, first electrode 240, second electrode 250, second dielectric layer 270 and second grid 260.
As shown in Figure 2, first grid 210 is formed on the substrate 200.First dielectric layer 220 is covered on first grid 210 and the substrate 200.Semiconductor layer 230 is formed on first dielectric layer 220.First electrode 240 and second electrode 250 lay respectively on the semiconductor layer 230, and have an interval 255 between second electrode 250 and this first electrode 240, make two electrodes separated from one another, and can not contact with each other, and expose semiconductor layer 230 partly.
In addition, the upright projection at above-mentioned interval 255 falls within on the first grid 210, and in other words the upright projection of first electrode 240 and second electrode 250 overlaps with the two ends of first grid 210 respectively.Second dielectric layer 270 is covered on first electrode 240, second electrode 250 and the semiconductor layer 230 partly.In the present embodiment, semiconductor layer 230 comprises channel layer 231 and doping semiconductor layer 232.So first electrode 240 and second electrode 250 have doping semiconductor layer 232 respectively with the face that connects of semiconductor layer 230.
Wanting ben be, if second grid 260 is made upright projection towards substrate 200, the sidewall of second grid 260 close second electrodes 250 can fall within after upright projection in the scope between 1/3 to second electrode, 250 sidewalls of spacer first electrode 240.As for second grid 260 another sidewall, then can fall within on first electrode 240 after the upright projection away from second electrode 250.
In other words, from the relevant position of second grid 260 with interval 255, second grid 260 overlaps with interval partly 255, and this interval that partly overlaps accounts for more than 1/3 of whole interval 255.
In an embodiment of the present invention, the material of each layer structure can comprise as follows.The material of substrate 200 comprises transparency carrier (as: glass substrate, quartz base plate or materials similar), flexible base plate (as: propionyl base polymer, esters polymer, rubber, epoxide polymer or materials similar) or light tight substrate (as: pottery, wafer or materials similar).Material as for first grid 210 and second grid 260 comprises tin indium oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminium (Al), chromium (Cr), titanium (Ti), tungsten (W), tantalum (Ta), copper (Cu), gold (Au), silver (Ag), molybdenum (Mo), neodymium (Nd) or above-mentioned combination.
The material of semiconductor layer 230 comprises amorphous silicon, polysilicon, monocrystalline silicon, microcrystal silicon or above-mentioned combination.The material of first electrode 240 and second electrode 250 comprises tin indium oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminium (Al), chromium (Cr), titanium (Ti), tungsten (W), tantalum (Ta), copper (Cu), gold (Au), silver (Ag), molybdenum (Mo), neodymium (Nd) or above-mentioned combination.The material of first dielectric layer 220 and second dielectric layer 270 comprises silicon nitride, silica, silicon oxynitride, carborundum, organo-silicon compound or above-mentioned combination.
Because first grid 210 electrically connects with second grid 260, when first grid 210 and second grid 260 are applied in voltage, semiconductor layer 230 can induce electric charge at two interfaces up and down near first dielectric layer 220 and second dielectric layer 270, form two current channels as upper and lower surface place, and the bias voltage of second grid can reduce transistorized critical voltage at semiconductor layer 230.So double gate transistor has higher current lead-through ability than traditional single gridistor.
Please refer to Fig. 3, it has transistorized another embodiment of double-grid structure for the present invention.This double gate transistor is made on the substrate 300, and its primary structure has comprised first grid 310, first dielectric layer 320, semiconductor layer 330, first electrode 340, second electrode 350, second dielectric layer 370 and second grid 360.In the present embodiment, semiconductor layer 330 comprises channel layer 331 and doping semiconductor layer 332.So first electrode 340 and second electrode 350 have doping semiconductor layer 332 respectively with the face that connects of semiconductor layer 330.
The material of above-mentioned each layer structure and position are identical with the shown embodiment of Fig. 2 haply.Variant place is, in the shown double gate transistor of Fig. 3, also comprises and isolates block 390.This isolates block 390 and is positioned on the semiconductor layer 330.As for 350 at first electrode 340 and second electrode respectively by isolate block 390 about two sides extend to cover and partly isolate block 390.It should be noted that the upper surface of isolating block 390,, constitute interval 355, and it does not expose isolation block 390 partly by the part of first electrode 340 and 350 coverings of second electrode.And isolate the acting in order to preventing when carrying out the lithographic procedures of first electrode 340 and second electrode 350 of block 390, the semiconductor layer 330 of below is damaged.In general, the material of isolation block comprises silicon nitride, silica, silicon oxynitride, carborundum, organo-silicon compound or above-mentioned combination.
Please refer to Fig. 4, it is for another embodiment of double gate transistor of the present invention.This double gate transistor is made on the substrate 400, and its primary structure has comprised first grid 410, first dielectric layer 420, semiconductor layer 430, first electrode 440, second electrode 450, second dielectric layer 470 and second grid 460.
As shown in Figure 4, first grid 410 is formed on the substrate 400.420 of first dielectric layers are covered on first grid 410 and the substrate 400.Semiconductor layer 430 is formed on first dielectric layer 420.First electrode 440 and second electrode 450 lay respectively on the semiconductor layer 430, and have interval 455 between second electrode 450 and this first electrode 440, make two electrodes separated from one another, and can not contact with each other, and expose semiconductor layer 430 partly.470 of second dielectric layers are covered on first electrode 440, second electrode 450 and the semiconductor layer 430 partly.Second grid 460 is positioned on second dielectric layer 470.In the present embodiment, semiconductor layer 430 comprises channel layer 431 and doping semiconductor layer 432.So first electrode 440 contacts with doping semiconductor layer 432 respectively with second electrode 450.
It should be noted that wherein first grid 410 does not overlap to some extent with second electrode 450.As shown in FIG., a side of first grid 410 close second electrodes 450, and any overlapping is not arranged with second electrode 450.As for the opposite side of first grid 410 away from second electrode 450, then first electrode 440 with part overlaps.
Wanting ben be, if first grid 410 is made upright projection, the sidewall of first grid 410 close second electrodes 450 can fall within after upright projection in the scope between 1/3 to second electrode, 450 sidewalls of spacer first electrode 440.As for first grid 410 another sidewall, then can fall within on first electrode 440 after the upright projection away from second electrode 450.
In other words, from the relevant position of first grid 410 with interval 455, first grid 410 overlaps with interval partly 455, and this interval that partly overlaps accounts for more than 1/3 of whole interval 455.
The disclosed double gate transistor of the present invention except above-described different structure designs, more can adopt different semiconductor layer structure aspects according to different topology requirements.Relevant semiconductor layer structure aspect is as described below.
Please refer to Fig. 5 A, shown semiconductor layer comprises channel layer 5311 and doping semiconductor layer 5312 among the figure.In a preferred embodiment, channel layer 5311 comprises the first shallow doped layer 5311a and the second shallow doped layer 5311b, wherein the second shallow doped layer 5311b is positioned on the first shallow diamicton 5311a, and the doping content of doping semiconductor layer 5312 is in fact greater than the first shallow doped layer 5311a and the second shallow doped layer 5311b, and the first shallow doped layer 5311a equates in fact with the doping content of the second shallow doped layer 5311b or unequal in fact (as: less than or greater than, the doping content of the preferred first shallow doped layer 5311a in fact less than the doping content of the second shallow doped layer 5311b).
As in part embodiment, semiconductor layer then can have first doped region, second doped region and non-doped region.For example, in Fig. 5 B, semiconductor layer has comprised non-doped region 5323 in the middle of being positioned at and first doped region 5321 that lays respectively at these non-doped region 5323 two ends.
In Fig. 5 C, first doped region 5331 is positioned at the two ends of semiconductor layer, and the block size of first doped region 533 1 at two ends can be not quite similar, but not 5333 of doped regions are between first doped region 5331 at semiconductor layer two ends, and above-mentioned each block is level to arrangement.
Please refer to Fig. 5 D, first doped region 5341 is positioned at the two ends of semiconductor layer, and 5343 of non-doped regions are between first doped region 5341 at semiconductor layer two ends.Second doped region 5342 is between first doped region 5341 and non-doped region 5343.That is to say that non-doped region 5343 is between first doped region 5341 and second doped region 5342.Wherein, the area of first doped region 5341 and second doped region 5342 can equate or unequal (as: less than or greater than), and above-mentioned each block is level to arrangement, and the doping content of second doped region 5342 and first doped region 5341 is equal in fact or unequal (as: less than or greater than, the doping content of the preferred second shallow doped layer 5342 in fact less than the doping content of the first shallow doped layer 5341).
Please refer to Fig. 5 E, first doped region 5351 is defined in the two ends of semiconductor layer, and 5353 of non-doped regions are between first doped region 5351 at semiconductor layer two ends.Have two second doped regions 5352 all between first doped region 5351 and non-doped region 5353.And non-doped region 5353 is between two second doped regions 5352.Wherein, the area of first doped region 5351 and second doped region 5352 can equate or unequal (as: less than or greater than), and each block is level to arrangement, and second doped region 5352 equates in fact with the doping content of first doped region 5351 or unequal (as less than or greater than).
Please refer to Fig. 5 F, second doped region 5362 is between first doped region 5361 and non-doped region 5363, and each block is vertically to arrangement, and the doping content of second doped region 5362 and first doped region 5361 is equal in fact or unequal (as less than or greater than).
Please refer to Fig. 5 G, non-doped region 5373 is between first doped region 5371 and second doped region 5372, and each block is vertically to arrangement, and the doping content of second doped region 5372 and first doped region 5371 is equal in fact or unequal (as less than or greater than).
Please refer to Fig. 5 H, non-doped region 5383 is between first doped region 5381 and second doped region 5382, and each block is level to arrangement, and the doping content of second doped region 5382 and first doped region 5381 is equal in fact or unequal (as less than or greater than).
Please refer to Fig. 6, it has the transistor arrangement profile of double-grid structure for the present invention.This double gate transistor is made on the substrate 600, and its primary structure has comprised first grid 610, first dielectric layer 620, semiconductor layer 630, second dielectric layer 670, second grid 660, the 3rd dielectric layer 675, first electrode 640 and second electrode 650.
As shown in Figure 6, first grid 610 is formed on the substrate 600.First dielectric layer 620 is covered on first grid 610 and the substrate 600.Semiconductor layer 630 is formed at the top of first dielectric layer, 620 upper surfaces and first grid 610.Wherein, the two ends of semiconductor layer 630 have first doped region 631 respectively, and have non-doped region 633 between two first doped regions 631.Second dielectric layer 670 is covered on semiconductor layer 630 and the substrate 600.Second grid 660 is positioned on second dielectric layer 670.The 3rd dielectric layer 675 is covered on second grid 660 and the substrate 600.
In addition, this double gate transistor also comprises one the 4th dielectric layer 680, is formed between second dielectric layer 670 and the 3rd dielectric layer 675, and is covered in second grid 660.
First electrode 640 and second electrode 650 lay respectively on the 3rd dielectric layer 675, and are electrically connected at first doped region 631 at semiconductor layer 630 two ends respectively.Wherein, have interval 655 between second electrode 650 and this first electrode 640, make two electrodes separated from one another, and can not contact with each other.Certainly, this 655 can equate in fact with the length of non-doped region or unequal at interval, look the demand that transistor arrangement designs.
One of them person of it should be noted that wherein first grid 610 and second grid 660 not with one of them overlapping of first doped region.
As shown in FIG., a side of first doped region 631 that second grid 660 is electrically connected near second electrodes 650 is overlapped in 655 top at interval, and first doped region 631 that is not electrically connected with second electrode 650 has any overlapping.The opposite side of first doped region 631 that is electrically connected away from second electrode 650 as for second grid 660 then overlaps with first doped region 631 that first electrode 640 is partly electrically connected.
Wanting ben is, if second grid 660 is made upright projection, the sidewall of first doped region 631 that second grid 660 is electrically connected near second electrodes 650 can fall within after upright projection at interval in the scope between first doped region, 631 sidewalls that 1/3 to second electrode 650 of 655 first doped regions 631 that electrically connected apart from first electrode 640 electrically connected.Another sidewall of first doped region 631 that is electrically connected away from second electrode 650 as for second grid 660 then can fall within after the upright projection on first doped region 631 that first electrode 640 electrically connected.
In other words, from second grid 660 and 655 relevant position at interval, second grid 660 with partly between every 655 overlappings, and this partly overlap between every accounting for more than 1/3 of whole interval 655.
As shown in FIG., a side of first doped region 631 that electrically connected near second electrodes 650 of first grid 610.The opposite side of first doped region 631 that is electrically connected away from second electrode 650 as for first grid 610 then overlaps with first doped region 631 that first electrode 640 is partly electrically connected.
Wanting ben is, if first grid 610 is made upright projection, the sidewall of first doped region 631 that first grid 610 is electrically connected near second electrodes 650 can fall within after upright projection in the scope between first doped region, 631 sidewalls that 1/3 to second electrode 650 of first doped region 631 that spacer first electrode 640 electrically connected electrically connected.Another sidewall of first doped region 631 that is electrically connected away from second electrode 650 as for, first grid 610 after upright projection, then can fall within on first doped region 631 that first electrode 640 electrically connected.
In other words, from the relevant position of first grid 610 with interval 655, first grid 610 overlaps with interval partly 655, and this interval that partly overlaps accounts for more than 1/3 of whole interval 655.
Please refer to Fig. 7, it has transistorized another embodiment of double-grid structure for the present invention.This double gate transistor is made on the substrate 700, and its primary structure has comprised first grid 710, first dielectric layer 720, semiconductor layer 730, second dielectric layer 770, second grid 760, the 4th dielectric layer 780, the 3rd dielectric layer 775, first electrode 740 and second electrode 750.
The material of above-mentioned each layer structure and position are identical with the shown embodiment of Fig. 6 haply.Variant place is, in the shown double gate transistor of Fig. 7, semiconductor layer 730 has more defined second doped region 732, the 3rd doped region 733 and non-doped region 734 except first doped region 731.Wherein, second doped region 732, the 3rd doped region 733 and non-doped region 734 are between first doped region 731 of semiconductor layer 730 2 ends.Non-doped region 734 is between second doped region 732 and the 3rd doped region 733.
In addition, among the embodiment of Fig. 6 representative, the kenel that the structure of its semiconductor layer 730 also can similar Fig. 5 D.Semiconductor layer 730 defines first doped region 5341, second doped region 5342 and non-doped region 5343.Wherein first doped region 5341 is defined in the two ends of semiconductor layer 730, and second doped region 5342 and non-doped region 5343, between first doped region 5341 of two ends.That is to say that non-doped region 5343 is at second doped region 5342 and semiconductor layer 730 wherein between first doped region 5341 of an end.Certainly, kenel that also can similar Fig. 5 C, Fig. 5 E.
Please continue with reference to Fig. 6 and Fig. 7, wherein one of them person's of first grid 660,760 and second grid 610,710 upright projection position does not also all overlap with second electrode 650,750.
Please refer to Fig. 8 A to Fig. 8 C, shown the structure vertical view (top view) of the disclosed double gate transistor of the present invention among the figure, comprise semiconductor layer 830, first electrode 840, second electrode 850 and second grid 860.Show that by this front view double gate transistor is a unsymmetric structure, and first electrode 840 has the both sides that two ends are positioned at second electrode 850.
Please earlier with reference to Fig. 8 A, have covering scope C among the figure, the covering scope that this is second grid 860 is generally apart from 1/3 place's to the second electrode 850 of first electrode 840 and trims the place.
And Fig. 8 A, Fig. 8 B and Fig. 8 C three figure represent three kinds of structure aspects of double gate transistor respectively, and main difference is the difference of 860 coverage area of second grid.Among Fig. 8 A, second grid 860 is in semiconductor layer 830, and the two-end-point of the second grid 860 and first electrode 840 trims.Among Fig. 8 B, the semiconductor layer more than 830 that the semiconductor layer 830 that second grid 860 two-end-points are contained is contained than first electrode, 840 two-end-points.Among Fig. 8 C, second grid 860 is contained all first electrode 840 and part semiconductor layers 830.
Please refer to Fig. 8 D, shown the another kind of structure vertical view of the disclosed double gate transistor of the present invention among the figure, comprise semiconductor layer 830, first electrode 840, second electrode 850 and second grid 860.Different with above-mentioned Fig. 8 A to Fig. 8 C is, in the shown structure aspect of Fig. 8 D, has the structural design of two second grids 860.
Because in the process of making second grid 860, the gold-tinted contraposition can't be very accurate, so use the structural design of two second grids 860 instead.Owing to adopt the structural design of two second grids 860, so when gold-tinted waves up and down and the situation of bit errors is arranged, can do compensation to electric current, and make the double gate transistor in the whole front panel have consistency, and the conducting electric current uniformity of each double gate transistor is better.
In addition, in the doped region of the above embodiments of the present invention, the doping semiconductor layer, doping that is mixed comprises N type (as: phosphorus, arsenic or materials similar), P type (as: boron or materials similar) or above-mentioned combination.And, the structure of the double gate transistor of the above embodiments of the present invention can be used for dissimilar displays, comprise LCD, electroluminescent display (electroluminescence display), Field Emission Display (field-emission display), carbon nanotube display (nano-carbon tubedisplay) or similar display, wherein, electroluminescent display includes type (as: micromolecule, macromolecule), inorganic type or above-mentioned mixing.
In sum, via the description of the embodiment of Fig. 2 and Fig. 3, in the disclosed double gate transistor of the present invention, the structure upright projection position of second grid overlaps with second electrode, and wherein second electrode of the foregoing description is the source electrode of double gate transistor.In the driving process of LCD, because the part that second grid and source electrode do not overlap, so reducing that the parasitic capacitance Cgs that double gate transistor produced will be relative is a lot.
In addition, during owing to first grid and the overlapping of second electrode, also have similar parasitic capacitance Cgs and produce.Therefore, can be with reference to the description of the embodiment of Fig. 4, Fig. 6 and Fig. 7, wherein, one of them person of first grid and second grid does not all overlap with second electrode (or second electrode electrically connected first doped region).So, in the driving process of LCD, the part that (or the doped region that is electrically connected with source electrode) do not overlap because one of them person of first grid and second grid and source electrode reduces much so the parasitic capacitance Cgs that double gate transistor produced will be relative.
So in fact in all embodiment of the present invention, one of them person of first grid and second grid does not overlap with second electrode (or second electrode electrically connected first doped region).
In the application of reality, display has comprised a plurality of dot structures, and double gate transistor of the present invention can be used as the switch (switch) of each dot structure.Please refer to Fig. 9 A, Fig. 9 A is the circuit diagram with first kind of dot structure of double gate transistor of the present invention.First kind of dot structure comprises that at least one double gate transistor 900 of the present invention, at least one electric capacity 92 and at least one are electrically connected at the holding wire 94 of double gate transistor 900.Wherein, double gate transistor 900 can be used the double gate transistor of various embodiment of the present invention.Thereby this kind double gate transistor 900 can reduce parasitic capacitance value, for example Cgs.
Holding wire 94 comprises at least one scan line (gate line) 94a and at least one data wire (dataline) 94b.And the first grid 910 of double gate transistor 900 is electrically connected at scan line 94a, and the second grid 960 of double gate transistor 900 is electrically connected at first grid 910.In addition, first electrode 940 of double gate transistor 900 is connected in data wire 94b, and second electrode 950 of double gate transistor 900 is connected to electric capacity 92.
Dot structure is when carrying out operation sequence, by scan line 94a input one scan signal, in order to conducting double gate transistor 900.At this moment, via scan line 94a, first grid 910 is applied in identical voltage with second grid 960, can make semiconductor layer induce electric charge, and forms current channel.By this, data wire 94b input voltage signal is sent to electric capacity 92 via the current channel and second electrode 950 of first electrode 940, semiconductor layer.
Please refer to Fig. 9 B, Fig. 9 B is the circuit diagram with second kind of dot structure of double gate transistor of the present invention.Second kind of dot structure comprises that at least one double gate transistor 900 of the present invention, at least one electric capacity 92, at least one are electrically connected at the holding wire 94 and the lead 96 of double gate transistor 900.Wherein, double gate transistor 900 can be used the double gate transistor of various embodiment of the present invention.Thereby this kind double gate transistor 900 can reduce parasitic capacitance, for example Cgs.
Holding wire 94 comprises at least one scan line (gate line) 94a and at least one data wire (dataline) 94b.And the first grid 910 of double gate transistor 900 is electrically connected at scan line 94a, and the second grid 960 of double gate transistor 900 is electrically connected at lead 96.In addition, first electrode 940 of double gate transistor 900 is connected in data wire 94b, and second electrode 950 of double gate transistor 900 is connected to electric capacity 92.
Dot structure is when carrying out operation sequence, by scan line 94a input scan signal, in order to conducting double gate transistor 900.At this moment, apply voltages to first grid 910, apply another voltage to second grid 960, can make semiconductor layer induce electric charge, and form current channel via lead 96 via scan line 94a.By this, data wire 94b input voltage signal is sent to electric capacity 92 via the current channel and second electrode 950 of first electrode 940, semiconductor layer.
It should be noted that first kind of dot structure of Fig. 9 A, only can import same voltage to first grid 910 and second grid simultaneously by scan line 94a.
Second kind of dot structure of Fig. 9 B can cooperate the in fact needs of operation, imports different voltage to first grid 910 and second grid 960 by scan line 94a with lead 96 respectively.
Please refer to Figure 10, three curves among the figure represent single gridistor, known double gate transistor and double gate transistor of the present invention respectively in applying the process of bias voltage, the test curve that the parasitic capacitance value that is produced is described to form.Relatively each curve can find out that the measured parasitic capacitance Cgs value of double gate transistor of the present invention reduces very many compared with the measured parasitic capacitance Cgs value of known double gate transistor significantly.
Therefore, the disclosed double gate transistor of the present invention has bigger conducting electric current and can reduce the situation that light leaks electricity compared with traditional single gridistor.Simultaneously, double gate transistor of the present invention has lower parasitic capacitance Cgs value compared with known double gate transistor, and reduces the feed voltage that is caused, and makes double gate transistor have more reliability, and the demonstration of liquid crystal screen is more correct and stable.
Though the present invention illustrates as above with preferred embodiment, so it is not in order to limit this creation spirit and creation entity, only to terminate in the foregoing description that.Therefore, the modification of being done in spirit that does not break away from this creation and scope all should comprise within the scope of the claims.
Claims (43)
1. double gate transistor comprises:
First grid is positioned on the substrate;
First dielectric layer is covered on this first grid and this substrate;
Semiconductor layer is positioned on this first dielectric layer and this first grid;
First electrode and second electrode lay respectively on this semiconductor layer, and have between this second electrode and this first electrode at interval, in order to disconnected from each other;
Second dielectric layer is covered in this first electrode, this second electrode and this semiconductor layer partly; And
Second grid is positioned on this second dielectric layer, and wherein one of them person of this second grid and this first grid does not overlap with this second electrode.
2. double gate transistor as claimed in claim 1, wherein this second grid is near a side of this second electrode.
3. double gate transistor as claimed in claim 2, wherein this second grid is away from the opposite side of this second electrode and partly this first electrode overlapping.
4. double gate transistor as claimed in claim 1, wherein this second grid is near a sidewall of this second electrode, apart from this first electrode, 1/3 place to and between this second electrode sidewall trims.
5. double gate transistor as claimed in claim 4, wherein this second grid is away from another sidewall of this second electrode, and its upright projection falls within this first electrode.
6. double gate transistor as claimed in claim 1, wherein this of this second grid and part overlaps at interval, and the interval of this part accounts for more than 1/3 of this interval.
7. double gate transistor as claimed in claim 1, wherein this first grid is near a side of this second electrode.
8. double gate transistor as claimed in claim 7, wherein this first grid is away from the opposite side of this second electrode and partly this first electrode overlapping.
9. double gate transistor as claimed in claim 1, wherein the material of this semiconductor layer comprises amorphous silicon, polysilicon, monocrystalline silicon, microcrystal silicon or above-mentioned combination.
10. double gate transistor as claimed in claim 1, wherein this first grid is near a sidewall of this second electrode, apart from this first electrode, 1/3 place to and between this second electrode sidewall trims.
11. as the double gate transistor of claim 10, wherein this first grid is away from another sidewall of this second electrode, its upright projection falls within this first electrode.
12. double gate transistor as claimed in claim 1, wherein this first grid overlaps with partly being somebody's turn to do the interval, and this part accounts for more than 1/3 of this interval at interval.
13. double gate transistor as claimed in claim 1, wherein also comprise the isolation block, be positioned on this semiconductor layer, this first electrode and this second electrode are covered on this isolation block of part by two sides extension about this isolation block respectively, and this isolation block is not then constituted this interval by the part of this first electrode and the covering of this second electrode.
14. double gate transistor as claimed in claim 1, wherein, this semiconductor layer comprises channel layer and doping semiconductor layer, is positioned on this channel layer.
15. as the double gate transistor of claim 14, wherein, this channel layer comprises the first shallow doped layer and the second shallow doped layer, is positioned on this first shallow diamicton.
16. double gate transistor as claimed in claim 1, wherein, this semiconductor layer comprises at least one first doped region, at least one second doped region and at least one non-doped region.
17. as the double gate transistor of claim 16, wherein, this first doped region is positioned at two ends of this semiconductor layer, and this non-doped region is between this first doped region of two ends of this semiconductor layer.
18. as the double gate transistor of claim 16, wherein, this second doped region is between this first doped region and this non-doped region.
19. as the double gate transistor of claim 16, wherein, this non-doping is between this first doped region and this second doped region.
20. a double gate transistor comprises:
First grid is positioned on the substrate;
First dielectric layer is covered on this first grid and this substrate;
Semiconductor layer is positioned on this first dielectric layer and this first grid, and two ends of this semiconductor layer have first doped region respectively;
Second dielectric layer is covered on this semiconductor layer and this substrate;
Second grid is positioned on this second dielectric layer;
The 3rd dielectric layer is covered on this second grid and this substrate; And
First electrode and second electrode, lay respectively on the 3rd dielectric layer and be electrically connected at this first doped regions of two ends of this semiconductor layer respectively, wherein, have between second electrode and this first electrode at interval, in order to disconnected from each other, and one of them person of this first grid and this second grid does not overlap with one of them person of this first doped region.
21. the double gate transistor as claim 20 more comprises: the 4th dielectric layer be formed between this second dielectric layer and the 3rd dielectric layer, and it covers this second grid.
22. as the double gate transistor of claim 20, wherein a side of this first doped region of being electrically connected near this second electrode of this second grid is overlapped in the top at this interval.
23. as the double gate transistor of claim 22, wherein the opposite side of this first doped region of being electrically connected away from this second electrode of this second grid overlaps with this first doped region that this first electrode is partly electrically connected.
24. double gate transistor as claim 20, a sidewall of this first doped region of being electrically connected near this second electrode of this second grid wherein, apart from this first doped region, 1/3 place that this first electrode is electrically connected to and between this first doped region sidewall of being electrically connected of this second electrode trims.
25. as the double gate transistor of claim 24, another sidewall of this first doped region of being electrically connected away from this second electrode of this second grid wherein, its upright projection falls within this first doped region that this first electrode is electrically connected.
26. as the double gate transistor of claim 20, wherein this second grid overlaps with partly being somebody's turn to do the interval, this part accounts for more than 1/3 of this interval at interval.
27. as the double gate transistor of claim 20, a side of this first doped region of being electrically connected near this second electrode of this first grid wherein.
28. as the double gate transistor of claim 27, the opposite side of this first doped region of being electrically connected away from this second electrode of this first grid wherein, this first doped region that is electrically connected with this first electrode partly overlaps.
29. as the double gate transistor of claim 20, wherein the material of this semiconductor layer comprises amorphous silicon, polysilicon, monocrystalline silicon, microcrystal silicon or above-mentioned combination.
30. double gate transistor as claim 20, a sidewall of this first doped region of being electrically connected near this second electrode of this first grid wherein, apart from this first doped region, 1/3 place that this first electrode is electrically connected to and between this first doped region sidewall of being electrically connected of this second electrode trims.
31. as the double gate transistor of claim 30, another sidewall of this first doped region of being electrically connected away from this second electrode of this first grid wherein, this first doped region that its upright projection is electrically connected in this first electrode.
32. as the double gate transistor of claim 20, wherein this first grid overlaps with partly being somebody's turn to do the interval, this part accounts for more than 1/3 of this interval at interval.
33. double gate transistor as claim 20, wherein this semiconductor layer comprises second doped region, the 3rd doped region and non-doped region, wherein this second doped region, the 3rd doped region and this non-doped region are between this first doped region of two ends of this semiconductor layer.
34. as the double gate transistor of claim 33, wherein this non-doped region is between this second doped region and the 3rd doped region.
35. as the double gate transistor of claim 20, wherein this semiconductor layer comprises second doped region and non-doped region, wherein this second doped region and this non-doped region are between this first doped region of two ends of this semiconductor layer.
36. as the double gate transistor of claim 35, wherein this non-doped region is between this first doped region of a wherein end of this second doped region and this semiconductor layer.
37. as the double gate transistor of claim 20, wherein one of them person of this first grid and this second grid does not overlap with this second electrode.
38. a dot structure comprises:
The double gate transistor of claim 1;
At least one electric capacity;
And at least one holding wire that is electrically connected at this double gate transistor, and this holding wire comprises at least one scan line and at least one data wire.
39. as the dot structure of claim 38, wherein this first grid of this double gate transistor is electrically connected at this scan line, and this second grid is electrically connected at this first grid.
40. as the dot structure of claim 38, more comprise lead, wherein, this first grid of this double gate transistor is electrically connected at this scan line, and this second grid is electrically connected at this lead.
41. a dot structure comprises:
Double gate transistor as claim 20;
At least one electric capacity;
And at least one holding wire that is electrically connected at this double gate transistor, and this holding wire comprises at least one scan line and at least one data wire.
42. as the dot structure of claim 41, wherein, this first grid of this double gate transistor is electrically connected at this scan line, and this second grid is electrically connected at this first grid.
43. as the dot structure of claim 42, more comprise lead, wherein, this first grid of this double gate transistor is electrically connected at this scan line, and this second grid is electrically connected at this lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610168651 CN101013725A (en) | 2006-07-10 | 2006-12-20 | Bigrid transistor and pixel structure using the same |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610105606 CN1885563A (en) | 2006-07-10 | 2006-07-10 | Dual gate transistor |
| CN200610105606.7 | 2006-07-10 | ||
| CN 200610168651 CN101013725A (en) | 2006-07-10 | 2006-12-20 | Bigrid transistor and pixel structure using the same |
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| CN105632419B (en) * | 2016-03-15 | 2018-05-11 | 深圳市华星光电技术有限公司 | The compensation circuit of liquid crystal display device and its Organic Light Emitting Diode |
| CN107063498A (en) * | 2017-05-19 | 2017-08-18 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | A kind of temperature sensor and preparation method thereof |
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