CN1885563A - Dual gate transistor - Google Patents
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- CN1885563A CN1885563A CN 200610105606 CN200610105606A CN1885563A CN 1885563 A CN1885563 A CN 1885563A CN 200610105606 CN200610105606 CN 200610105606 CN 200610105606 A CN200610105606 A CN 200610105606A CN 1885563 A CN1885563 A CN 1885563A
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Abstract
The disclosed dual-grid transistor comprises: a first grid on a plate, a first dielectric layer covered on the first grid and plate, a semiconductor layer on top of the first dielectric layer and grid, a first and second electrode on the semiconductor layer separated by someone, a second dielectric layer covered electrodes and part semiconductor layer, and a second grid on the second dielectric layer, wherein one of two grids does not overlay with the second electrode.
Description
Technical field
The present invention relates to the structural design of a kind of transistor (transistor), particularly relate to a kind of transistor with double-grid structure (dual-gate structures).
Background technology
Along with the progress that shows science and technology, compare with traditional CRT monitor, Thin Film Transistor-LCD (thin film transistor liquid crystal display, TFT-LCD) owing to have the little and advantage that do not take up space of light, thin, low radiation and volume, become at present main force's product of monitor market, be the fast development in response to liquid crystal display product, the inter-industry competition of liquid crystal panel manufacturer increases day by day.How to promote usefulness, reliability and the reduction cost of manufacture of thin-film transistor, be all important developing goal.
Amorphous silicon film transistor (amorphous silicon thin film transistor) has the function of Control current conducting, therefore often be used as LCD (liquid crystal display, LCD) or Organic Light Emitting Diode (organic light emitting diode, OLED) pixel of display (pixel) switch.
In order to promote the current lead-through ability of thin-film transistor, a kind of thin-film transistor with double-grid structure also is subjected to the attention of industry gradually in recent years.Please refer to Fig. 1, it shows existing thin-film transistor profile with double-grid structure.As shown in Figure 1, this thin-film transistor is made on the substrate 10, and its structure has mainly comprised first grid 11, second grid 16, semiconductor layer 13, drain electrode 14 and source electrode 15.
First grid 11 is formed at substrate 10 upper surfaces, and 13 of semiconductor layers are formed on the first grid 11, and wherein semiconductor layer 13 has comprised channel layer 131 and doping semiconductor layer 132.Drain electrode 14 is formed on the semiconductor layer 13 in the mode corresponding to first grid 11 two ends with source electrode 15, and drain 14 with source electrode 15 and semiconductor layer 13 become doping semiconductor layer 132.Second grid 16 with the mode corresponding to first grid 11 be formed at the drain electrode 14 and source electrode 15 on, and with first grid 11 electrical ties.Wherein the edge of second grid 16 is overlapping with the edge part of drain electrode 14 and source electrode 15.
In addition, this double-gate film transistor has more first dielectric layer 12 and second dielectric layer 17.First dielectric layer 12 is formed on the substrate 10, and covers first grid 11.17 of second dielectric layers are to be covered on drain electrode 14 and the source electrode 15, and are positioned under the second grid 16.
This double-gate film transistor arrangement has better conducting current capacity than the thin-film transistor of the single grid of tradition, and can effectively lower the electric field crowding effect, for the problem of element light leakage current sizable improvement is arranged.
Yet, in existing double-gate film transistor arrangement, because the edge of second grid 16 is overlapping with the edge part of drain electrode 14 and source electrode 15, therefore in the driving process of LCD, second grid 16 and source electrode 14 overlapping parts cause parasitic capacitance Cgs to increase easily.What specify is that the increase of parasitic capacitance Cgs can cause feed voltage (feed through voltage) to strengthen, and then influences the operating voltage of pixel electrode, the related correctness that has influence on the GTG demonstration.
In sum, the inventor is very big to the quality influence of display thoughts on existing its parasitic capacitance of double-gate film transistor arrangement Cgs, so attempt proposing a kind of structural design of double gate transistor,, and then overcome above-mentioned problem of deriving so that effectively reduce the generation of parasitic capacitance.
Summary of the invention
The object of the present invention is to provide a kind of transistor with double-grid structure, the vertical Image Location of its second grid is not overlapping with second electrode, reduce issuable parasitic capacitance between the second grid and second electrode by this, and the minimizing feed voltage is to promote the usefulness and the reliability of double gate transistor.
Another object of the present invention is to provide a kind of transistor with double-grid structure, wherein the vertical reflection of one of them of second grid and first grid not overlapping with second electrode (or second electrode be electrically connected first doped region) is overlapping.So, in the driving process of LCD, (or second electrode be electrically connected first doped region) do not have overlapping part because one of them of second grid and first grid and second electrode, reduces much so the parasitic capacitance that double gate transistor produced will be relative.
The disclosed double gate transistor of the present invention comprises first grid, is formed on the substrate.First dielectric layer is covered on first grid and the substrate.Semiconductor layer is positioned at first dielectric layer and first grid top.First electrode and second electrode lay respectively on the semiconductor layer, and between second electrode and first electrode, have one at interval, in order to two electrodes disconnected from each other.Second dielectric layer is covered in first electrode, second electrode and semiconductor layer partly.Second grid is positioned on second dielectric layer, and wherein one of them of second grid and first grid is not overlapping with second electrode.
The disclosed double gate transistor of the present invention comprises first grid, is positioned on the substrate.First dielectric layer is covered on first grid and the substrate.Semiconductor layer be positioned at first dielectric layer and first grid top, and two ends of semiconductor layer has first doped region respectively.Second dielectric layer is covered on semiconductor layer and the substrate.Second grid is positioned on second dielectric layer.The 3rd dielectric layer is covered on second grid and the substrate.
First electrode and second electrode lay respectively on the 3rd dielectric layer and are electrically connected on first doped region of two ends of semiconductor layer respectively.Wherein, between second electrode and first electrode, have at interval, in order to disconnected from each other.Wherein, one of them of first grid and second grid, not overlapping with one of them of this first doped region.
In order further to understand feature of the present invention and content, see also following about detailed description of the present invention and accompanying drawing.
Description of drawings
Fig. 1 is the generalized section of double gate transistor in existing;
Fig. 2 is the generalized section of double gate transistor of the present invention;
Fig. 3 is the generalized section of an embodiment of double gate transistor of the present invention;
Fig. 4 is the generalized section of an embodiment of double gate transistor of the present invention;
Fig. 5 A to Fig. 5 H is the various aspects of semiconductor layer in the double gate transistor;
Fig. 6 is the generalized section of an embodiment of double gate transistor of the present invention;
Fig. 7 is the generalized section of an embodiment of double gate transistor of the present invention;
Fig. 8 A to Fig. 8 C is the top view of three kinds of structure aspects of double gate transistor; And
Fig. 9 be single gridistor, existing double gate transistor and double gate transistor of the present invention in applying the process of bias voltage, the test curve that the parasitic capacitance value that is produced is described to form.
The simple symbol explanation
10,200,300,400,600,700: substrate
11,210,310,410,610,710: first grid
12,220,320,420,620,720: the first dielectric layers
13,230,330,430,630,730,830: semiconductor layer
14,240,340,440,640,740,840: the first electrodes
15,250,350,450,650,750,850: the second electrodes
255,355,455,655,755: at interval
16,260,360,460,660,760,860: second grid
17,270,370,470,670,770: the second dielectric layers
132,232,332,432,5312: doping semiconductor layer
390: isolate block
131,231,331,431,5311: channel layer
5311a: the first shallow doped layer
5311b: the second shallow doped layer
5321,5331,5341,5351,5361,5371,5381,631,731: the first doped regions
5323,5333,5343,5353,5363,5373,5383,633,734: non-doped region
5342,5352,5362,5372,5382,732: the second doped regions
733: the three doped regions
675,775: the three dielectric layers
680,780: the four dielectric layers
Embodiment
Please refer to Fig. 2, it has the transistor arrangement profile of double-grid structure for the present invention.This double gate transistor is made on the substrate 200, and its primary structure has comprised first grid 210, first dielectric layer 220, semiconductor layer 230, first electrode 240, second electrode 250, second dielectric layer 270 and second grid 260.
As shown in Figure 2, first grid 210 is formed on the substrate 200.First dielectric layer 220 is covered on first grid 210 and the substrate 200.Semiconductor layer 230 is formed on first dielectric layer 220.First electrode 240 and second electrode 250 lay respectively on the semiconductor layer 230, and between second electrode 250 and this first electrode 240, have interval 255, make two electrodes separated from one another, and can not contact with each other, and expose semiconductor layer 230 partly.
In addition, the vertical reflection at above-mentioned interval 255 falls within on the first grid 210, and in other words first electrode 240 is overlapping with the two ends of first grid 210 respectively with the vertical reflection of second electrode 250.Second dielectric layer 270 is covered on first electrode 240, second electrode 250 and the semiconductor layer 230 partly.In the present embodiment, semiconductor layer 230 comprises channel layer 231 and doping semiconductor layer 232.So first electrode 240 and second electrode 250 have doping semiconductor layer 232 respectively with the knot of semiconductor layer 230.
Second grid 260 is positioned on second dielectric layer 270, it should be noted that wherein second grid 260 is not overlapping to some extent with second electrode 250.As shown in FIG., second grid 260 is overlapped in 255 top at interval, and does not have any overlapping with second electrode 250 near a side of second electrode 250.As for, second grid 260 is away from the opposite side of second electrode 250, and is then overlapping with first electrode 240 partly.
Wanting ben be, if second grid 260 is made vertical reflection towards substrate 200, second grid 260 is near the sidewall of second electrodes 250, can fall within after vertically videoing in the scope between 1/3 to second electrode, 250 sidewalls of spacer first electrode 240.As for, second grid 260, then can fall within on first electrode 240 behind vertical reflection away from another sidewall of second electrode 250.
In other words, from the relevant position of second grid 260 with interval 255, second grid 260 is overlapping with interval 255 partly, and this partly accounts for more than 1/3 of whole interval 255 in overlapping interval.
In an embodiment of the present invention, the material of each layer structure can comprise as follows.The material of substrate 200 comprises transparency carrier (as: glass substrate, quartz base plate or materials similar), flexible base plate (as: the third vinegar base polymer, esters polymer, rubber, epoxide polymer or materials similar) or light tight substrate (as: pottery, wafer or materials similar).Material as for first grid 210 and second grid 260 comprises tin indium oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminium (Al), chromium (Cr), titanium (Ti), tungsten (W), tantalum (Ta), copper (Cu), gold (Au), silver (Ag), molybdenum (Mo), neodymium (Nd) or above-mentioned combination.
The material of semiconductor layer 230 comprises amorphous silicon, polysilicon, monocrystalline silicon, microcrystal silicon or above-mentioned combination.The material of first electrode 240 and second electrode 250 comprises tin indium oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminium (Al), chromium (Cr), titanium (Ti), tungsten (W), tantalum (Ta), copper (Cu), gold (Au), silver (Ag), molybdenum (Mo), neodymium (Nd) or above-mentioned combination.The material of first dielectric layer 220 and second dielectric layer 270 comprises silicon nitride, silica, silicon oxynitride, carborundum, organo-silicon compound or above-mentioned combination.
Because first grid 210 and second grid 260 electrical ties, when first grid 210 and second grid 260 are applied in voltage, semiconductor layer 230 can induce electric charge at two interfaces up and down near first dielectric layer 220 and second dielectric layer 270, form two current channels as upper and lower surface place, and the bias voltage of second grid can reduce transistorized critical voltage at semiconductor layer 230.So double gate transistor has higher current lead-through ability than traditional single gridistor.
Please refer to Fig. 3, it has transistorized another embodiment of double-grid structure for the present invention.This double gate transistor is made on the substrate 300, and its primary structure has comprised first grid 310, first dielectric layer 320, semiconductor layer 330, first electrode 340, second electrode 350, second dielectric layer 370 and second grid 360.In the present embodiment, semiconductor layer 330 comprises channel layer 331 and doping semiconductor layer 332.So first electrode 340 and second electrode 350 have doping semiconductor layer 332 respectively with the knot of semiconductor layer 330.
The material of above-mentioned each layer structure and position are identical with the shown embodiment of Fig. 2 haply.Variant place is, in the shown double gate transistor of Fig. 3, also comprises and isolates block 390.This isolates block 390 and is positioned on the semiconductor layer 330.As for 350 at first electrode 340 and second electrode respectively by isolate block 390 about two sides extend to cover and partly isolate block 390.It should be noted that the upper surface of isolating block 390,, constitute interval 355, and it does not expose isolation block 390 partly by the part of first electrode 340 and 350 coverings of second electrode.And isolate the acting in order to preventing when carrying out the photoetching etching program of first electrode 340 and second electrode 350 of block 390, the semiconductor layer 330 of below is damaged.In general, the material of isolation block comprises silicon nitride, silica, silicon oxynitride, carborundum, organo-silicon compound or above-mentioned combination.
Please refer to Fig. 4, it is for another embodiment of double gate transistor of the present invention.This double gate transistor is made on the substrate 400, and its primary structure has comprised first grid 410, first dielectric layer 420, semi-conductor layer 430, first electrode 440, second electrode 450, second dielectric layer 470 and second grid 460.
As shown in Figure 4, first grid 410 is formed on the substrate 400.First dielectric layer 420 then is covered on first grid 410 and the substrate 400.Semiconductor layer 430 is formed on first dielectric layer 420.First electrode 440 and second electrode 450 lay respectively on the semiconductor layer 430, and between second electrode 450 and this first electrode 440, have an interval 455, make two electrodes separated from one another, and can not contact with each other, and expose semiconductor layer 430 partly.Second dielectric layer 470 then is covered on first electrode 440, second electrode 450 and the semiconductor layer 430 partly.Second grid 460 is positioned on second dielectric layer 470.In the present embodiment, semiconductor layer 430 comprises channel layer 431 and doping semiconductor layer 432.So first electrode 440 and second electrode 450 contact with doping semiconductor layer 432 respectively.
It should be noted that wherein first grid 410 is not overlapping to some extent with second electrode 450.As shown in FIG., a side of first grid 410 close second electrodes 450, and do not have any overlapping with second electrode 450.As for, first grid 410 is away from the opposite side of second electrode 450, and is then overlapping with first electrode 440 partly.
Wanting ben be, if first grid 410 is made vertical reflection, first grid 410 is near the sidewall of second electrodes 450, can fall within after vertically videoing in the scope between 1/3 to second electrode, 450 sidewalls of spacer first electrode 440.As for, first grid 410, then can fall within on first electrode 440 behind vertical reflection away from another sidewall of second electrode 450.
In other words, from the relevant position of first grid 410 with interval 455, first grid 410 is overlapping with interval 455 partly, and this partly accounts for more than 1/3 of whole interval 455 in overlapping interval.
The disclosed double gate transistor of the present invention except above-described different structure designs, more can adopt different semiconductor layer structure aspects according to different topology requirements.Relevant semiconductor layer structure aspect is as described below.
Please refer to Fig. 5 A, shown semiconductor layer comprises channel layer 5311 and doping semiconductor layer 5312 among the figure.In a preferred embodiment, channel layer 5311 comprises the first shallow doped layer 5311a and the second shallow doped layer 5311b, wherein the second shallow doped layer 5311b is positioned on the first shallow diamicton 5311a, and the doping content of doping semiconductor layer 5312 is in fact greater than the first shallow doped layer 5311a and the second shallow doped layer 5311b, and the first shallow doped layer 5311a equates in fact with the doping content of the second shallow doped layer 5311b or unequal in fact (as: less than or greater than, preferred person, the doping content of the first shallow doped layer 5311a is in fact less than the doping content of the second shallow doped layer 5311b).
As for, in part embodiment, semiconductor layer then can have first doped region, second doped region and non-doped region.For example, in Fig. 5 B, semiconductor layer has comprised non-doped region 5323 in the middle of being positioned at and first doped region 5321 that lays respectively at these non-doped region 5323 two ends.
In Fig. 5 C, first doped region 5331 is positioned at the two ends of semiconductor layer, and the block size of first doped region 5331 at two ends can be not quite similar, but not 5333 of doped regions are between first doped region 5331 at semiconductor layer two ends, and above-mentioned each block is level to arrangement.
Please refer to Fig. 5 D, first doped region 5341 is positioned at the two ends of semiconductor layer, and 5343 of non-doped regions are between first doped region 5341 at semiconductor layer two ends.Second doped region 5342 is between first doped region 5341 and non-doped region 5343.That is to say that non-doped region 5343 is between first doped region 5341 and second doped region 5342.Wherein, the area of first doped region 5341 and second doped region 5342 can equate or unequal (as: less than or greater than), and above-mentioned each block is level to arrangement, and the doping content of second doped region 5342 and first doped region 5341 is equal in fact or unequal (as: less than or greater than, preferred person, the doping content of the second shallow doped layer 5342 is in fact less than the doping content of the first shallow doped layer 5341).
Please refer to Fig. 5 E, first doped region 5351 is defined in the two ends of semiconductor layer, and 5353 of non-doped regions are between first doped region 5341 at semiconductor layer two ends.Have two second doped regions 5352, all between first doped region 5351 and non-doped region 5353.And non-doped region 5353 is between two second doped regions 5352.Wherein, the area of first doped region 5351 and second doped region 5352 can equate or unequal (as: less than or greater than), and each block is level to arrangement, and second doped region 5352 equates in fact with the doping content of first doped region 5351 or unequal (as less than or greater than).
Please refer to Fig. 5 F, second doped region 5362 is between first doped region 5361 and non-doped region 5363, and each block is vertically to arrangement, and the doping content of second doped region 5362 and first doped region 5361 is equal in fact or unequal (as less than or greater than).
Please refer to Fig. 5 G, non-doped region 5373 is between first doped region 5371 and second doped region 5372, and each block is vertically to arrangement, and the doping content of second doped region 5372 and first doped region 5371 is equal in fact or unequal (as less than or greater than).
Please refer to Fig. 5 H, non-doped region 5383 is between first doped region 5381 and second doped region 5382, and each block is level to arrangement, and the doping content of second doped region 5382 and first doped region 5381 is equal in fact or unequal (as less than or greater than).
Please refer to Fig. 6, it has the transistor arrangement profile of double-grid structure for the present invention.This double gate transistor is made on the substrate 600, and its primary structure has comprised first grid 610, first dielectric layer 620, semiconductor layer 630, second dielectric layer 670, second grid 660, the 3rd dielectric layer 675, first electrode 640 and second electrode 650.
As shown in Figure 6, first grid 610 is formed on the substrate 600.First dielectric layer 620 is covered on first grid 610 and the substrate 600.Semiconductor layer 630 is formed at the top of first dielectric layer, 620 upper surfaces and Supreme Being's one grid 610.Wherein, the two ends of semiconductor layer 630 have first doped region 631 respectively, and have non-doped region 633 between two first doped regions 631.Second dielectric layer 670 is covered on semiconductor layer 630 and the substrate 600.Second grid 660 is positioned on second dielectric layer 670.The 3rd dielectric layer 675 is covered on second grid 660 and the substrate 600.
In addition, this double gate transistor also comprises the 4th dielectric layer 680, is formed between second dielectric layer 670 and the 3rd dielectric layer 675, and is covered in second grid 660.
One of them that it should be noted that wherein first grid 610 and second grid 660 is not overlapping with one of them of first doped region.
As shown in FIG., a side of first doped region 631 that second grid 660 close second electrodes 650 are electrically connected be overlapped in 655 top at interval, and first doped region 631 that is not electrically connected with second electrode 650 has any overlapping.The opposite side of first doped region 631 that is electrically connected away from second electrode 650 as for, second grid 260, then first doped region 631 that is electrically connected with first electrode 640 partly is overlapping.
Wanting ben is, if second grid 660 is made vertical reflection, the sidewall of first doped region 631 that second grid 660 is electrically connected near second electrodes 650 can fall within behind vertical reflection in the scope between first doped region, 631 sidewalls that 1/3 to second electrode 650 of 655 first doped regions 631 that are electrically connected apart from first electrode 640 at interval is electrically connected.Another sidewall of first doped region 631 that is electrically connected away from second electrode 650 as for, second grid 660 behind vertical reflection, then can fall within on first doped region 631 that first electrode 640 is electrically connected.
In other words, from the relevant position of second grid 660 with interval 655, second grid 660 is overlapping with interval 655 partly, and this partly accounts for more than 1/3 of whole interval 655 in overlapping interval.
As shown in FIG., a side of first doped region 631 that is electrically connected near second electrodes 650 of first grid 610.The opposite side of first doped region 631 that is electrically connected away from second electrode 650 as for, first grid 610, then first doped region 631 that is electrically connected with first electrode 640 partly is overlapping.
Wanting ben is, if first grid 610 is made vertical reflection, the sidewall of first doped region 631 that first grid 610 is electrically connected near second electrodes 650 can fall within behind vertical reflection in the scope between first doped region, 631 sidewalls that 1/3 to second electrode 650 of first doped region 631 that spacer first electrode 640 is electrically connected is electrically connected.Another sidewall of first doped region 631 that is electrically connected away from second electrode 650 as for, first grid 610 behind vertical reflection, then can fall within on first doped region 631 that first electrode 640 is electrically connected.
In other words, from the relevant position of first grid 610 with interval 655, first grid 610 is overlapping with interval 655 partly, and this partly accounts for more than 1/3 of whole interval 655 in overlapping interval.
Please refer to Fig. 7, it has transistorized another embodiment of double-grid structure for the present invention.This double gate transistor is made on the substrate 700, and its primary structure has comprised first grid 710, first dielectric layer 720, semiconductor layer 730, second dielectric layer 770, second grid 760, the 4th dielectric layer 780, the 3rd dielectric layer 775, first electrode 740 and second electrode 750.
The material of above-mentioned each layer structure and position are identical with the shown embodiment of Fig. 6 haply.Variant place is, in the shown double gate transistor of Fig. 7, semiconductor layer 730 has more defined second doped region 732, the 3rd doped region 733 and non-doped region 734 except first doped region 731.Wherein, second doped region 732, the 3rd doped region 733 and non-doped region 734 are between first doped region 731 of semiconductor layer 730 2 ends.Non-doped region 734 is between second doped region 732 and the 3rd doped region 733.
In addition, among the embodiment of Fig. 6 representative, the kenel that the structure of its semiconductor layer 730 also can similar Fig. 5 D.Semiconductor layer 730 defines first doped region 5341, second doped region 5342 and non-doped region 5343.Wherein first doped region 5341 is defined in the two ends of semiconductor layer 730, and second doped region 5342 and non-doped region 5343, between first doped region 5341 of two ends.That is to say that non-doped region 5343 is at second doped region 5342 and semiconductor layer 730 wherein between first doped region 5341 of an end.Certainly, kenel that also can similar Fig. 5 C, Fig. 5 E.
Please continue with reference to Fig. 6 and Fig. 7, wherein the vertical Image Location of one of them of first grid 660,760 and second grid 610,710 is also all not overlapping with second electrode 650,750.
Please refer to Fig. 8 A to Fig. 8 C, shown the structure top view (top view) of the disclosed double gate transistor of the present invention among the figure, comprise semiconductor layer 830, first electrode 840, second electrode 850 and second grid 860.Show that by this front view double gate transistor is a unsymmetric structure, and first electrode 840 has the both sides that two ends are positioned at second electrode 850.
Please earlier with reference to Fig. 8 A, have covering scope C among the figure, the covering scope that this is second grid 860 is generally apart from 1/3 place's to the second electrode 850 of first electrode 840 and trims the place.
And Fig. 8 A, Fig. 8 B and Fig. 8 C three figure represent three kinds of structure aspects of double gate transistor, and main difference is the difference of 860 coverage area of second grid.Among Fig. 8 A, second grid 860 is in semiconductor layer 830, and the two-end-point of the second grid 860 and first electrode 840 trims.Among Fig. 8 B, the semiconductor layer more than 830 that the semiconductor layer 830 that second grid 860 two-end-points are contained is contained than first electrode, 840 two-end-points.Among Fig. 8 C, second grid 860 is contained all first electrode 840 and part semiconductor layers 830.
Moreover in the doped region of the above embodiments of the present invention, the doping semiconductor layer, doping that is mixed comprises N type (as: phosphorus, arsenic or materials similar), P type (as: boron or materials similar) or above-mentioned combination.And, the structure of the double gate transistor of the above embodiments of the present invention can be used for dissimilar displays, comprise LCD, electro-exciting light-emitting display (electroluminescence display), Field Emission Display (field-emission display), CNT (carbon nano-tube) display (nano-carbon tubedisplay) or similar display, wherein, electro-exciting light-emitting display includes type (as: micromolecule, macromolecule), inorganic type or above-mentioned mixing.
In sum, via the description of the embodiment of Fig. 2 and Fig. 3, in the disclosed double gate transistor of the present invention, the vertical Image Location of the structure of second grid is not overlapping with second electrode, and wherein second electrode of the foregoing description is the source electrode of double gate transistor.In the driving process of LCD, because second grid and source electrode do not have overlapping part, so reducing that the parasitic capacitance Cgs that double gate transistor produced will be relative is a lot.
In addition, because first grid and second electrode when overlapping, also have similar parasitic capacitance Cgs generation.Therefore, can be with reference to the description of the embodiment of Fig. 4, Fig. 6 and Fig. 7, wherein, one of them of first grid and second grid is all not overlapping with second electrode (or second electrode be electrically connected first doped region).So, in the driving process of LCD, because one of them of first grid and second grid do not have overlapping part with source electrode (or the doped region that is electrically connected with source electrode), so reducing that the parasitic capacitance Cgs that double gate transistor produced will be relative is a lot.
So in fact in all embodiment of the present invention, one of them of first grid and second grid is not overlapping with second electrode (or second electrode be electrically connected first doped region).
Please refer to Fig. 9, three curves among the figure represent single gridistor, existing double gate transistor and double gate transistor of the present invention respectively in applying the process of bias voltage, the test curve that the parasitic capacitance value that is produced is described to form.Relatively each curve can be found out, the measured parasitic capacitance Cgs value of double gate transistor of the present invention is compared with the measured parasitic capacitance Cgs value of existing double gate transistor, and reduction is very many significantly.
Therefore, the disclosed double gate transistor of the present invention has bigger conducting electric current and can reduce the situation that light leaks electricity compared with traditional single gridistor.Simultaneously, double gate transistor of the present invention has lower parasitic capacitance Cgs value compared with existing double gate transistor, and reduces the feed voltage that is caused, and makes double gate transistor have more reliability, and the demonstration of LCD screen is more correct and stable.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with claim the person of being defined be as the criterion.
Claims (37)
1. double gate transistor comprises:
First grid is positioned on the substrate;
First dielectric layer is covered on this first grid and this substrate;
Semiconductor layer is positioned on this first dielectric layer and this first grid;
First electrode and second electrode lay respectively on this semiconductor layer, and have between this second electrode and this first electrode at interval, in order to disconnected from each other;
Second dielectric layer, be covered in this first electrode, this second electrode, with semiconductor layer partly; And
Second grid is positioned on this second dielectric layer, and wherein one of them of this second grid and this first grid is not overlapping with this second electrode.
2. double gate transistor as claimed in claim 1, wherein this second grid is near a side of this second electrode.
3. double gate transistor as claimed in claim 2, wherein this second grid is away from the opposite side of this second electrode, with partly first electrode is overlapping.
4. double gate transistor as claimed in claim 1, wherein this second grid is near the sidewall of this second electrode, apart from this first electrode, 1/3 place to and between this second electrode sidewall trims.
5. double gate transistor as claimed in claim 4, wherein this second grid is away from another sidewall of this second electrode, and its vertical reflection falls within this first electrode.
6. double gate transistor as claimed in claim 1, wherein this second grid and partly interval overlapping, this part accounts for more than 1/3 of this interval at interval.
7. double gate transistor as claimed in claim 1, wherein this first grid is near a side of this second electrode.
8. double gate transistor as claimed in claim 7, wherein this first grid is away from the opposite side of this second electrode, with partly first electrode is overlapping.
9. double gate transistor as claimed in claim 1, wherein the material of this semiconductor layer comprises amorphous silicon, polysilicon, monocrystalline silicon, microcrystal silicon or above-mentioned combination.
10. double gate transistor as claimed in claim 1, wherein this first grid is near the sidewall of this second electrode, apart from this first electrode, 1/3 place to and between this second electrode sidewall trims.
11. double gate transistor as claimed in claim 10, wherein this first grid is away from another sidewall of this second electrode, and its vertical reflection falls within this first electrode.
12. double gate transistor as claimed in claim 1, wherein this first grid and partly interval overlapping, this part accounts for more than 1/3 of this interval at interval.
13. double gate transistor as claimed in claim 1, wherein also comprise the isolation block, be positioned on this semiconductor layer, this first electrode and this second electrode are extended to cover partly by two sides about this isolation block respectively isolates on the block, and this isolation block is not then constituted this interval by the part of this first electrode and the covering of this second electrode.
14. double gate transistor as claimed in claim 1, wherein, this semiconductor layer comprises channel layer and doping semiconductor layer, on this channel layer of position.
15. double gate transistor as claimed in claim 14, wherein, this channel layer comprises the first shallow doped layer and the second shallow doped layer, is positioned on this first shallow diamicton.
16. double gate transistor as claimed in claim 1, wherein, this semiconductor layer comprises at least one first doped region, at least one second doped region and at least one non-doped region.
17. double gate transistor as claimed in claim 16, wherein, this first doped region be positioned at two ends of this semiconductor layer, and this non-doped region is between this first doped region of two ends of this semiconductor layer.
18. double gate transistor as claimed in claim 16, wherein, this second doped region is between this first doped region and this non-doped region.
19. double gate transistor as claimed in claim 16, wherein, this non-doping is between this first doped region and this second doped region.
20. a double gate transistor comprises:
First grid is positioned on the substrate;
First dielectric layer is covered on this first grid and this substrate;
Semiconductor layer is positioned on this first dielectric layer and this first grid, and two ends of this semiconductor layer have first doped region respectively;
Second dielectric layer is covered on this semiconductor layer and this substrate;
Second grid is positioned on this second dielectric layer;
The 3rd dielectric layer is covered on this second grid and this substrate; And
First electrode and second electrode, lay respectively on the 3rd dielectric layer and be electrically connected on this first doped regions of two ends of this semiconductor layer respectively, wherein, between second electrode and this first electrode, have at interval, in order to disconnected from each other, and one of them of this first grid and this second grid, not overlapping with one of them of this first doped region.
21. double gate transistor as claimed in claim 20 also comprises: the 4th dielectric layer be formed between this second dielectric layer and the 3rd dielectric layer, and it covers this second grid.
22. double gate transistor as claimed in claim 20, a side of this first doped region of being electrically connected near this second electrode of this second grid wherein is overlapped in the top at this interval.
23. double gate transistor as claimed in claim 22, the opposite side of this first doped region of being electrically connected away from this second electrode of this second grid wherein, this first doped region that is electrically connected with first electrode partly is overlapping.
24. double gate transistor as claimed in claim 20, the sidewall of this first doped region of being electrically connected near this second electrode of this second grid wherein is between trimming apart from this first doped region, 1/3 place to this first doped region sidewall that is electrically connected with this second electrode that this first electrode is electrically connected.
25. double gate transistor as claimed in claim 24, another sidewall of this first doped region of being electrically connected away from this second electrode of this second grid wherein, its vertical reflection falls within this first doped region that this first electrode is electrically connected.
26. double gate transistor as claimed in claim 20, wherein this second grid and partly interval overlapping, this part accounts for more than 1/3 of this interval at interval.
27. double gate transistor as claimed in claim 20, wherein a side of this first doped region of being electrically connected near this second electrode of this first grid.
28. double gate transistor as claimed in claim 27, the opposite side of this first doped region of being electrically connected away from this second electrode of this first grid wherein, this first doped region that is electrically connected with first electrode partly is overlapping.
29. double gate transistor as claimed in claim 20, wherein the material of this semiconductor layer comprises amorphous silicon, polysilicon, monocrystalline silicon, microcrystal silicon or above-mentioned combination.
30. double gate transistor as claimed in claim 20, the sidewall of this first doped region of being electrically connected near this second electrode of this first grid wherein is between trimming apart from this first doped region, 1/3 place to this first doped region sidewall that is electrically connected with this second electrode that this first electrode is electrically connected.
31. double gate transistor as claimed in claim 30, another sidewall of this first doped region of being electrically connected away from this second electrode of this first grid wherein, it vertically is mapped across this first doped region that this first electrode is electrically connected.
32. double gate transistor as claimed in claim 20, wherein this first grid and partly interval overlapping, this part accounts for more than 1/3 of this interval at interval.
33. double gate transistor as claimed in claim 20, wherein this semiconductor layer comprises second doped region, the 3rd doped region and non-doped region, wherein this second doped region, the 3rd doped region and this non-doped region are between this first doped region of two ends of this semiconductor layer.
34. double gate transistor as claimed in claim 33, this non-doped region wherein is between this second doped region and the 3rd doped region.
35. double gate transistor as claimed in claim 20, wherein this semiconductor layer comprises second doped region and non-doped region, and wherein this second doped region and this non-doped region are between this first doped region of two ends of this semiconductor layer.
36. double gate transistor as claimed in claim 35, this non-doped region wherein is between this first doped region of the wherein end of this second doped region and this semiconductor layer.
37. double gate transistor as claimed in claim 20, wherein one of them of this first grid and this second grid is not overlapping with this second electrode.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610105606 CN1885563A (en) | 2006-07-10 | 2006-07-10 | Dual gate transistor |
| CN 200610168651 CN101013725A (en) | 2006-07-10 | 2006-12-20 | Bigrid transistor and pixel structure using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610105606 CN1885563A (en) | 2006-07-10 | 2006-07-10 | Dual gate transistor |
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| CN1885563A true CN1885563A (en) | 2006-12-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN 200610105606 Pending CN1885563A (en) | 2006-07-10 | 2006-07-10 | Dual gate transistor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101770805B (en) * | 2008-12-29 | 2013-03-27 | 台湾积体电路制造股份有限公司 | Read/write margin improvement in SRAM design using dual-gate transistors |
| CN101834189B (en) * | 2009-03-11 | 2015-07-08 | 统宝光电股份有限公司 | Image display system |
| WO2015135270A1 (en) * | 2014-03-11 | 2015-09-17 | 京东方科技集团股份有限公司 | Oled array substrate, manufacturing method therefor, and display |
-
2006
- 2006-07-10 CN CN 200610105606 patent/CN1885563A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101770805B (en) * | 2008-12-29 | 2013-03-27 | 台湾积体电路制造股份有限公司 | Read/write margin improvement in SRAM design using dual-gate transistors |
| CN101834189B (en) * | 2009-03-11 | 2015-07-08 | 统宝光电股份有限公司 | Image display system |
| WO2015135270A1 (en) * | 2014-03-11 | 2015-09-17 | 京东方科技集团股份有限公司 | Oled array substrate, manufacturing method therefor, and display |
| US9583551B2 (en) | 2014-03-11 | 2017-02-28 | Boe Technology Group Co., Ltd. | OLED array substrate, method for fabricating the same, and display device |
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