CN107968096A - The preparation method of array base palte, display panel and array base palte - Google Patents
The preparation method of array base palte, display panel and array base palte Download PDFInfo
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- CN107968096A CN107968096A CN201711180716.4A CN201711180716A CN107968096A CN 107968096 A CN107968096 A CN 107968096A CN 201711180716 A CN201711180716 A CN 201711180716A CN 107968096 A CN107968096 A CN 107968096A
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- layer
- array base
- base palte
- active layer
- viewing area
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- 238000002360 preparation method Methods 0.000 title claims abstract description 23
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims abstract description 68
- 229910052751 metal Inorganic materials 0.000 claims abstract description 68
- 239000002184 metal Substances 0.000 claims abstract description 68
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims abstract description 48
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052733 gallium Inorganic materials 0.000 claims abstract description 26
- 229910052738 indium Inorganic materials 0.000 claims abstract description 26
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000011787 zinc oxide Substances 0.000 claims abstract description 24
- 239000010410 layer Substances 0.000 claims description 361
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical group [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 29
- 239000011241 protective layer Substances 0.000 claims description 29
- 229910052709 silver Inorganic materials 0.000 claims description 29
- 239000004332 silver Substances 0.000 claims description 29
- 238000005530 etching Methods 0.000 claims description 28
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 13
- 229910003437 indium oxide Inorganic materials 0.000 claims description 5
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 22
- 238000004519 manufacturing process Methods 0.000 abstract description 14
- 230000008569 process Effects 0.000 abstract description 9
- 230000002829 reductive effect Effects 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 93
- 238000000151 deposition Methods 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 239000000463 material Substances 0.000 description 12
- 230000002093 peripheral effect Effects 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000008021 deposition Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 238000001771 vacuum deposition Methods 0.000 description 7
- 239000004411 aluminium Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 229910004205 SiNX Inorganic materials 0.000 description 5
- 238000004380 ashing Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 239000002905 metal composite material Substances 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 238000004080 punching Methods 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 238000004026 adhesive bonding Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 230000007704 transition Effects 0.000 description 4
- 239000010949 copper Substances 0.000 description 3
- 230000036961 partial effect Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000010363 phase shift Effects 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- GRPQBOKWXNIQMF-UHFFFAOYSA-N indium(3+) oxygen(2-) tin(4+) Chemical compound [Sn+4].[O-2].[In+3] GRPQBOKWXNIQMF-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention relates to the preparation method of a kind of array base palte, display panel and array base palte, array base palte includes：Substrate；The grid being formed on substrate；The insulating layer being formed on grid；The active layer being formed on insulating layer, wherein, active layer is indium gallium zinc oxide；The complex metal layer being formed on active layer, complex metal layer includes the tin indium oxide film layer being connected with active layer and the metallic diaphragm being connected with tin indium oxide film layer, wherein, metallic diaphragm is pixel layer in offering port, tin indium oxide film layer part corresponding with viewing area in viewing area.Active layer is prepared with indium gallium zinc oxide so that active layer is better contacted with the source/drain containing tin indium oxide film layer, effectively reduces contact berrier so that the electron mobility of array base palte is improved；On the other hand, using the tin indium oxide film layer in complex metal layer as pixel layer, process can be reduced, and then effectively improves production efficiency, reduces production cost.
Description
Technical field
The present invention relates to array base palte manufacturing technology field, more particularly to array base palte, display panel and array base palte
Preparation method.
Background technology
TFT (Thin Film Transistor) refers to array base palte, and the liquid crystal display being made by it is referred to as
TFT LCD (Liquid Crystal Display, liquid crystal display), TFT LCD are that current display line compares in the industry mainstream
One of display device, its feature are that each liquid crystal pixel point is driven by being integrated in the tft array substrate behind pixel
It is dynamic, due to being directly to drive, so TFT LCD can accomplish the high reaction speed of comparison, brightness and contrast, it is current
One of best LCD color display apparatus.
Traditional A-Si (non-crystalline silicon) TFT technological processes are usually to pass through grid layer, active layer, source/drain layer, protection
The preparation of layer and 5 procedure of pixel layer, the A-Si TFT process prepared using above-mentioned traditional handicraft is more, and cost occupies height not
Under, cause the higher price of TFT LCD.
The content of the invention
Based on this, it is necessary to provide the preparation method of a kind of array base palte, display panel and array base palte.
A kind of array base palte, including：
Substrate；
The grid being formed on the substrate；
The insulating layer being formed on the grid；
The active layer being formed on the insulating layer, wherein, the active layer is indium gallium zinc oxide；
The complex metal layer being formed on the active layer, the complex metal layer include the oxygen being connected with the active layer
Change indium tin film layer and the metallic diaphragm that is connected with the tin indium oxide film layer, wherein, the metallic diaphragm in viewing area in opening
Equipped with port, tin indium oxide film layer part corresponding with the viewing area is pixel layer.
In one of the embodiments, protective layer is further included, the protective layer is formed on the complex metal layer.
In one of the embodiments, the metallic diaphragm is silver film.
In one of the embodiments, the insulating layer offers through hole.
A kind of display panel, including the array base palte described in any of the above-described embodiment.
A kind of preparation method of array base palte, including：
Grid is formed on substrate；
Insulating layer is formed on the grid；
The active layer of indium gallium zinc oxide is prepared on the insulating layer；
The active layer is performed etching；
Complex metal layer is prepared on the active layer, the complex metal layer includes tin indium oxide film layer and metal film
Layer, the indium tin oxide layer are connected with the active layer, and the metallic diaphragm is connected with the indium tin oxide layer；
The corresponding part in the viewing area metallic diaphragm is etched away, the complex metal layer outside the viewing area is set
Source/drain is set to, the corresponding part tin indium oxide film layer in the viewing area is arranged to pixel layer.
In one of the embodiments, it is described step is performed etching to the active layer to be：
The active layer is exposed, developed and etched, the part active layer in the viewing area is etched away.
In one of the embodiments, described the step of etching away the corresponding part in the viewing area metallic diaphragm, is：
To the exposure of the corresponding part in the viewing area metallic diaphragm, development and etching, by the corresponding part in viewing area
The metallic diaphragm etches away.
In one of the embodiments, described the step of etching away the corresponding part in the viewing area metallic diaphragm it
After further include：
Protective layer is prepared on the complex metal layer.
In one of the embodiments, the metallic diaphragm is silver film.
The preparation method of above-mentioned array base palte, display panel and array base palte, on the one hand, being prepared with indium gallium zinc oxide has
Active layer so that active layer is better contacted with the source/drain containing tin indium oxide film layer, effectively reduces contact berrier so that
The electron mobility of array base palte is improved；On the other hand, using the tin indium oxide film layer in complex metal layer as pixel layer,
Process can be reduced, and then effectively improves production efficiency, reduces production cost.
Brief description of the drawings
Fig. 1 is the part section structural representation of the array base palte of one embodiment；
Fig. 2A is the structure diagram of the array base palte in preparation process of one embodiment；
Fig. 2 B are the structure diagram of the array base palte in preparation process of one embodiment；
Fig. 2 C are the structure diagram of the array base palte in preparation process of one embodiment；
Fig. 2 D are the structure diagram of the array base palte in preparation process of one embodiment；
Fig. 2 E are the structure diagram of the array base palte in preparation process of one embodiment；
Fig. 2 F are the structure diagram of the array base palte in preparation process of one embodiment；
Fig. 3 is the flow diagram of the preparation method of the array base palte of one embodiment.
Embodiment
For the ease of understanding the present invention, the present invention is described more fully below with reference to relevant drawings.In attached drawing
Give the better embodiment of the present invention.But the present invention can realize in many different forms, however it is not limited to herein
Described embodiment.On the contrary, the purpose for providing these embodiments is to make to understand more the disclosure
Add thorough and comprehensive.
Unless otherwise defined, all of technologies and scientific terms used here by the article is with belonging to technical field of the invention
The normally understood implication of technical staff is identical.Term used herein is intended merely to the mesh of description specific embodiment
, it is not intended that in the limitation present invention.Term as used herein " and/or " include one or more relevant Listed Items
Arbitrary and all combination.
For example, a kind of array base palte, including：Substrate；The grid being formed on the substrate；It is formed on the grid
Insulating layer；The active layer being formed on the insulating layer, wherein, the active layer is indium gallium zinc oxide；Have described in being formed at
Complex metal layer in active layer, the complex metal layer include the tin indium oxide film layer that is connected with the active layer and with it is described
The metallic diaphragm of tin indium oxide film layer connection, wherein, the metallic diaphragm is in offering port, the tin indium oxide in viewing area
Film layer part corresponding with the viewing area is pixel layer.
For example, a kind of display panel, including the array base palte described in above-described embodiment.
For example, a kind of preparation method of array base palte, including：Grid is formed on substrate；Formed on the grid exhausted
Edge layer；The active layer of indium gallium zinc oxide is prepared on the insulating layer；The active layer is performed etching；In the active layer
On prepare complex metal layer, the complex metal layer includes tin indium oxide film layer and metallic diaphragm, the indium tin oxide layer and institute
Active layer connection is stated, the metallic diaphragm is connected with the indium tin oxide layer；By the corresponding part in the viewing area metallic diaphragm
Etch away, the complex metal layer outside the viewing area is arranged to source/drain, by corresponding part institute in the viewing area
State tin indium oxide film layer and be arranged to pixel layer.
In above-described embodiment, on the one hand, prepare active layer with indium gallium zinc oxide so that active layer is with containing tin indium oxide
The source/drain of film layer better contacts with, and effectively reduces contact berrier so that the electron mobility of array base palte is improved；
On the other hand, using the tin indium oxide film layer in complex metal layer as pixel layer, process can be reduced, and then effectively improve production
Efficiency, reduces production cost.
In one embodiment, as shown in Figure 1, there is provided a kind of array base palte 10, including：Substrate 100；It is formed at the base
Grid 210 and storage capacitor electrode (storage capacitor electrode being omitted in figure, do not show) on plate 100；It is formed on the grid 210
Insulating layer 220；The active layer 230 being formed on the insulating layer 220, wherein, the active layer 230 aoxidizes for indium gallium zinc
Thing；The complex metal layer 240 being formed on the active layer 230, the complex metal layer 240 include and the active layer 230
The tin indium oxide film layer 241 of connection and the metallic diaphragm 242 being connected with the tin indium oxide film layer 241, wherein, the metal
Film layer 242 is in offering port, the tin indium oxide film layer 241 and the 251 corresponding portion of viewing area in the viewing area 251
It is divided into pixel layer.
Specifically, array base palte has viewing area, which is transparent region, for printing opacity and then display pixel.Example
Such as, which also has switch region 252, and the switch region 252 is interior to include grid formed with thin film transistor (TFT), the thin film transistor (TFT)
210th, insulating layer 220, active layer 230 and source/drain, the i.e. part of the metal composite layer 240 outside viewing area 251 are source/drain
Pole.
For example, the tin indium oxide film layer 241 part corresponding with the port is arranged to pixel layer, for example, with it is described
The part tin indium oxide film layer 241 and the metallic diaphragm 242 that metallic diaphragm 242 connects are arranged to source/drain
(Source＆Drain), i.e., the part that metal composite layer is not etched is source/drain, the portion alignd in metal composite layer with port
It is pixel layer (Pixel layers) to divide tin indium oxide film layer 241, which is alternatively referred to as pixel electrode, for example, the source/drain bag
Include source electrode and drain electrode.Since source/drain and pixel layer are respectively a part for tin indium oxide film layer 241, so so that source/drain
Pole is connected with pixel layer.
Specifically, which is glass substrate, which is transparent glass substrate, for example, the grid 210
(Gate) it is metal gates 210, which is isolated by insulating layer 220 with complex metal layer 240, which is used as battle array
The scan line of row substrate 10, the renewal of the picture for controlling display, and for controlling switching on for active layer 230
With closing.
The insulating layer 220 is used to be dielectrically separated from grid 210 and active layer 230, isolated gate 210 and source/drain, for example,
The insulating layer 220 is SiNx layer, for example, the insulating layer 220 includes SiO2 (silica) layers and SiNx layer being connected with each other.Should
(Island layers) switches being used for as pixel of active layer 230, the signal for controlling source/drain are inputted to pixel, also used
In the bright dark degree of control pixel light emission.Source/drain is used to be used as signal wire, controls each pixel to need the magnitude of voltage reached,
The brightness of pixel, and peripheral metal circuit of the source/drain also as array base palte 10 are controlled, for antistatic.Pixel layer
Referred to as pixel ITO layer or pixel electrode, for the electrode plate as pixel, for controlling the torsion of liquid crystal, determine the saturating of pixel
Light path degree.
In the present embodiment, since the tin indium oxide film layer 241 in source/drain and the indium gallium zinc oxide of active layer 230 are equal
Containing indium oxide, therefore, source/drain can be better contacted with active layer 230, so as to reduce source/drain and active layer
Contact berrier between 230, without realizing both connections using transition zone so that the structure of array base palte 10 is more simple
It is single, reduce technological process, reduce production cost.
In addition, the metallic diaphragm 242 in the complex metal layer 240 of source/drain has compared with low resistance, source/drain is enabled to
More preferably, for example, the metallic diaphragm 242 is silver film, the material of the silver film is metallic silver (Ag) to the electric conductivity of pole, i.e., this is multiple
Metal layer 240 includes tin indium oxide film layer 241 and silver film, for example, the silver film and being connected with the silver film
The tin indium oxide film layer 241 is arranged to source/drain, which includes silver film and the indium oxide being connected with silver film
Tin film layer 241, metallic silver have relatively low resistance so that source/drain has preferable electric conductivity, so that array base palte 10
Overall performance more preferably.
For example, by being performed etching to silver film, form the port, for example, the port with the viewing area 251,
For example, the silver film in viewing area is etched away, figure which forms after being etched for silver film, in this way, with the port
Corresponding partial oxidation indium tin film layer 241 is pixel layer.
In one embodiment, array base palte 10 further includes protective layer 250, and the protective layer 250 is formed at described compound
On metal layer 240, for example, the protective layer 250 is formed on the active layer 230.For example, complex metal layer 240 is switching
252 corresponding position of area offers raceway groove (Channel), and the active layer 230 is connected by raceway groove with protective layer 250.For example,
The protective layer 250 is at least partially arranged in the raceway groove.For example, the protective layer 250 connects with the metallic diaphragm 242
Connect, for example, the protective layer 250 is connected with the silver film, for example, the protective layer 250 has by the raceway groove with described
Active layer 230 connects.By the inside figure of the protection array base palte 10 of the protective layer 250, active layer 230 is protected.It is logical
The protection of overprotection layer 250 so that the service life of array base palte 10 is improved.
In one embodiment, the insulating layer 220 offers multiple through holes 221, and the exterior cabling of array base palte 10 should
Through hole is connected with grid 210, for example, the through hole 221 is opened in the position that insulating layer 220 is located at outside viewing area 251, for example, respectively
It is respectively arranged with tin indium oxide film layer in through hole, the tin indium oxide film layer in each through hole is connected with each other.That is, in insulating layer
After 220 etchings form through hole 221, tin indium oxide film layer is prepared on insulating layer 220 so that tin indium oxide film layer is formed at through hole
In 221, in this way, the tin indium oxide film layer in each through hole 221 can connect, and exterior cabling can pass through the oxidation in through hole
Indium tin film layer is connected with grid.For example, using phase deviation mask plate, by yellow light technique and photoresist ashing process to active
The insulating layer 220 of the periphery of layer 230 carries out gluing, exposure, development and etching, and through hole 221 is formed on insulating layer 220, in this way,
During the peripheral 220 depositing indium tin oxide film layer of insulating layer of active layer 230 and active layer 230, tin indium oxide film layer can sink
Product is used as peripheral wiring, in this way, peripheral cabling is in through hole 221 in the tin indium oxide membrane layer portion of peripheral area deposition
It can be connected by the tin indium oxide film layer in through hole 221 with grid 210.
In one embodiment, there is provided a kind of display panel 100, including the array base palte described in any of the above-described embodiment
10.For example, a kind of display device, including display panel 100 in above-described embodiment.For example, a kind of display, including above-mentioned implementation
The display device of example.
In one embodiment, there is provided a kind of preparation method of array base palte 10, as shown in figure 3, including：
Step 302, grid is formed on substrate.
For example, grid and storage capacitance Cs electrodes are formed on substrate.The array base palte has viewing area 251 and switch region
252.For example, grid and storage capacitance Cs electrodes are formed on the switch region 252 of substrate.
Specifically, as shown in Figure 2 A, grid 210 and storage capacitance Cs electrode (not shown) are formed on the substrate 100, should
Grid 210 is 210 metal layer of grid, for example, the material of the grid 210 is molybdenum (Mo) and aluminium (AL) composition metal, for example, grid
210 include molybdenum layer and aluminium lamination, for example, the material of the grid 210 is titanium (Ti) and aluminium (AL) composition metal, for example, the grid 210
Including titanium layer and aluminium lamination, for example, the material of the grid 210 is nickel (Ni) and copper (Cu) metal composite layer, for example, the grid 210
Including nickel layer and layers of copper, and for example, grid 210 is tin indium oxide (ITO) layer and silver-colored (Ag) metal composite layer, for example, the grid 210
Including indium tin oxide layer and silver layer.
For example, grid 210 is deposited on the glass substrate, for example, vacuum coating deposits to form grid on the glass substrate
210, for example, vacuum coating deposits to form 210 metal layer of grid on the glass substrate, and 210 metal layer of grid is exposed,
Development and etching, form the grid 210 of preset pattern.
Step 304, insulating layer is formed on the grid.
Specifically, as shown in Figure 2 B, insulating layer 220 is formed on the grid 210, the material of the insulating layer 220 is
SiNx (silicon nitride), for example, the depositing insulating layer 220 on the grid 210 for forming preset pattern.For example, the insulating layer 220 is
SiNx layer, for example, the insulating layer 220 includes SiO2 (silica) layers and SiNx layer being connected with each other.The insulating layer be used for every
From grid 210.For example, form insulating layer on the switch region 252 of the substrate and viewing area.
Step 306, the active layer of indium gallium zinc oxide is prepared on the insulating layer.
As shown in Figure 2 C, the active layer 230 of indium gallium zinc oxide is prepared on the insulating layer 220.For example, the active layer
230 material is indium gallium zinc oxide (IGZO), for example, vacuum coating deposits to form active layer 230, example on insulating layer 220
Such as, vacuum coating deposits one layer of indium gallium zinc oxide layer on insulating layer 220, which is active layer 230.
Specifically, which is the amorphous oxides containing indium, gallium and zinc, the carrier of indium gallium zinc oxide
Mobility is 20~30 times of the non-crystalline silicon (a-si) of traditional A-Si TFT.Active layer 230 in the present embodiment uses indium gallium
Zinc oxide is prepared, and can effectively improve charge-discharge velocity of the array base palte 10 to pixel electrode, and then improve pixel
Response speed, improves the line scanning rate of pixel.
Step 308, the active layer is performed etching.
As shown in Figure 2 D, the active layer 230 is performed etching so that the active layer 230 in the viewing area 251 and
The part of outer peripheral areas is etched away, for example, being performed etching to the active layer 230 so that the active layer 230 is in switch region
Outer portion is all etched away so that the insulating layer 220 in viewing area 251 is exposed.For example, the vacuum coating on insulating layer 220
Indium gallium zinc oxide layer is deposited, gluing, exposure, development and etching are carried out to the indium gallium zinc oxide layer, formed in switch region 252
Active layer 230, and the active layer segment outside switch region 252 is etched away.
For example, this step is further included forms through hole 221 to the punching of insulating layer 220 outside viewing area 251.For example, to periphery
The insulating layer 220 in region carries out punching and forms through hole 221.
Specifically, in this step, using phase deviation mask plate, by yellow light technique and photoresist ashing process to indium gallium
Zinc oxide layer and the insulating layer 220 of indium gallium zinc oxide layer periphery carry out gluing, exposure, development and etching, prepare active
Layer 230, and through hole 221 is formed to the punching of insulating layer 220 outside viewing area 251, which is located in switch region 252.Value
Obtain one to be mentioned that, since part of the active layer 230 outside switch region 252 is all etched away so that the insulating layer in viewing area
220 is exposed.
It is noted that in the present embodiment, phase deviation mask plate is also known as skew shift cover (PSM, Phase Shift
Mask), its some places plus last layer phase transfer layer (Phase-Shift Layer) mainly on light shield, to improve exposure
Comparison of light and shade, using skew shift cover need not change its exposure light source and photoresist technology i.e. can reach enhancing exposure machine solution
As ability or the depth of focus for the exposure image for increasing exposure machine.
Yellow light technique in the present embodiment is Half Tone Method, its principle is that make use of the partial light permeability of grating
PR (photoresist) can not exclusively being exposed, semi-transparent membrane part is determined the amount of light transmission by the difference in height of required passivation layer,
Light penetration is 35% of normal segments or so under normal circumstances.
Photoresist ashing process is performs etching photoresist using oxygen plasma, since photoresist is by C, H and O etc.
Element composition has photosensitive high molecular polymer, therefore, when being etched with oxygen plasma to it, oxygen plasma and photoetching
Glue occurs chemical reaction generation volatile gas and is taken away by vacuum pump, as a result so that photoresist is constantly thinned, reduces, and due to
Etching to photoresist is isotropic, and therefore, it is laterally also etched photoresist lines thinned while, as a result lines
Attenuate.
Step 310, prepare complex metal layer on the active layer, the complex metal layer include tin indium oxide film layer and
Metallic diaphragm, the indium tin oxide layer are connected with the active layer, and the metallic diaphragm is connected with the indium tin oxide layer.
For example, prepare complex metal layer on insulating layer in active layer and viewing area, for example, in active layer and aobvious
Show and tin indium oxide film layer and metallic diaphragm are sequentially prepared on the insulating layer in area.
As shown in Figure 2 E, complex metal layer 240 is prepared on the active layer 230, the complex metal layer 240 includes oxygen
Change indium tin film layer 241 and metallic diaphragm 242, the indium tin oxide layer are connected with the active layer 230, the metallic diaphragm 242
It is connected with the indium tin oxide layer
Specifically, which is formed by the material deposition of composition metal, for example, on the active layer 230
Vacuum coating deposits complex metal layer 240, which includes tin indium oxide (ITO) and the gold with compared with low resistance characteristic
Belong to, for example, the complex metal layer 240 includes tin indium oxide film layer 241 and the metallic diaphragm 242 being connected with each other, indium oxide tin film
The material of layer 241 is tin indium oxide, and the material of the metallic diaphragm 242 is the metal with compared with low resistance characteristic, for example, active
Vacuum coating depositing indium tin oxide film layer 241 and metallic diaphragm 242 successively on layer 230.For example, the metallic diaphragm 242 is silverskin
Layer.
It is noted that since active layer 230 is etched, the part that active layer 230 is etched is corresponding
Insulating layer 220 is exposed, and when depositing complex metal layer 240, complex metal layer 240 is by active layer 230 and exposed insulation
Deposited on layer 220, so that complex metal layer 240 is covered in active layer 230 and the insulating layer of the periphery of active layer 230
220。
It should be understood that complex metal layer 240 includes indium oxide layer tin film layer 241, its material is tin indium oxide, and
The material of active layer 230 is indium gallium zinc oxide, and tin indium oxide and indium gallium zinc oxide all contain indium oxide, therefore, oxidation
Indium tin film layer 241 can be better contacted with active layer 230 so that contact berrier between the two is smaller.
Step 312, the corresponding part in the viewing area metallic diaphragm is etched away, will be described compound outside the viewing area
Metal layer is arranged to source/drain, and the corresponding part tin indium oxide film layer in the viewing area is arranged to pixel layer.
As shown in Figure 2 F, the metallic diaphragm 242 is etched so that the corresponding part metals film layer in the viewing area 251
242 and the metallic diaphragm 242 of peripheral desired zone be etched away, with the corresponding composition metal outside the viewing area 251
Layer 240 is source/drain, is pixel layer with the 251 corresponding part of the viewing area tin indium oxide film layer 241.
In the present embodiment, phase deviation mask plate is used in metallic diaphragm 242, passes through yellow light technique and photoresist ashing work
Skill is carrying out gluing, exposure, development and etching so that in viewing area 251 and outer peripheral areas part 242 quilt of metallic diaphragm
Etch away, so so that metallic diaphragm 242 is etched away in 251 inside points of viewing area, so that the portion in viewing area 251
Divide tin indium oxide film layer 241 exposed, and using the partial oxidation indium tin film layer 241 in viewing area 251 as pixel layer, that is, as
Plain electrode.
For example, described the step of etching away the corresponding part in the viewing area metallic diaphragm, is：To the viewing area pair
Part metallic diaphragm exposure, development and the etching answered, the corresponding part in the viewing area metallic diaphragm is etched away.Example
Such as, as shown in Figure 2 F, complex metal layer 240 is exposed, developed and etched, by outside channel region, display pixel area and periphery
The corresponding part in the region metallic diaphragm 242 etches away, and light is taken off after then etching the tin indium oxide film layer of above-mentioned position again
Photoresist, the complex metal layer 240 in switch region 252 just etch away, that is, by 242 He of metallic diaphragm in switch region 252
Tin indium oxide film layer 241 etches away, and forms raceway groove in switch region 252, and make it that the active layer 230 in switch region 252 is exposed.Again
Metallic diaphragm 242 in viewing area is etched away so that tin indium oxide film layer 241 is exposed, through photoresist in final switch area 252
Ashing leaks out complex metal layer 240, and the complex metal layer 240 leaked out is used as source/drain.
In this way, with the metallic diaphragm 242 and tin indium oxide film layer 241 that are not etched away in switch region 252 for source/drain,
It is pixel layer with the tin indium oxide film layer 241 in viewing area.For example, the pixel layer is Pixel layers, i.e. the pixel layer is Pixel
ITO.It should be understood that due to tin indium oxide film layer 241 and metallic diaphragm 242 as source/drain, metallic diaphragm 242 has
There is relatively low resistance, therefore so that source/drain has preferable electric conductivity.Further, since tin indium oxide film layer 241 can be with
Active layer 230 better contacts with so that contact berrier between the two is smaller, therefore so that the performance of array base palte 10 is more preferably.
It should be understood that the contact berrier between metal and semiconductor is " Schottky barrier ", traditional array base palte
Larger potential barrier, active layer 230 will be produced between 10 active layer 230 and the source/drain of metal using A-Si (non-crystalline silicon)
For semiconductor, and source/drain is metal, therefore, in order to reduce potential barrier between the two, it is necessary to increase by one layer of n+ therebetween
A-Si is to make transition zone, so so that technique is complex, in the present embodiment, since tin indium oxide film layer 241 can be with indium gallium
The active layer 230 of zinc oxide better contacts with, and contact berrier between the two is smaller, it is therefore not necessary to increase transition zone, subtracts
Lack and prepared material so that technique is more simple, and reduces production cost.
Further, since metallic diaphragm 242 is etched so that the corresponding tin indium oxide film layer of metal layer after etching
241 is exposed, using the tin indium oxide film layer 241 of this part as pixel layer, without additional deposition pixel layer, further simplify work
Skill, and reduce further production technology.
In one embodiment, further included after step 312 and pixel layer is exposed, develop and is etched.
For example, the tin indium oxide film layer 241 to the 251 corresponding part of viewing area of active layer 230 be exposed, develop and
Etching so that pixel layer forms preset pattern.
In one embodiment, described the step of being performed etching to the active layer, is：The active layer is exposed,
Development and etching, the part active layer in the viewing area is etched away.As shown in Figure 2 E, to the active layer 230 into
Row exposure, development and etching, by the viewing area 251 and the part active layer of outer peripheral areas etches away, and then make
It is exposed to obtain part of the insulating layer in viewing area.
In one embodiment, in the corresponding part in the viewing area by the active layer, the metallic diaphragm is carved
Further included after the step of erosion：Protective layer is prepared on the complex metal layer.
As shown in Figure 1, prepare protective layer 250 on the complex metal layer 240.For example, sink on complex metal layer 240
Product protective layer 250 (Passivation), for example, the deposition plating protective layer 250 on metallic diaphragm 242, for example, in silver film
Upper deposition plating protective layer 250, for example, the deposition plating protective layer 250 on silver film and active layer 230, for example, the silver film
With protective layer is formed in raceway groove, protected by the inside figure of 250 protective film transistor of protective layer, and to active layer 230
Shield so that the service life of array base palte 10 is improved.
For example, after deposition protective layer 250, yellow light technique is carried out again to protective layer 250, the part in viewing area is protected
Layer etches away so that the tin indium oxide film layer 241 in viewing area is exposed.
Protective layer 250 in the present embodiment compared to the protective layer 250 prepared in traditional amorphous silicon technology, due to source/
Drain electrode is directly connected to pixel layer, and traditional thin film transistor (TFT) source/drain electrode and the connection of pixel layer are needed by protecting
Sheath punching is attached, due to that need not be punched to protective layer, so as to avoid the via that protective layer occurs due to punching inverse
Angle, spend the problems such as pitting corrosion, improves the yield of product.
In one embodiment, the metallic diaphragm 242 is silver film, for example, the metallic diaphragm 242 is Ag film layers, example
Such as, tin indium oxide film layer 241 and silver film are sequentially depositing in the peripheral insulating layer 220 of active layer 230 and active layer 230, i.e.,
The complex metal layer 240 includes tin indium oxide film layer 241 and silver film, for example, the silver film and with the silver film connect
The tin indium oxide film layer 241 connect is arranged to source/drain, which includes silver film and the oxygen being connected with silver film
Change indium tin film layer 241, metallic silver has relatively low resistance so that source/drain has preferable electric conductivity, so that array base
The overall performance of plate 10 is more preferably.
In above-described embodiment, 4 yellow light techniques are use only, without carrying out individually deposition and yellow light technique to pixel layer,
Preparation process compared to the array base palte 10 of traditional non-crystalline silicon has lacked a yellow light technique, effectively reduces production cost,
Improve production efficiency.Due to the tin indium oxide film layer 241 and metallic diaphragm 242 as source/drain, metallic diaphragm 242 has
Relatively low resistance, therefore so that source/drain has preferable electric conductivity.Further, since tin indium oxide film layer 241 can be with having
Active layer 230 better contacts with so that contact berrier between the two is smaller, therefore so that the performance of array base palte 10 more preferably, subtracts
Transition zone is lacked so that the technique of array base palte 10 is more simple, effectively improves production efficiency, reduces production cost.
It should be noted that in said system embodiment, included modules are simply drawn according to function logic
Point, but above-mentioned division is not limited to, as long as corresponding function can be realized；In addition, each function module is specific
Title is also only to facilitate mutually distinguish, the protection domain being not intended to limit the invention.
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality
Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope that this specification is recorded all is considered to be.
Embodiment described above only expresses the several embodiments of the present invention, its description is more specific and detailed, but simultaneously
Cannot therefore it be construed as limiting the scope of the patent.It should be pointed out that come for those of ordinary skill in the art
Say, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
- A kind of 1. array base palte, it is characterised in that including：Substrate；The grid being formed on the substrate；The insulating layer being formed on the grid；The active layer being formed on the insulating layer, wherein, the active layer is indium gallium zinc oxide；The complex metal layer being formed on the active layer, the complex metal layer include the indium oxide being connected with the active layer Tin film layer and the metallic diaphragm being connected with the tin indium oxide film layer, wherein, the metallic diaphragm in viewing area in offering Port, tin indium oxide film layer part corresponding with the viewing area is pixel layer.
- 2. array base palte according to claim 1, it is characterised in that further include protective layer, the protective layer is formed at institute State on complex metal layer.
- 3. array base palte according to claim 1, it is characterised in that the metallic diaphragm is silver film.
- 4. array base palte according to claim 1, it is characterised in that the insulating layer offers through hole.
- 5. a kind of display panel, it is characterised in that including the array base palte described in any one of claims 1 to 4.
- A kind of 6. preparation method of array base palte, it is characterised in that including：Grid is formed on substrate；Insulating layer is formed on the grid；The active layer of indium gallium zinc oxide is prepared on the insulating layer；The active layer is performed etching；Complex metal layer is prepared on the active layer, the complex metal layer includes tin indium oxide film layer and metallic diaphragm, institute State indium tin oxide layer to be connected with the active layer, the metallic diaphragm is connected with the indium tin oxide layer；The corresponding part in the viewing area metallic diaphragm is etched away, the complex metal layer outside the viewing area is arranged to Source/drain, pixel layer is arranged to by the corresponding part tin indium oxide film layer in the viewing area.
- 7. the preparation method of array base palte according to claim 1, it is characterised in that described to be carved to the active layer Losing step is：The active layer is exposed, developed and etched, the part active layer in the viewing area is etched away.
- 8. the preparation method of array base palte according to claim 7, it is characterised in that described by the corresponding part in viewing area The step of metallic diaphragm etches away be：To the exposure of the corresponding part in the viewing area metallic diaphragm, development and etching, by described in the corresponding part in viewing area Metallic diaphragm etches away.
- 9. the preparation method of array base palte according to claim 7, it is characterised in that described by the corresponding portion in viewing area Further included after the step of dividing the metallic diaphragm to etch away：Protective layer is prepared on the complex metal layer.
- 10. the preparation method of array base palte according to claim 6, it is characterised in that the metallic diaphragm is silver film.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111326082A (en) * | 2020-04-14 | 2020-06-23 | Tcl华星光电技术有限公司 | Backboard unit, manufacturing method thereof and display device |
| WO2021159578A1 (en) * | 2020-02-10 | 2021-08-19 | Tcl华星光电技术有限公司 | Display panel |
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| CN101097927A (en) * | 2006-06-27 | 2008-01-02 | 三菱电机株式会社 | Active matrix TFT array substrate and method of manufacturing the same |
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| CN101097927A (en) * | 2006-06-27 | 2008-01-02 | 三菱电机株式会社 | Active matrix TFT array substrate and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2021159578A1 (en) * | 2020-02-10 | 2021-08-19 | Tcl华星光电技术有限公司 | Display panel |
| US11961841B2 (en) | 2020-02-10 | 2024-04-16 | Tcl China Star Optoelectronics Technology Co., Ltd. | Display panel |
| CN111326082A (en) * | 2020-04-14 | 2020-06-23 | Tcl华星光电技术有限公司 | Backboard unit, manufacturing method thereof and display device |
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