CN106252395B - A kind of thin film transistor (TFT) and preparation method thereof - Google Patents
A kind of thin film transistor (TFT) and preparation method thereof Download PDFInfo
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- CN106252395B CN106252395B CN201610763431.2A CN201610763431A CN106252395B CN 106252395 B CN106252395 B CN 106252395B CN 201610763431 A CN201610763431 A CN 201610763431A CN 106252395 B CN106252395 B CN 106252395B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
Abstract
The invention discloses a kind of thin film transistor (TFT)s and preparation method thereof.The thin film transistor (TFT) includes: substrate, bottom-gate, bottom-gate insulating layer, channel, etching barrier layer, source electrode, drain electrode, top gate insulating layer and top-gated pole, wherein, bottom-gate is located on substrate, bottom-gate insulating layer is located in bottom-gate, channel is located on bottom-gate insulating layer, etching barrier layer is located on channel, source electrode and drain electrode is located at the two sides of channel, top gate insulating layer is located in source electrode and drain electrode, top-gated pole is located on the gate insulating layer of top, and one of source electrode and drain electrode and top-gated pole or bottom-gate have lap.Using thin-film transistor structure provided by the invention, the upper channel and lower channel avoided in double-gate film transistor in the prior art is difficult the problem of simultaneously turning on, use thin-film transistor structure provided by the invention, it can produce relatively steady current/voltage, and then improve the display performance of AMOLED display screen.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of thin film transistor (TFT) and preparation method thereof.
Background technique
With the continuous development of field of display technology, active matrix organic light-emitting diode (AMOLED) display screen is because of tool
There are high-resolution, high brightness and the fast extensive concern by all circles of response.
Currently, most of user is by two working standards of big display screen, high-resolution alternatively display screen, and show
The quality for shielding the electron transfer capabilities of backboard directly affects brightness and resolution ratio of display screen etc., therefore, is preparing display screen back
It is the one side that user's emphasis considers that electron mobility is improved when plate.
When preparing the backboard of AMOLED display screen, in order to improve the electron transfer capabilities of backboard, the method generallyd use
There are two types of: the first, the back veneer material for selecting electron mobility relatively high, for example, using low temperature polycrystalline silicon (LTPS) or oxygen
Change semiconductor as back veneer material, it may be assumed that thin film transistor (TFT) is prepared using low-temperature polysilicon silicon technology and oxide semiconductor technology
(TFT), the backboard as AMOLED display screen.Second, the back using the thin film transistor (TFT) of double-grid structure as display screen
Plate, so that the electron transfer capabilities of backboard are improved, for example, using the structure of double-gate film transistor shown in FIG. 1, Ke Yiti
The electron transfer capabilities of AMOLED display backplane.
Using the backboard of the thin film transistor (TFT) production AMOLED display screen of double-grid structure, back can be effectively improved really
The electron transfer capabilities of plate.But in the work of double-gate film transistor, usually require that upper channel in thin film transistor (TFT) and
Lower channel simultaneously turns on, and otherwise can generate hump (Hump) effect, that is, causes the operating current generated in thin film transistor (TFT) unstable
It is fixed, and then influence the display performance of display screen.
But in practical applications, channel is not can guarantee sometimes yet even if applying voltage to top-gated pole and bottom-gate simultaneously
It is simultaneously turned on lower channel, therefore, using double-gate film transistor arrangement in the prior art, sometimes results in film crystal
The electric current of pipe output is unstable, so that the display performance of display screen is relatively low.
Summary of the invention
In view of the above problems, the present invention provides a kind of thin film transistor (TFT)s, the double grid for solving to use in the prior art
When electrode film transistor is as AMOLED backboard, due in the double-gate film transistor upper channel and lower channel can not be simultaneously
Conducting, and the problem for causing the display performance of AMOLED display screen relatively low.
The present invention provides a kind of thin film transistor (TFT), which includes:
Substrate, bottom-gate, bottom-gate insulating layer, channel, etching barrier layer, source electrode, drain electrode, top gate insulating layer and top-gated
Pole, wherein the bottom-gate is located on the substrate, and the bottom-gate insulating layer is located in the bottom-gate, the channel position
In on the bottom-gate insulating layer, the etching barrier layer is located on the channel, and the source electrode and drain electrode is located at described
The two sides of channel, the top gate insulating layer are located in the source electrode and drain electrode, and the top-gated pole is located at the top gate insulator
On layer, and one of the source electrode and drain electrode and the top-gated pole or bottom-gate have lap.
Preferably, the source electrode and drain electrode and the top-gated pole and bottom-gate have the lap to include:
The top-gated pole and the source electrode or drain electrode have lap, and the bottom-gate and the source electrode and drain electrode have weight
Folded part.
Preferably, the source electrode and drain electrode and the top-gated pole and bottom-gate have the lap to include:
The top-gated pole and the source electrode and drain electrode have lap, the bottom-gate and the source electrode or drain electrode to have weight
Folded part.
Preferably, the source electrode and drain electrode and the top-gated pole and bottom-gate have the lap to include:
The top-gated pole and the source electrode have lap and with the no lap of drain electrode, the bottom-gate and institute
Stating source electrode does not have lap and has lap with the drain electrode.
Preferably, the source electrode and drain electrode and the top-gated pole and bottom-gate have the lap to include:
The top-gated pole and the drain electrode have lap and do not have lap, the bottom-gate and institute with the source electrode
It states the no lap of drain electrode and has lap with the source electrode.
Correspondingly, the present invention also provides a kind of preparation methods of thin film transistor (TFT), this method comprises:
The first metal film is deposited on substrate, and processing is patterned to first metal film, forms bottom-gate；
Bottom-gate insulating film and channel film are sequentially depositing in the bottom-gate, and respectively to the bottom-gate insulating film and
Channel film is patterned processing, forms bottom-gate insulating layer and channel；
The deposition-etch barrier layer on the channel, the etching barrier layer is for protecting the channel；
The second metal film is deposited on the channel, and processing is patterned to second metal film, in the ditch
Source electrode and drain electrode is respectively formed on the both ends in road；
The deposition top gate insulating layer in the source electrode and drain electrode；
Third metal film is deposited on the top gate insulating layer, and processing is patterned to the third metal film,
Top-gated pole is formed, so that one of the source electrode and drain electrode and the top-gated pole or bottom-gate have lap.
Preferably, described that processing is patterned to the third metal film, top-gated pole is formed, so that the source electrode and leakage
There are lap in one of pole and the top-gated pole or bottom-gate, comprising:
Image conversion processing is carried out to the third metal film, forms top-gated pole so that the top-gated pole and the source electrode or
Drain electrode has lap, then is patterned processing to first metal film, forms bottom-gate and includes:
Processing is patterned to first metal film, forms bottom-gate so that the bottom-gate and the source electrode and
Drain electrode has lap.
Preferably, described that processing is patterned to the third metal film, top-gated pole is formed, so that the source electrode and leakage
There are lap in one of pole and the top-gated pole or bottom-gate, comprising:
Image conversion processing is carried out to the third metal film, forms top-gated pole so that the top-gated pole and the source electrode and
Drain electrode has lap, then is patterned processing to first metal film, forms bottom-gate and includes:
Processing is patterned to first metal film, forms bottom-gate so that the bottom-gate and the source electrode or
Drain electrode has lap.
Preferably, described that processing is patterned to the third metal film, top-gated pole is formed, so that the source electrode and leakage
There are lap in one of pole and the top-gated pole or bottom-gate, comprising:
Image conversion processing is carried out to the third metal film, top-gated pole is formed, so that the top-gated pole has with the source electrode
Lap and with the no lap of the drain electrode, then processing, formation bottom-gate are patterned to first metal film
Include:
Processing is patterned to first metal film, bottom-gate is formed, so that the bottom-gate does not have with the source electrode
There is lap and has lap with the drain electrode.
Preferably, described that processing is patterned to the third metal film, top-gated pole is formed, so that the source electrode and leakage
There are lap in one of pole and the top-gated pole or bottom-gate, comprising:
Processing is patterned to the third metal film, forms top-gated pole, so that the top-gated pole has with the drain electrode
Lap and there is no lap with the source electrode, then processing is patterned to first metal film, forms bottom-gate
Include:
Processing is patterned to first metal film, forms bottom-gate, so that the bottom-gate does not have with the drain electrode
There is lap and has lap with the source electrode.
The present invention provides a kind of thin film transistor (TFT), the thin film transistor (TFT) include: substrate, bottom-gate, bottom-gate insulating layer,
Channel, etching barrier layer, source electrode, drain electrode, top gate insulating layer and top-gated pole, wherein bottom-gate is located on substrate, and bottom-gate is exhausted
Edge layer is located in bottom-gate, and channel is located on bottom-gate insulating layer, and etching barrier layer is located on channel, and source electrode and drain electrode distinguishes position
It in the two sides of channel, pushes up gate insulating layer and is located in source electrode and drain electrode, top-gated pole is located on the gate insulating layer of top, and source electrode and leakage
There are lap in one of pole and top-gated pole or bottom-gate.In double-gate film crystal structure compared to the prior art, top-gated pole
There is lap with bottom-gate and source electrode and drain electrode, and in double-gate film transistor arrangement provided in the present invention, it is making
When standby top-gated pole and bottom-gate, so that one of source electrode and drain electrode and top-gated pole or bottom-gate have lap, such film is brilliant
Body structure can make upper channel and lower channel in thin film transistor (TFT) simultaneously turn on.Therefore, the film crystal that this programme provides
Pipe structure avoids in double-gate film transistor in the prior art since top-gated pole and bottom-gate have with source electrode and drain electrode
Lap uses film crystal provided by the invention so that channel and lower channel be caused to be difficult the problem of simultaneously turning on
Pipe structure can produce relatively steady current/voltage, and then improve the display performance of AMOLED display screen.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present invention, constitutes a part of the invention, this hair
Bright illustrative embodiments and their description are used to explain the present invention, and are not constituted improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is a kind of thin-film transistor structure in the prior art；
Fig. 2 is a kind of thin-film transistor structure in the prior art；
Fig. 3 is a kind of thin-film transistor structure in the prior art；
Fig. 4 is a kind of thin-film transistor structure that the embodiment of the present invention 1 provides；
Fig. 5 is a kind of thin-film transistor structure that the embodiment of the present invention 1 provides；
Fig. 6 is a kind of thin-film transistor structure that the embodiment of the present invention 1 provides；
Fig. 7 is a kind of thin-film transistor structure that the embodiment of the present invention 1 provides；
Fig. 8 is a kind of thin-film transistor structure that the embodiment of the present invention 1 provides；
Fig. 9 is a kind of flow diagram of the preparation method for thin film transistor (TFT) that the embodiment of the present invention 1 provides；
Figure 10 is a kind of thin-film transistor structure that the embodiment of the present invention 2 provides；
Figure 11 is a kind of thin-film transistor structure that the embodiment of the present invention 2 provides；
Figure 12 is a kind of thin-film transistor structure that the embodiment of the present invention 2 provides；
Figure 13 is a kind of flow diagram of the preparation method for thin film transistor (TFT) that the embodiment of the present invention 2 provides；
Figure 14 is a kind of thin-film transistor structure that the embodiment of the present invention 3 provides；
Figure 15 is a kind of thin-film transistor structure that the embodiment of the present invention 3 provides；
Figure 16 is a kind of flow diagram of the preparation method for thin film transistor (TFT) that the embodiment of the present invention 3 provides；
Figure 17 is a kind of thin-film transistor structure that the embodiment of the present invention 4 provides；
Figure 18 is a kind of thin-film transistor structure that the embodiment of the present invention 4 provides；
Figure 19 is a kind of flow diagram of the preparation method for thin film transistor (TFT) that the embodiment of the present invention 4 provides；
Figure 20 is a kind of voltage-current curve graph of thin film transistor (TFT) provided by the invention；
Figure 21 is a kind of thin-film transistor structure in the prior art.
Specific embodiment
It has been recorded in aforementioned background art, in the prior art by using two grid thin film transistor (TFT), to mention
The electron transfer capabilities of high AMOLED display backplane are as shown in Figure 1 common double-gate film transistor arrangement, the film
Transistor specifically includes: substrate 101, bottom-gate 102, bottom-gate insulating layer 103, channel 104, etching barrier layer 105, source electrode
106, drain electrode 107, top gate insulating layer 108 and top-gated pole 109, and the specific structure of channel 104 is as shown in Fig. 2, include upper ditch
Road 1041 and lower channel 1042, wherein top-gated pole 109 and source electrode 106 and drain electrode 107 have lap, and bottom-gate 102
There is lap with source electrode 106 and drain electrode 107.
Because having above-mentioned lap in double-gate film transistor in the prior art, cause to top-gated pole 109
After 102 making alive of bottom-gate, the upper channel 1041 that not can guarantee in channel 104 is simultaneously turned on lower channel 1042, to produce
Raw hump effect.As shown in figure 3, if the lower ditch 1042 in channel 104 is first connected than upper channel 1041, when to source electrode
When 106 galvanization, route of the electric current in channel 104 is " OA-AC-CD ", and then, electric current is exported from drain electrode 107；At this moment
Upper channel in channel 104 is connected again, and electric current equally can also be exported from drain electrode 107, it is clear that along route OB due to upper ditch
Road 1041 and lower channel 1042 do not simultaneously turn on, and cause the electric current exported from drain electrode 107 that can change, i.e. generation hump effect
It answers, this hump effect will affect the display performance of display screen.
In addition, as shown in Figure 1, since top-gated pole 109 and source electrode 106 and drain electrode 107 have lap, and top-gated pole
There was only relatively thin top gate insulating layer 108 between 109 and source electrode 106 and grid 107, is easy in this way in top-gated pole 109
The be overlapped part between source electrode 106 and drain electrode 107, generates parasitic capacitance, the generation of this parasitic capacitance also can be to display screen
Display performance have a negative impact.
In view of the above problems, the present invention provides a kind of thin film transistor (TFT)s, the double grid for solving to use in the prior art
When electrode film transistor is as AMOLED backboard, due in the double-gate film transistor upper channel and lower channel can not be simultaneously
Conducting, and the problem for causing the display performance of AMOLED display screen relatively low, the structure of the thin film transistor (TFT) specifically include: base
Plate, bottom-gate, bottom-gate insulating layer, channel, etching barrier layer, source electrode, drain electrode, top gate insulating layer and top-gated pole, wherein institute
It states bottom-gate to be located on the substrate, the bottom-gate insulating layer is located in the bottom-gate, and the channel is located at the bottom gate
On the insulating layer of pole, the etching barrier layer is located on the channel, and the source electrode and drain electrode is located at the two sides of the channel,
The top gate insulating layer is located in the source electrode and drain electrode, and the top-gated pole is located on the top gate insulating layer, and described
One of source electrode and drain electrode and the top-gated pole or bottom-gate have lap.
Correspondingly, the present invention also provides a kind of preparation method of thin film transistor (TFT), this method is specifically included:
The first metal film is deposited on substrate, and processing is patterned to first metal film, forms bottom-gate；In
It is sequentially depositing bottom-gate insulating film and channel film in the bottom-gate, and the bottom-gate insulating film and channel film are carried out respectively
Graphical treatment forms bottom-gate insulating layer and channel；The deposition-etch barrier layer on the channel, the etching barrier layer are used
In the protection channel；The second metal film is deposited on the channel, and processing, In are patterned to second metal film
Source electrode and drain electrode is respectively formed on the both ends of the channel；The deposition top gate insulating layer in the source electrode and drain electrode；Described
It pushes up and deposits third metal film on gate insulating layer, and processing is patterned to the third metal film, form top-gated pole, so that
One of the source electrode and drain electrode and the top-gated pole or bottom-gate have lap.
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with the specific embodiment of the invention 1,
2,3 and 4 and corresponding attached drawing technical solution of the present invention is clearly and completely described, and provided in embodiment 1,2,3 and 4
Thin film transistor (TFT) structure be based on identical inventive concept, i.e., by changing the structure of top-gated pole and/or bottom-gate so that
Upper channel and lower channel simultaneously turn on, and avoid the generation of hump effect.
Obviously, the described embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on this hair
Embodiment in bright, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, shall fall within the protection scope of the present invention.
The technical solution provided below in conjunction with attached drawing, each embodiment that the present invention will be described in detail.
Embodiment 1
The embodiment of the invention provides a kind of thin-film transistor structure, the double grid for solving to use in the prior art is very thin
When film transistor is as AMOLED backboard, due in the double-gate film transistor upper channel and lower channel can not lead simultaneously
It is logical, and the problem for causing the display performance of AMOLED display screen relatively low.Thin-film transistor structure provided by the invention such as Fig. 4
With shown in Fig. 5, which is specifically included:
Substrate, bottom-gate, bottom-gate insulating layer, channel, etching barrier layer, source electrode, drain electrode, top gate insulating layer and top-gated
Pole, wherein the bottom-gate is located on the substrate, and the bottom-gate insulating layer is located in the bottom-gate, the channel position
In on the bottom-gate insulating layer, the etching barrier layer is located on the channel, and the source electrode and drain electrode is located at described
The two sides of channel, the top gate insulating layer are located in the source electrode and drain electrode, and the top-gated pole is located at the top gate insulator
On layer, and the top-gated pole and the source electrode or drain electrode have lap, and the bottom-gate and the source electrode and drain electrode have weight
Folded part.
Specifically, thin film transistor (TFT) as shown in Figure 4, the thin film transistor (TFT) specifically include: substrate 401, bottom-gate 402,
Bottom-gate insulating layer 403, channel 404, etching barrier layer 405, source electrode 406, drain electrode 407, top gate insulating layer 408 and top-gated pole
409, wherein bottom-gate 402 is located at 401 on substrate, and bottom-gate insulating layer 403 is located at 402 in bottom-gate, and channel 404 is located at bottom
On gate insulating layer 403, etching barrier layer 405 is located on channel 404, and source electrode 406 is located at the two sides of channel with drain electrode 407
404, top gate insulating layer 408 is located on source electrode 406 and drain electrode 407, and top-gated pole 409 is located on the gate insulating layer 408 of top, and bottom
Grid 402 and source electrode 406 and drain electrode 407 have lap, and top-gated pole 409 and drain electrode 407 have lap, but and source electrode
406 do not have lap.
Specifically, thin film transistor (TFT) as shown in Figure 5, the thin film transistor (TFT) specifically include: substrate 501, bottom-gate 502,
Bottom-gate insulating layer 503, channel 504, etching barrier layer 505, source electrode 506, drain electrode 507, top gate insulating layer 508 and top-gated pole
509, wherein bottom-gate 502 is located at 501 on substrate, and bottom-gate insulating layer 503 is located at 502 in bottom-gate, and channel 504 is located at bottom
On gate insulating layer 503, etching barrier layer 505 is located on channel 504, and source electrode 506 is located at the two sides of channel with drain electrode 507
504, top gate insulating layer 508 is located on source electrode 506 and drain electrode 507, and top-gated pole 509 is located on the gate insulating layer 508 of top, and bottom
Grid 502 and source electrode 506 and drain electrode 507 have a lap, and top-gated pole 509 and source electrode 506 have a lap, and with drain electrode
507 do not have lap.
Double-gate film transistor in compared with the prior art, top-gated pole and bottom-gate have overlapping with source electrode and drain electrode
Part, and in the double-gate film transistor in Fig. 4, top-gated pole 409 and source electrode 406 do not have lap.
The beneficial effect obtained using the thin film transistor (TFT) of Fig. 4 structure is specific as follows:
As shown in fig. 6, because top-gated pole 409 and source electrode 406 do not have lap, after to 409 making alive of top-gated pole, this
When top-gated pole 409 top gate insulating layer 408 generate electric field, the field regime of generation is determined by the structure of top-gated pole 409.
Shown in specific Fig. 6, according to the shape of top-gated pole 409, the range for the electric field that gate insulating layer 408 generates on top is E~F, therefore,
The charge inducing generated on 404 surface of channel is also only distributed in E~F range, with the increase of the voltage of top-gated pole 409,
Then the upper channel EF in channel 404 is switched on；And bottom-gate 402 and source electrode 406 and drain electrode 407 have lap, such as Fig. 6 institute
402 structure of bottom-gate shown, the field regime of generation are P~Q, it can in the charge inducing that bottom-gate insulating layer 403 generates
Range be P~Q, with the increase of the voltage of bottom-gate 402, then entire lower channel will be switched in channel 404.
When to source electrode 406 plus electric current, as shown in fig. 6, from the electric current of the edge O point of source electrode 406 input channel 404, meeting
Drain electrode 407 is opened up to along lower channel, and upper channel is not because top-gated pole 409 is be overlapped with source electrode 406 between O point and E point
Part, therefore, the electric current being passed through from O point can not be directly communicated to drain electrode 407 directed along upper channel (OF).But it is passed through from O point
Electric current can along " OA-AB-BE-EF " (as shown in Figure 7), thus, eventually arrive at drain electrode 407.
For clarity, the current trend in the thin film transistor (TFT) in this detailed description Fig. 4, it is specific as shown in fig. 7,
It wherein, is " OA-AB-BC-CD " along the current trend of lower channel, the current trend along upper channel is " OA-AB-BE-EF ".
It follows that since top-gated pole 409 and source electrode 406 do not have lap, only under in channel 404
Channel is switched on, and upper channel is just switched on simultaneously, it may be assumed that has been achieved the effect that upper channel and lower channel while being switched on.
The current trend principle in current trend principle and Fig. 4 thin film transistor (TFT) in the channel 504 of Fig. 5 thin film transistor (TFT)
It is identical, to avoid repeating, just no longer the current trend principle in thin film transistor (TFT) in Fig. 5 is described in detail here.Specifically
Current trend it is as shown in Figure 8: along lower channel current trend be " OA-AD-DE ", along upper channel current trend be " OB-
BC-CD-DE”。
Similarly, because top-gated pole 509 and drain electrode 507 do not have lap, also there was only the lower channel quilt in channel 504
When conducting, upper channel can be just switched on, i.e., equally achieved the effect that upper channel and lower channel while being switched on.
In addition, the top-gated pole and the distance between source electrode and drain electrode in double-gate film transistor are usually close, and therefore, In
When thin film transistor (TFT) works, top-gated pole and the lap in source electrode and drain electrode, parasitic capacitance easy to form, the production of parasitic capacitance
It is raw, the output of electric current in thin film transistor (TFT) can equally be impacted.And the top-gated pole in thin film transistor (TFT) provided by the invention
With source electrode or the no lap of drain electrode, therefore the generation of a part of parasitic capacitance can be reduced, improve the property of thin film transistor (TFT)
Energy.
The present invention provides a kind of thin film transistor (TFT), the thin film transistor (TFT) include: substrate, bottom-gate, bottom-gate insulating layer,
Channel, source electrode, drain electrode, top gate insulating layer and top-gated pole, wherein bottom-gate is located on substrate, and bottom-gate insulating layer is located at bottom
On grid, channel is located on bottom-gate insulating layer, and source electrode and drain electrode is located at the two sides of channel, and top gate insulating layer is located at source
On pole and drain electrode, top-gated pole is located on the gate insulating layer of top, and bottom-gate and source electrode and drain electrode have a lap, top-gated pole with
Source electrode or drain electrode have lap.Top-gated pole and bottom-gate and source electrode in double-gate film crystal structure compared to the prior art
Have lap with drain electrode, and in double-gate film transistor arrangement provided in the present invention, although bottom-gate and source electrode and
Drain electrode has lap, but top-gated pole and source electrode or the no lap of drain electrode, using thin film transistor (TFT) provided by the invention
The beneficial effect obtained as AMOIED display backplane is:
1, because top-gated pole and source electrode or the no lap of drain electrode, such film crystal structure are led by lower channel
Upper channel is connected while logical.Therefore, the thin-film transistor structure that this programme provides, avoids bigrid in the prior art
Since top-gated pole and bottom-gate have lap with source electrode and drain electrode in thin film transistor (TFT), to cause channel and lower channel
It is difficult the problem of simultaneously turning on, that is, uses thin-film transistor structure provided by the invention, can produce relatively steady electric current/electricity
Pressure, and then improve the display performance of AMOLED display screen.
2, because top-gated pole and source electrode or the no lap of drain electrode, reduce a part of parasitic capacitance in thin film transistor (TFT)
Generation, improve the performance of thin film transistor (TFT), and then improve the display performance of AMOLED display screen.
Correspondingly, it the present invention also provides a kind of preparation method of thin film transistor (TFT), is equally used for solving in the prior art
When the double-gate film transistor of use is as AMOLED backboard, due to the upper channel and lower ditch in the double-gate film transistor
The problem that road can not simultaneously turn on, and cause the display performance of AMOLED display screen relatively low.The detailed process of this method is such as
Shown in Fig. 9, this method comprises:
Step 901: depositing the first metal film on substrate, and processing is patterned to first metal film, formed
Bottom-gate.
In this step, layer of metal film is deposited on substrate, metal here can be the metals such as copper, aluminium, and deposit
Mode can be vapor deposition, specifically can be thermal evaporation deposition or magnetron sputtering method etc. for metal film deposition in substrate
On.
After by the first metal film deposition on substrate, processing is patterned to the metal film, obtains bottom gate configuration.
Here the mode of graphical treatment can be chemical etching or physical etchings etc., and common chemical etching can be using acidity
Solution is chemically reacted with the first metal film, and usually can also use mask plate, so that the first metal film is etched bottom gate
The shape of pole；Common physical etchings can bombard the first metal film with using plasma etc., during bombardment
Sometimes mask plate can be also used, to obtain bottom-gate.
Step 902: bottom-gate insulating film and channel film are sequentially depositing in the bottom-gate, and respectively to the bottom-gate
Insulating film and channel film are patterned processing, form bottom-gate insulating layer and channel.
On the basis of the bottom-gate that step 901 obtains, bottom-gate insulating film and channel film (active layer) are deposited, here
Bottom-gate insulating film can be SiNx film, and channel film can be α-Si etc..And in bottom-gate after deposition bottom-gate insulating layer,
It needs to be patterned the gate insulating layer processing, obtains gate insulating layer after graphical, then, sink on gate insulating layer
Product channel film equally will also be patterned processing to the channel film, obtain channel.
Here it is identical as the graphic method that step 901 is recorded that the graphic method used can be, or there are also other
Graphic method, be not especially limited here.
Step 903: the deposition-etch barrier layer on the channel, the etching barrier layer is for protecting the channel.
In step, the deposition-etch barrier layer on channel, the etching barrier layer is for protecting the channel, specifically, because
Source electrode and drain electrode is prepared on channel two sides for step 904 needs, quarter would generally be used during preparing source electrode and drain electrode
The method of erosion, the at this moment corrosion in order to avoid channel by etching solution etc., therefore one layer of etching barrier layer is deposited on channel
Channel is avoided to be destroyed.
Step 904: the second metal film is deposited on the channel, and processing is patterned to second metal film,
Source electrode and drain electrode is respectively formed on the both ends of the channel.
In this step, the second metal film is deposited on channel, the second metal film here is also possible to copper or aluminium etc.
Conductive metal film, and the same or similar side of graphic method that patterned method here can also be mentioned with step 901
Method.
Step 905: the deposition top gate insulating layer in the source electrode and drain electrode.
This step is similar to step 902, and which is not described herein again, as shown in Fig. 4 or Fig. 5, post-depositional top gate insulating layer
It is distributed in the surface of entire device.
Step 906: depositing third metal film on the top gate insulating layer, and figure is carried out to the third metal film
Change processing forms top-gated pole, and the bottom-gate and the source electrode and drain electrode have lap, the top-gated pole and the source
Pole or drain electrode have lap.
This step and the method that step 901 obtains bottom-gate are same or similar, also just repeat no more here.
Using the preparation method of thin film transistor (TFT) provided by the invention beneficial effect obtained, with the aforementioned applications present invention
The thin film transistor (TFT) of offer beneficial effect obtained is same or similar, to avoid repeating, is no longer described in detail here.
Embodiment 2
Embodiment 2 provides second of thin-film transistor structure for the present invention, is equally used for what solution used in the prior art
When double-gate film transistor is as AMOLED backboard, due in the double-gate film transistor upper channel and lower channel can not
The problem for simultaneously turning on, and causing the display performance of AMOLED display screen relatively low.Thin film transistor (TFT) knot provided by the invention
Structure is as shown in Figure 10 and Figure 11, which specifically includes:
Substrate, bottom-gate, bottom-gate insulating layer, channel, etching barrier layer, source electrode, drain electrode, top gate insulating layer and top-gated
Pole, wherein the bottom-gate is located on the substrate, and the bottom-gate insulating layer is located in the bottom-gate, the channel position
In on the bottom-gate insulating layer, the etching barrier layer is located on the channel, and the source electrode and drain electrode is located at described
The two sides of channel, the top gate insulating layer are located in the source electrode and drain electrode, and the top-gated pole is located at the top gate insulator
On layer, and the top-gated pole and the source electrode and drain electrode have lap, the bottom-gate and the source electrode or drain electrode to have weight
Folded part.
Specifically, thin film transistor (TFT) as shown in Figure 10, the thin film transistor (TFT) specifically include: substrate 1001, bottom-gate
1002, bottom-gate insulating layer 1003, channel 1004, etching barrier layer 1005, source electrode 1006, drain electrode 1007, top gate insulating layer
1008 and top-gated pole 1009, wherein bottom-gate 1002 is located at 1001 on substrate, and bottom-gate insulating layer 1003 is located in bottom-gate
1002, channel 1004 is located on bottom-gate insulating layer 1003, and etching barrier layer 1005 is located on channel 1004, source electrode 1006 and leakage
Pole 1007 is located at the two sides 1004 of channel, and top gate insulating layer 1008 is located on source electrode 1006 and drain electrode 1007, top-gated pole
1009 are located on the gate insulating layer 1008 of top, and the top-gated pole 1009 and the source electrode 1006 and drain electrode 1007 have overlapping portion
Point, the bottom-gate 1002 does not have lap with the source electrode 1006.
Specifically, thin film transistor (TFT) as shown in figure 11, the thin film transistor (TFT) specifically include: substrate 1101, bottom-gate
1102, bottom-gate insulating layer 1103, channel 1104, etching barrier layer 1105, source electrode 1106, drain electrode 1107, top gate insulating layer
1108 and top-gated pole 1109, wherein bottom-gate 1102 is located at 1101 on substrate, and bottom-gate insulating layer 1103 is located in bottom-gate
1102, channel 1104 is located on bottom-gate insulating layer 1103, and etching barrier layer 1105 is located on channel 1104, source electrode 1106 and leakage
Pole 1107 is located at the two sides 1104 of channel, and top gate insulating layer 1108 is located on source electrode 1106 and drain electrode 1107, top-gated pole
1109 are located on the gate insulating layer 1108 of top, and top-gated pole 1109 and source electrode 1106 and drain electrode 1107 have lap, bottom gate
Pole 1102 and source electrode 1106 have lap, but do not have lap with drain electrode 1107.
Double-gate film transistor in compared with the prior art, top-gated pole and bottom-gate have overlapping with source electrode and drain electrode
Part, and in the double-gate film transistor in Figure 10, bottom-gate 1002 and source electrode 1006 do not have lap, and compared to existing
There is a double-gate film transistor in technology, in the double-gate film transistor in Figure 11, bottom-gate 1102 does not have with drain electrode 1107
There is lap.
Fig. 4 and Fig. 5 knot is used in the beneficial effect and embodiment obtained using the thin film transistor (TFT) of Figure 10 and Figure 11 structure
The beneficial effect that the thin film transistor (TFT) of structure obtains is similar, and the thin film transistor (TFT) in Fig. 4 and Fig. 5 is only the case where lower channel is connected
Under, upper channel could be connected, and the thin film transistor (TFT) in Figure 10 and Figure 11 only upper channel be connected in the case where, could incite somebody to action
Lower channel conducting.
For clarity, it is illustrated for the current trend in the thin film transistor (TFT) in Figure 10, it is specific as shown in figure 12,
It wherein, is " OA-AB-BC-CD " along the current trend of lower channel, the current trend along upper channel is " OA-AE ".According in Figure 10
Electric current moves towards principle in thin film transistor (TFT), it is easy to know the trend of the electric current in Figure 11 in thin film transistor (TFT), here just not
It is described in detail again.
The present invention provides a kind of thin film transistor (TFT), the thin film transistor (TFT) include: substrate, bottom-gate, bottom-gate insulating layer,
Channel, source electrode, drain electrode, top gate insulating layer and top-gated pole, wherein bottom-gate is located on substrate, and bottom-gate insulating layer is located at bottom
On grid, channel is located on bottom-gate insulating layer, and source electrode and drain electrode is located at the two sides of channel, and top gate insulating layer is located at source
On pole and drain electrode, top-gated pole is located on the gate insulating layer of top；And top-gated pole and source electrode and drain electrode have a lap, bottom-gate with
Source electrode or drain electrode have lap.In double-gate film crystal structure compared to the prior art, top-gated pole and bottom-gate and source
Pole and drain electrode have lap, and in double-gate film transistor arrangement provided in the present invention, although top-gated pole and source electrode
There are lap, but bottom-gate and source electrode or the no lap of drain electrode with drain electrode, top-gated pole making alive must be given in this way, made
Upper channel conducting in thin film transistor (TFT), lower channel could be connected, i.e., so that upper channel and lower ditch in thin film transistor (TFT)
Road simultaneously turns on.Therefore, the thin-film transistor structure that this programme provides, avoids double-gate film transistor in the prior art
In be all closed due to bottom-gate and bottom-gate, cause channel and lower channel to be difficult the problem of simultaneously turning on, i.e., so that film
Relatively steady current/voltage is generated in transistor, and then improves the display performance of AMOLED display screen.
Correspondingly, it the present invention also provides a kind of preparation method of thin film transistor (TFT), is equally used for solving in the prior art
When the double-gate film transistor of use is as AMOLED backboard, due to the upper channel and lower ditch in the double-gate film transistor
The problem that road can not simultaneously turn on, and cause the display performance of AMOLED display screen relatively low.The detailed process of this method is such as
Shown in Figure 13, this method comprises:
Step 1301: depositing the first metal film on substrate, and processing is patterned to first metal film, formed
Bottom-gate.
Step 1302: bottom-gate insulating film and channel film are sequentially depositing in the bottom-gate, and respectively to the bottom gate
Pole insulating film and channel film are patterned processing, form bottom-gate insulating layer and channel.
Step 1303: the deposition-etch barrier layer on the channel, the etching barrier layer is for protecting the channel.
Step 1304: the second metal film is deposited on the channel, and processing is patterned to second metal film,
Source electrode and drain electrode is respectively formed on the both ends of the channel.
Step 1305: the deposition top gate insulating layer in the source electrode and drain electrode.
Step 1306: depositing third metal film on the top gate insulating layer, and figure is carried out to the third metal film
Shapeization processing, forms top-gated pole, and the top-gated pole and the source electrode and drain electrode have a lap, the bottom-gate with it is described
Source electrode or drain electrode have lap.
The preparation method for the film crystal that the preparation method and embodiment 1 of film crystal provided in an embodiment of the present invention provide
Identical, which is not described herein again.And the preparation method beneficial effect obtained of application thin film transistor (TFT) provided by the invention, and it is preceding
It states and applies thin film transistor (TFT) provided by the invention beneficial effect obtained same or similar, to avoid repeating, here also no longer
It is described in detail.
Embodiment 3
Embodiment 3 provides the third thin-film transistor structure for the present invention, is equally used for what solution used in the prior art
When double-gate film transistor is as AMOLED backboard, due in the double-gate film transistor upper channel and lower channel can not
The problem for simultaneously turning on, and causing the display performance of AMOLED display screen relatively low.Thin film transistor (TFT) knot provided by the invention
Structure is as shown in figure 14, which specifically includes:
Substrate, bottom-gate, bottom-gate insulating layer, channel, etching barrier layer, source electrode, drain electrode, top gate insulating layer and top-gated
Pole, wherein the bottom-gate is located on the substrate, and the bottom-gate insulating layer is located in the bottom-gate, the channel position
In on the bottom-gate insulating layer, the etching barrier layer is located on the channel, and the source electrode and drain electrode is located at described
The two sides of channel, the top gate insulating layer are located in the source electrode and drain electrode, and the top-gated pole is located at the top gate insulator
On layer；And the bottom-gate and the source electrode do not have lap and have lap, the top-gated pole and institute with the drain electrode
State source electrode have lap and with the no lap of the drain electrode.
Specifically, thin film transistor (TFT) as shown in figure 14, the thin film transistor (TFT) specifically include: substrate 1401, bottom-gate
1402, bottom-gate insulating layer 1403, channel 1404, etching barrier layer 1405, source electrode 1406, drain electrode 1407, top gate insulating layer
1408 and top-gated pole 1409, wherein bottom-gate 1402 is located on substrate 1401, and bottom-gate insulating layer 1403 is located at bottom-gate 1402
On, channel 1404 is located on bottom-gate insulating layer 1403, and etching barrier layer 1405 is located on channel 1404, source electrode 1406 and drain electrode
1407 are located at the two sides 1404 of channel, and top gate insulating layer 1408 is located on source electrode 1406 and drain electrode 1407, top-gated pole
1409 are located on the gate insulating layer 1408 of top, and bottom-gate 1402 and source electrode 1406 have weight without lap and with drain electrode 1407
Folded part, top-gated pole 1409 and source electrode 1406 have lap and with drain electrode 1407 without lap.
Double-gate film transistor in compared with the prior art, top-gated pole and bottom-gate have overlapping with source electrode and drain electrode
Part, and in the double-gate film transistor in Figure 14, bottom-gate 1402 and source electrode 1406 without lap and with drain electrode
1407 have lap, and top-gated pole 1409 and source electrode 1406 have lap and with drain electrode 1407 without lap.
Thin film transistor (TFT) provided in an embodiment of the present invention, it is similar with the inventive concept of embodiment 1 and embodiment 2, it is specific logical
Figure 15 is crossed to illustrate the current trend of thin film transistor (TFT) provided by the invention, when aliving in source electrode 1406, along lower channel
Current trend be " OA-AB-BD-DF ", along upper channel current trend be " OA-AC-CE-ED-DF ".
It follows that, when only upper channel conducting, passing to electricity to source electrode 1406 in thin film transistor (TFT) provided by the invention
Stream, drain electrode 1407 does not have electric current output, because not forming current loop in channel at this time；Similarly, when only lower channel is led
When logical, pass to electric current to source electrode 1406, drain electrode 1407 equally there will not be electric current output, only when upper channel and lower channel simultaneously
When conducting, closed circuit can be being formed in channels, pass to electric current to source electrode 1406 at this time, it is defeated that drain electrode 1407 just has electric current
Out, i.e., using thin film transistor (TFT) provided in an embodiment of the present invention channel and lower channel are simultaneously turned on.The present invention provides
A kind of thin film transistor (TFT), the thin film transistor (TFT) include: substrate, bottom-gate, bottom-gate insulating layer, channel, etching barrier layer, source
Pole, drain electrode, top gate insulating layer and top-gated pole, wherein bottom-gate is located on substrate, and bottom-gate insulating layer is located in bottom-gate,
Channel is located on bottom-gate insulating layer, and etching barrier layer is located on channel, and source electrode and drain electrode is located at the two sides of channel, top-gated
Pole insulating layer is located in source electrode and drain electrode, and top-gated pole is located on the gate insulating layer of top, and top-gated pole and source electrode and drain electrode have weight
Folded part, bottom-gate and source electrode or the no lap of drain electrode.In double-gate film crystal structure compared to the prior art, top
Grid and bottom-gate and source electrode and drain electrode have lap, are shown using thin film transistor (TFT) provided by the invention as AMOIED
The beneficial effect that screen backboard obtains is:
1, when upper channel is connected and lower channel is not turned on, drain electrode does not have electric current generation when to source electrode plus electric current, and
When lower channel is connected and upper channel is connected, drain electrode equally there will not be electric current generation when to source electrode plus electric current；Only when upper ditch
When road and lower channel simultaneously turn on, drain electrode just has electric current generation when to source electrode plus electric current, that is, has reached upper and lower channel while having led
Logical effect.Therefore, the thin-film transistor structure that this programme provides, avoids in double-gate film transistor in the prior art
Since top-gated pole and bottom-gate have lap with source electrode and drain electrode, so that channel and lower channel be caused to be difficult to simultaneously turn on
The problem of, that is, thin-film transistor structure provided by the invention is used, can produce relatively steady current/voltage, and then improve
The display performance of AMOLED display screen.
2, because top-gated pole and no lap that drains, reduce the production of a part of parasitic capacitance in thin film transistor (TFT)
It is raw, the performance of thin film transistor (TFT) is improved, and then improve the display performance of AMOLED display screen.
Correspondingly, it the present invention also provides a kind of preparation method of thin film transistor (TFT), is equally used for solving in the prior art
When the double-gate film transistor of use is as AMOLED backboard, due to the upper channel and lower ditch in the double-gate film transistor
The problem that road can not simultaneously turn on, and cause the display performance of AMOLED display screen relatively low.The detailed process of this method is such as
Shown in Figure 16, this method comprises:
Step 1601: depositing the first metal film on substrate, and processing is patterned to first metal film, formed
Bottom-gate.
Step 1602: bottom-gate insulating film and channel film are sequentially depositing in the bottom-gate, and respectively to the bottom gate
Pole insulating film and channel film are patterned processing, form bottom-gate insulating layer and channel.
Step 1603: the deposition-etch barrier layer on the channel, the etching barrier layer is for protecting the channel.
Step 1604: the second metal film is deposited on the channel, and processing is patterned to second metal film,
Source electrode and drain electrode is respectively formed on the both ends of the channel.
Step 1605: the deposition top gate insulating layer in the source electrode and drain electrode.
Step 1606: depositing third metal film on the top gate insulating layer, and figure is carried out to the third metal film
Shapeization processing forms top-gated pole, and the bottom-gate and the source electrode do not have lap and have lap with the drain electrode,
The top-gated pole and the source electrode have lap and with the no lap of drain electrode.
The preparation method for the film crystal that the preparation method and embodiment 1 of film crystal provided in an embodiment of the present invention provide
Identical, which is not described herein again.And the preparation method beneficial effect obtained of application thin film transistor (TFT) provided by the invention, and it is preceding
It states and applies thin film transistor (TFT) provided by the invention beneficial effect obtained same or similar, to avoid repeating, here also no longer
It is described in detail.
Embodiment 4
Embodiment 4 provides the 4th kind of thin-film transistor structure for the present invention, is equally used for what solution used in the prior art
When double-gate film transistor is as AMOLED backboard, due in the double-gate film transistor upper channel and lower channel can not
The problem for simultaneously turning on, and causing the display performance of AMOLED display screen relatively low.Thin film transistor (TFT) knot provided by the invention
Structure is as shown in figure 17, which specifically includes:
Substrate, bottom-gate, bottom-gate insulating layer, channel, etching barrier layer, source electrode, drain electrode, top gate insulating layer and top-gated
Pole, wherein the bottom-gate is located on the substrate, and the bottom-gate insulating layer is located in the bottom-gate, the channel position
In on the bottom-gate insulating layer, the etching barrier layer is located on the channel, and the source electrode and drain electrode is located at described
The two sides of channel, the top gate insulating layer are located in the source electrode and drain electrode, and the top-gated pole is located at the top gate insulator
On layer, and the bottom-gate and the no lap of the drain electrode and there are lap, the top-gated pole and institute with the source electrode
Stating drain electrode has lap and does not have lap with the source electrode.
Specifically, thin film transistor (TFT) as shown in figure 17, the thin film transistor (TFT) specifically include: substrate 1701, bottom-gate
1702, bottom-gate insulating layer 1703, channel 1704, etching barrier layer 1705, source electrode 1706, drain electrode 1707, top gate insulating layer
1708 and top-gated pole 1709, wherein bottom-gate 1702 is located at 1701 on substrate, and bottom-gate insulating layer 1703 is located in bottom-gate
1702, channel 1704 is located on bottom-gate insulating layer 1703, and the etching barrier layer 1705 is located at 1704 on the channel, source electrode
1706 are located at the two sides 1704 of channel with drain electrode 1707, and top gate insulating layer 1708 is located at source electrode 1706 and drain electrode 1707
On, top-gated pole 1709 is located on the gate insulating layer 1708 of top, and bottom-gate 1702 and drain electrode 1707 do not have lap and and source
There is lap in pole 1706, and top-gated pole 1709 and drain electrode 1707 have lap and with source electrode 1706 without lap.
Double-gate film transistor in compared with the prior art, top-gated pole and bottom-gate have overlapping with source electrode and drain electrode
Part, and in the double-gate film transistor in Figure 17, bottom-gate 1702 and drain electrode 1707 do not have lap and and source electrode
1706 have lap, and top-gated pole 1709 and drain electrode 1707 have lap and with source electrode 1706 without lap.
Thin film transistor (TFT) provided in an embodiment of the present invention, it is similar with the inventive concept of embodiment 3, for Figure 18
The current trend of bright thin film transistor (TFT) provided in an embodiment of the present invention, when aliving in source electrode 1706, along the electricity of lower channel
It flows away to for " OA-AB-BC-CD ", the current trend along upper channel is " OA-AB-BE-EF ".
The present invention provides a kind of thin film transistor (TFT), the thin film transistor (TFT) include: substrate, bottom-gate, bottom-gate insulating layer,
Channel, source electrode, drain electrode, top gate insulating layer and top-gated pole, wherein bottom-gate is located on substrate, and bottom-gate insulating layer is located at bottom
On grid, channel is located on bottom-gate insulating layer, and etching barrier layer is located on channel, and source electrode and drain electrode is located at the two of channel
Side, top gate insulating layer are located in source electrode and drain electrode, and top-gated pole is located on the gate insulating layer of top, and bottom-gate and drain electrode are without weight
Folded partially and with source electrode to have lap, top-gated pole and drain electrode have lap and do not have lap with source electrode.Using this hair
The thin film transistor (TFT) of bright offer is as the beneficial effect that AMOIED display backplane obtains:
1, when upper channel is connected and lower channel is not turned on, drain electrode does not have electric current generation when to source electrode plus electric current, and
When lower channel is connected and upper channel is connected, drain electrode equally there will not be electric current generation when to source electrode plus electric current；Only when upper ditch
When road and lower channel simultaneously turn on, drain electrode just has electric current generation when to source electrode plus electric current, that is, has reached upper and lower channel while having led
Logical effect.Therefore, the thin-film transistor structure that this programme provides, avoids in double-gate film transistor in the prior art
Since top-gated pole and bottom-gate have lap with source electrode and drain electrode, so that channel and lower channel be caused to be difficult to simultaneously turn on
The problem of, that is, thin-film transistor structure provided by the invention is used, can produce relatively steady current/voltage, and then improve
The display performance of AMOLED display screen.
2, because top-gated pole and source electrode do not have lap, reduce the production of a part of parasitic capacitance in thin film transistor (TFT)
It is raw, the performance of thin film transistor (TFT) is improved, and then improve the display performance of AMOLED display screen.
Correspondingly, it the present invention also provides a kind of preparation method of thin film transistor (TFT), is equally used for solving in the prior art
When the double-gate film transistor of use is as AMOLED backboard, due to the upper channel and lower ditch in the double-gate film transistor
The problem that road can not simultaneously turn on, and cause the display performance of AMOLED display screen relatively low.The detailed process of this method is such as
Shown in Figure 19, this method comprises:
Step 1901: depositing the first metal film on substrate, and processing is patterned to first metal film, formed
Bottom-gate.
Step 1902: bottom-gate insulating film and channel film are sequentially depositing in the bottom-gate, and respectively to the bottom gate
Pole insulating film and channel film are patterned processing, form bottom-gate insulating layer and channel.
Step 1903: the deposition-etch barrier layer on the channel, the etching barrier layer is for protecting the channel.
Step 1904: the second metal film is deposited on the channel, and processing is patterned to second metal film,
Source electrode and drain electrode is respectively formed on the both ends of the channel.
Step 1905: the deposition top gate insulating layer in the source electrode and drain electrode.
Step 1906: depositing third metal film on the top gate insulating layer, and figure is carried out to the third metal film
Shapeization processing, forms top-gated pole, and the bottom-gate and the no lap of the drain electrode and has lap with the source electrode,
The top-gated pole and the drain electrode have lap and do not have lap with the source electrode.
The preparation method for the film crystal that the preparation method and embodiment 1 of film crystal provided in an embodiment of the present invention provide
Identical, which is not described herein again.And the preparation method beneficial effect obtained of application thin film transistor (TFT) provided by the invention, and it is preceding
It states and applies thin film transistor (TFT) provided by the invention beneficial effect obtained same or similar, to avoid repeating, here also no longer
It is described in detail.
Figure 20 is the electricity of the voltage-current curve of thin film transistor (TFT) provided by the invention and the thin film transistor (TFT) of ordinary construction
The comparison diagram of piezo-electric flow curve, the corresponding grid voltage of abscissa in reference axis, ordinate are the electric current that drain electrode generates.And
Thin film transistor (TFT) of the invention in Figure 20 is using embodiment 1, embodiment 2, implements any film crystal in 3 and embodiment 4
Pipe structure, specifically, thin film transistor (TFT) in implementation 1, embodiment 2, embodiment 3 and the embodiment 4 obtained by many experiments
Voltage-current curve, it is roughly the same with the voltage-current curve of thin film transistor (TFT) of the invention in Figure 20.
Here the thin film transistor (TFT) of ordinary construction is as shown in figure 21, specifically includes: substrate 2101, bottom-gate 2102, bottom
Gate insulating layer 2103, channel 2104, etching barrier layer 2105, source electrode 2106 and drain electrode 2107, and Figure 21 is in the prior art
The thin-film transistor structure of common bottom-gate.
As shown in Figure 21, when grid voltage is greater than 2V, the electric current that the corresponding drain electrode of thin film transistor (TFT) of the invention generates is big
Generate 5 times or so of electric current of the thin film transistor (TFT) drain electrode of about ordinary construction, and according to can be calculated: film of the invention is brilliant
The electron mobility of body pipe is about 46.0cm2/ VS, the electron mobility of the thin film transistor (TFT) of ordinary construction, which is greater than, is
19.3cm2/ VS, i.e., the electron mobility of thin film transistor (TFT) of the invention are about the thin film transistor (TFT) electron transfer of ordinary construction
2.38 times of rate.
Accordingly, with respect to bottom gate thin film transistor structure in the prior art, using thin film transistor (TFT) provided by the invention
The electron transfer capabilities in transistor can be improved in structure.And as shown in Figure 20, the electric piezo-electric of thin film transistor (TFT) of the invention
The shape of flow curve is roughly the same with the shape of the voltage-current curve of bottom gate thin film transistor structure, illustrates using this hair
The thin-film transistor structure of bright offer, there is no bring other undesirable effects to thin film transistor (TFT).
The above description is only an embodiment of the present invention, is not intended to restrict the invention.For those skilled in the art
For, the invention may be variously modified and varied.All any modifications made within the spirit and principles of the present invention are equal
Replacement, improvement etc., should be included within scope of the presently claimed invention.
Claims (2)
1. a kind of thin film transistor (TFT) characterized by comprising substrate, bottom-gate, bottom-gate insulating layer, channel, etch stopper
Layer, source electrode, drain electrode, top gate insulating layer and top-gated pole, wherein the bottom-gate is located on the substrate, and the bottom-gate is exhausted
Edge layer is located in the bottom-gate, and the channel is located on the bottom-gate insulating layer, and the etching barrier layer is located at the ditch
On road, the source electrode and drain electrode is located at the two sides of the channel, and the top gate insulating layer is located at the source electrode and drain electrode
On, the top-gated pole is located on the top gate insulating layer, wherein
The top-gated pole and the source electrode have lap and with the no lap of drain electrode, the bottom-gate and the source
Extremely there is lap without lap and with the drain electrode；Either
The top-gated pole and the drain electrode have lap and do not have lap, the bottom-gate and the leakage with the source electrode
Extremely there is lap without lap and with the source electrode.
2. a kind of preparation method of thin film transistor (TFT), which is characterized in that this method comprises:
The first metal film is deposited on substrate, and processing is patterned to first metal film, forms bottom-gate；
Bottom-gate insulating film and channel film are sequentially depositing in the bottom-gate, and respectively to the bottom-gate insulating film and channel
Film is patterned processing, forms bottom-gate insulating layer and channel；
The deposition-etch barrier layer on the channel, the etching barrier layer is for protecting the channel；
The second metal film is deposited on the channel, and processing is patterned to second metal film, in the channel
Source electrode and drain electrode is respectively formed on both ends；
The deposition top gate insulating layer in the source electrode and drain electrode；
Third metal film is deposited on the top gate insulating layer, and processing is patterned to the third metal film, is formed
Top-gated pole,
So that the top-gated pole and the source electrode have lap and with the no lap of drain electrode, the bottom-gate with
The source electrode does not have lap and has lap with the drain electrode；Either
So that the top-gated pole and the drain electrode have lap and do not have lap, the bottom-gate and institute with the source electrode
It states the no lap of drain electrode and has lap with the source electrode.
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| CN107255710B (en) * | 2017-06-01 | 2019-07-09 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | Multichannel micro-fluidic fluorescence detection device and method |
| JP2021504952A (en) * | 2017-11-27 | 2021-02-15 | シェンジェン ロイオル テクノロジーズ カンパニー リミテッドＳｈｅｎｚｈｅｎ Ｒｏｙｏｌｅ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｃｏ．， Ｌｔｄ． | Manufacturing method of TFT substrate, ESD protection circuit and TFT substrate |
| CN108122932B (en) * | 2017-12-26 | 2020-06-05 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and preparation method |
| US10593807B2 (en) | 2017-12-26 | 2020-03-17 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Array substrate and fabricating method thereof |
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