CN105006487A - Top gate self-aligned metal oxide semiconductor thin-film transistor and preparation method thereof - Google Patents
Top gate self-aligned metal oxide semiconductor thin-film transistor and preparation method thereof Download PDFInfo
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- CN105006487A CN105006487A CN201510411880.6A CN201510411880A CN105006487A CN 105006487 A CN105006487 A CN 105006487A CN 201510411880 A CN201510411880 A CN 201510411880A CN 105006487 A CN105006487 A CN 105006487A
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- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 30
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 239000010409 thin film Substances 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 39
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 16
- 238000002161 passivation Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229910052786 argon Inorganic materials 0.000 claims abstract description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 11
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000001257 hydrogen Substances 0.000 claims abstract description 7
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 7
- 238000000137 annealing Methods 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 23
- 238000005516 engineering process Methods 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 13
- 238000000605 extraction Methods 0.000 claims description 11
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 10
- 238000001259 photo etching Methods 0.000 claims description 9
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052733 gallium Inorganic materials 0.000 claims description 7
- 229910052738 indium Inorganic materials 0.000 claims description 7
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000011787 zinc oxide Substances 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 238000009832 plasma treatment Methods 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000000992 sputter etching Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 60
- 238000001020 plasma etching Methods 0.000 description 4
- 229920001621 AMOLED Polymers 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a top gate self-aligned metal oxide semiconductor thin-film transistor and a preparation method thereof. The method comprises the steps of: after an active region is deposited and etched on a substrate, performing argon plasma processing on the whole active region, and forming a high-conductivity layer on the upper surface of the active region; and after a gate electrode is deposited and etched and a gate medium is etched, forming a self-aligned source region and a drain region. Argon plasma process can effectively reduce the surface resistances and contact resistances of the source region and the drain region; furthermore a thin high-conductivity layer is introduced on the upper surface of a channel region for forming a double-layer conductive channel structure; and for the source region and the drain region, the conductivity of the whole source region and the drain region are improved and the resistances of the source region and the drain region are reduced through a plasma processing process, a quick annealing process and a reacting ion etching gate medium layer over-etching process after a gate medium pattern is defined, or through a method of performing hydrogen doping on the source region and the drain region according to the annealing process after a hydrogen-containing silicon nitride passivation layer is deposited.
Description
Technical field
The invention belongs to semiconductor integrated circuit manufacture and flat display field, be specifically related to a kind of top grid autoregistration metal oxide semiconductor films transistor and preparation method thereof.
Background technology
Flat panel display industry is as the electronics and information industry with development potentiality, and development in recent years is rapid.Active liquid crystal display (AMLCD) industry of its main flow has become one of pillar industry in electronics and information industry.Thin-film transistor (TFT) is the core devices of flat panel display, and in AMLCD display, TFT is usually used as address selection switch device.Amorphous silicon hydride (a-Si:H) TFT is the TFT technology be most widely used, but is limited to its low carrier mobility, and this technology can not meet AMLCD flat panel display of future generation to the requirement of high definition image quality.On the other hand, utilize OLED (OLED) self-luminous characteristic to show (AMOLED) as the Activematric OLED of flat panel display and receive increasing concern.TFT has vital effect in AMOLED display pixel circuits, and it is not only as address selection switch, and simultaneously also for OLED luminescent device provides drive current, this feature makes AMOLED have higher requirement to TFT output current and mobility.At present, the TFT mainstream technology being widely studied the generation flat panel display that faces down is low temperature polycrystalline silicon (LTPS) technology and the metal oxide TFT that is representative with indium gallium zinc oxide (IGZO).In LTPS technology, the feature due to polycrystalline silicon material makes its large-area uniformity not good, and main application fields is small-medium size display screen.And metal oxide TFT is regarded as the major candidate of flat panel display of future generation because of its many advantage.
Many advantages is had: semiconductor material with wide forbidden band characteristic makes it adapt to the requirement of all-transparent display with the TFT technology that IGZO TFT is representative; Lower technological temperature can meet use glass substrate or plastic flexible substrate; Large-area uniformity adapts to the requirement of large-size screen monitors display; High carrier mobility can meet the requirement etc. of flat panel display high definition image quality of future generation.The research of current most IGZO TFT all adopts bottom gate stacked device architecture, its weak point has: that introduces in back of the body channel etching (BCE) technique can impact device property excessively quarter, etch-protecting layer (ESL) technology is used to address this problem, but also makes process complexity improve simultaneously; To the punctual crossover region problem introduced, the existence of crossover region limits the application of bottom grating structure when scaled down, its application in high speed circuit of the crossover region capacitance limits simultaneously introduced.
Form the top gate device structure of source-drain area with self-registered technology and effectively can solve the problem that bottom-gate device structure brings.In addition, the gate dielectric layer above raceway groove and gate electrode effectively cover above raceway groove, can play the effect of protective layer to raceway groove.
Summary of the invention
The object of the invention is to provide a kind of top grid autoregistration metal oxide semiconductor films transistor and preparation method thereof.The method effectively improves device performance.
Technical scheme of the present invention is as follows:
A kind of top grid autoregistration metal oxide semiconductor films transistor, include active layer, gate dielectric layer, gate electrode, source-drain electrode, described active layer is positioned at substrate, and gate dielectric layer is positioned at active layer, and gate electrode is positioned on gate dielectric layer.It is characterized in that active layer is metal-oxide semiconductor (MOS), comprise channel region, source region and drain region, source region and drain region lay respectively at left side and the right side of channel region; Before deposit gate dielectric layer, carry out argon (Ar) plasma treatment to whole active layer, after process, active layer upper surface forms the high conductivity layer of 5 ~ 15 nanometers.
The present invention improves active layer upper surface layer conductivity, after deposit, etching gate dielectric layer figure, forms self-aligned source region and drain region.Meanwhile, thin high conductivity layer is introduced in argon plasma process over the channel region surface, forms bilayer conductive channel structure; For source region and drain region, further using plasma process, rapid thermal annealing, reactive ion dry etching gate dielectric layer carving technology can be crossed after defining gate medium figure, or by deposit hydrogeneous silicon nitride passivation post growth annealing, source region and drain region are carried out to the method for hydrogen doping, to improve the conductivity in whole source region and drain region, reduce source region and drain region resistance further.Its preparation process comprises:
(1) at Grown layer of metal oxide semiconductor thin-film, photoetching, etching is adopted, or stripping technology, be formed with active layer district;
(2) argon plasma process is carried out to whole active layer district;
(3) at active layer deposit one deck gate dielectric layer;
(4) deposit one deck conductive layer on gate dielectric layer, adopt photoetching, etching, or stripping technology defines gate electrode figure;
(5) take gate electrode as barrier etch gate dielectric layer, form gate medium figure, below gate medium figure, active layer is channel region, and the gate medium left and right sides is respectively source region and drain region;
(6) enter transistor and prepare postchannel process, comprise deposit passivation layer, opening contact hole, deposit conductive layer, definition conducting layer figure formation extraction electrode.
In step (1), substrate is silicon chip, glass substrate or plastic flexible substrate.
In step (1), active layer metal oxide depositing technics is the magnetron sputtering technique growth adopting ceramic target, its material is indium gallium zinc oxide (IGZO), or zinc oxide (ZnO) and doping system thereof comprise one or several combinations in III or the IV race elements such as tin (Sn), indium (In), gallium (Ga), aluminium (Al); Pattern definition method be etching or stripping technology in one.
In step (2), argon plasma is adopted to carry out plasma treatment to whole active layer district, improve active layer upper surface conductivity, this plasma-treating technology order can be adjusted to before photoetching in step (1), etching or stripping technology be formed with source region figure.
In step (3), gate dielectric material be one in silicon dioxide, silicon nitride or both mutually combine, using plasma strengthens the deposit of chemical vapor deposition (PECVD) technique; Or one or more the combination in high dielectric constant insulating material, adopts magnetron sputtering or the deposit of atomic layer deposition (ALD) technique.
In step (4), gate electrode conductive film is the one in the non-transparent metals such as Al, Ti, Cr, or the one in the transparent conductive film such as ITO, AZO, InO, adopts the method deposit of direct current or rf magnetron sputtering.
In step (5), in order to improve the conductivity in source region and drain region further, can adopt grid medium etching, graphically complete after can carry out argon plasma process again to reduce the resistance in source region and drain region further.
In step (6), transistor postchannel process comprises deposit passivation layer, opening contact hole, deposit conductive layer, definition conducting layer figure formation extraction electrode, wherein, passivation layer can be one in silicon dioxide, silicon nitride or both combine mutually, adopt pecvd process deposit, or be one or more the combination in high dielectric constant insulating material, adopt magnetron sputtering or the deposit of ALD technique; Membrane of conducting layer is the one in the transparent conductive films such as a kind of or ITO, AZO, InO in the non-transparent metals such as Al, Ti, Cr, adopts the method deposit of direct current or rf magnetron sputtering.
In step (6), when adopting silicon nitride as passivation layer, before opening contact hole, the hydrogen trap in silicon nitride can be made to enter device source region and drain region by annealing, thus hydrogen doping is realized to source region and drain region, to reduce the resistance in source region and drain region further.
Advantage of the present invention:
Film crystal tube preparation method of the present invention can realize the oxide thin film transistor pushing up grid self-alignment structure, key is to carry out argon plasma process to the metal oxide in whole active area, improve whole active area upper surface conductivity, its advantage is mainly reflected in following two aspects: first, after to gate electrode and grid medium etching, form self aligned source region and drain region, what effectively prevent between grid and source/drain region is overlapping, inhibits the parasitic capacitance that crossover region is introduced; Secondly, argon plasma process makes channel region upper surface form thin high conductivity layer, form bilayer conductive channel structure, high conductivity layer provides low resistance conductive path in device ON state service area, significantly improve ON state service area electric current, this high connductivity layer thickness is little simultaneously, and in OFF state service area, carriers effectively exhausts, OFF state service area electric current can not enlarge markedly, thus effectively improves device property; Again, this device is the coplanar homojunction structure of top grid, and compared with bottom gate stacked structure, source/drain region resistance effectively reduces; In addition, after self-aligned source region and drain region are formed, the conductivity in source region and drain region can be improved by second time plasma treatment, hydrogeneous silicon nitride passivation annealing process further, thus fall further low source/drain region resistance.
Accompanying drawing explanation
Fig. 1 is a kind of generalized section of pushing up grid autoregistration metal oxide semiconductor films transistor and preparation method thereof of the present invention;
Fig. 2 (a) ~ (f) sequentially show a kind of embodiment main technological steps pushing up grid autoregistration metal oxide semiconductor films transistor and preparation method thereof of the present invention.
1-glass substrate in above-mentioned figure; 2-active area metal-oxide film; Active layer upper surface high conductivity layer after the process of 3-argon plasma; 4-gate medium; 5-gate electrode; 6-passivation layer; 7-gate electrode extraction electrode; 8-source region extraction electrode; 9-drain region extraction electrode.
Embodiment
Below in conjunction with Figure of description, by example, the present invention will be further described.
One top grid autoregistration metal oxide semiconductor films transistor of the present invention is formed in glass substrate, as depicted in figs. 1 and 2.This thin-film transistor includes active layer, gate dielectric layer, gate electrode, passivation layer, extraction electrode, described active layer is positioned at substrate, gate dielectric layer is positioned at active layer, gate electrode is positioned on gate dielectric layer, passivation layer is positioned on source region, drain region and gate electrode, and extraction electrode is positioned on passivation layer.
An a kind of embodiment of pushing up grid autoregistration metal oxide semiconductor films transistor and preparation method thereof of the present invention, by shown in Fig. 2 (a) to Fig. 2 (f), comprises the following steps:
(1) in glass substrate 1, use the IGZO metal oxide semiconductor films of rf magnetron sputtering deposit one deck about 50 nanometer thickness.Then photoetching, etching are formed with source region 2, as shown in Fig. 2 (a);
(2) in plasma enhanced CVD (PECVD) system, radio-frequency power is 20 ~ 60 watts, argon plasma process is carried out to whole active area, the high conductivity layer 3 of one deck 5 ~ 15 nanometer is formed, as shown in Fig. 2 (b) at whole active layer upper surface;
(3) using plasma strengthens the silica membrane that chemical vapor deposition (PECVD) deposit a layer thickness is about 150 nanometers;
(4) adopt rf magnetron sputtering to grow the transparent conductive metal oxide ito thin film of one deck about 110 nanometer thickness, then photoetching and etching form gate electrode 5;
(5) with gate electrode 5 for barrier layer, adopt reactive ion etching (RIE) etching silicon dioxide film, obtain gate dielectric layer 4, as shown in Fig. 2 (c), spend quarter, hydrogen doping is carried out to source region and drain region, reduce the resistance in source region and drain region;
(6) using plasma strengthens the silicon dioxide that chemical vapor deposition (PECVD) deposit a layer thickness is about 200 nanometers, as passivation layer 6, as shown in Fig. 2 (d);
(7) carry out photoetching, then adopt reactive ion etching (RIE) method to etch grid, source electrode, drain contact hole, as shown in Fig. 2 (e);
(8) rf magnetron sputtering is adopted to grow the transparent conductive metal oxide ito thin film of one deck about 110 nanometer thickness, then photoetching and etching form thin-film transistor gate extraction electrode 7, source electrode extraction electrode 8, drain electrode extraction electrode 9, as shown in Fig. 2 (f).
It is finally noted that, the object publicizing and implementing mode is to help to understand the present invention further, but it will be appreciated by those skilled in the art that: without departing from the spirit and scope of the invention and the appended claims, various substitutions and modifications are all possible.Therefore, the present invention should not be limited to the content disclosed in embodiment, and the scope that the scope of protection of present invention defines with claims is as the criterion.
Claims (10)
1. a top grid autoregistration metal oxide semiconductor films transistor, include active layer, gate dielectric layer, gate electrode, source-drain electrode, described active layer is positioned at substrate, gate dielectric layer is positioned at active layer, gate electrode is positioned on gate dielectric layer, it is characterized in that active layer is metal-oxide semiconductor (MOS), comprise channel region, source region and drain region, source region and drain region lay respectively at left side and the right side of channel region; Before deposit gate dielectric layer, argon plasma process is carried out to whole active layer, after plasma treatment, form high conductivity layer at active layer upper surface.
2. top grid autoregistration metal oxide semiconductor films transistor as claimed in claim 1, it is characterized in that, the thickness range of described high conductivity layer is 5 ~ 15 nanometers.
3. top grid autoregistration metal oxide semiconductor films transistor as claimed in claim 1, it is characterized in that, active layer metal oxide materials is indium gallium zinc oxide, or zinc oxide and doping system thereof comprise one or several combinations in III or the IV race elements such as tin, indium, gallium, aluminium.
4. top grid autoregistration metal oxide semiconductor films transistor as claimed in claim 1, it is characterized in that, gate dielectric material is one or more the combination in silicon dioxide, silicon nitride or high dielectric constant insulating material.
5. top grid autoregistration metal oxide semiconductor films transistor as claimed in claim 1, it is characterized in that, gate electrode conductive film is the one in a kind of or ITO, AZO, InO transparent conductive film in Al, Ti, Cr non-transparent metals.
6. the preparation method of top grid autoregistration metal oxide semiconductor films transistor as claimed in claim 1, its step comprises:
1) at Grown layer of metal oxide semiconductor thin-film, photoetching, etching is adopted, or stripping technology, remove the region beyond active area, be formed with active layer district;
2) argon plasma process is carried out to whole active layer district;
3) at active layer deposit one deck gate dielectric layer;
4) deposit one deck conductive layer on gate dielectric layer, adopt photoetching, etching, or stripping technology defines gate electrode figure;
5) take gate electrode as barrier etch gate dielectric layer, form gate medium figure, below gate medium figure, active layer is channel region, and the gate medium left and right sides is respectively source region and drain region;
6) enter transistor and prepare postchannel process, comprise deposit passivation layer, opening contact hole, deposit conductive layer, definition conducting layer figure formation extraction electrode.
7. preparation method as claimed in claim 6, it is characterized in that, described substrate is silicon chip, glass substrate or plastic flexible substrate.
8. preparation method as claimed in claim 6, it is characterized in that, described active layer metal oxide depositing technics is the magnetron sputtering technique growth adopting ceramic target, material is indium gallium zinc oxide or zinc oxide and doping system thereof, comprises one or several combinations in III or the IV race elements such as tin, indium, gallium, aluminium.
9. preparation method as claimed in claim 6, is characterized in that, in step 5) in grid medium etching, graphically complete after carry out argon plasma process again.
10. preparation method as claimed in claim 6, it is characterized in that, step 6) in passivation layer be one in silicon dioxide, silicon nitride or both mutually combine, adopt pecvd process deposit, or be one or more the combination in high dielectric constant insulating material, adopt magnetron sputtering or the deposit of ALD technique, when adopting silicon nitride as passivation layer, before opening contact hole, the hydrogen trap in silicon nitride is made to enter device source region and drain region by annealing.
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| CN105575819A (en) * | 2016-02-26 | 2016-05-11 | 华南理工大学 | Metal oxide thin film transistor with top gate structure and manufacturing method thereof |
| CN105977306A (en) * | 2016-06-21 | 2016-09-28 | 北京大学深圳研究生院 | Self-aligned thin-film transistor and preparation method thereof |
| CN106158978A (en) * | 2016-07-08 | 2016-11-23 | 武汉华星光电技术有限公司 | Thin film transistor (TFT), array base palte and preparation method thereof |
| CN107706242A (en) * | 2016-08-09 | 2018-02-16 | 元太科技工业股份有限公司 | Transistor and its manufacture method |
| CN107799604A (en) * | 2017-09-05 | 2018-03-13 | 华南理工大学 | A kind of autoregistration top-gated indium tin zinc oxide film transistor and its manufacture method |
| CN107808826A (en) * | 2017-10-26 | 2018-03-16 | 京东方科技集团股份有限公司 | A kind of preparation method of bottom emitting top-gated self-aligned thin film transistor |
| CN109314133A (en) * | 2016-06-30 | 2019-02-05 | 英特尔公司 | Integrated circuit die with rear road transistor |
| CN113497064A (en) * | 2021-07-23 | 2021-10-12 | 合肥维信诺科技有限公司 | Preparation method of array substrate and array substrate |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105575819A (en) * | 2016-02-26 | 2016-05-11 | 华南理工大学 | Metal oxide thin film transistor with top gate structure and manufacturing method thereof |
| CN105977306A (en) * | 2016-06-21 | 2016-09-28 | 北京大学深圳研究生院 | Self-aligned thin-film transistor and preparation method thereof |
| CN109314133A (en) * | 2016-06-30 | 2019-02-05 | 英特尔公司 | Integrated circuit die with rear road transistor |
| CN106158978A (en) * | 2016-07-08 | 2016-11-23 | 武汉华星光电技术有限公司 | Thin film transistor (TFT), array base palte and preparation method thereof |
| CN107706242A (en) * | 2016-08-09 | 2018-02-16 | 元太科技工业股份有限公司 | Transistor and its manufacture method |
| CN107706242B (en) * | 2016-08-09 | 2021-03-12 | 元太科技工业股份有限公司 | Transistor and method of manufacturing the same |
| CN107799604A (en) * | 2017-09-05 | 2018-03-13 | 华南理工大学 | A kind of autoregistration top-gated indium tin zinc oxide film transistor and its manufacture method |
| WO2019047336A1 (en) * | 2017-09-05 | 2019-03-14 | 华南理工大学 | Self-aligned top gate itzo thin film transistor and manufacturing method therefor |
| CN107799604B (en) * | 2017-09-05 | 2019-10-11 | 华南理工大学 | A kind of autoregistration top-gated indium tin zinc oxide film transistor and its manufacturing method |
| US11049881B2 (en) | 2017-09-05 | 2021-06-29 | South China University Of Technology | Method for manufacturing a top-gate self-aligned indium-tin-zinc oxide thin-film transistor |
| CN107808826A (en) * | 2017-10-26 | 2018-03-16 | 京东方科技集团股份有限公司 | A kind of preparation method of bottom emitting top-gated self-aligned thin film transistor |
| CN113497064A (en) * | 2021-07-23 | 2021-10-12 | 合肥维信诺科技有限公司 | Preparation method of array substrate and array substrate |
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