CN103311128A - Self-aligning metal oxide thin film transistor and manufacturing method thereof - Google Patents
Self-aligning metal oxide thin film transistor and manufacturing method thereof Download PDFInfo
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- CN103311128A CN103311128A CN2013102337439A CN201310233743A CN103311128A CN 103311128 A CN103311128 A CN 103311128A CN 2013102337439 A CN2013102337439 A CN 2013102337439A CN 201310233743 A CN201310233743 A CN 201310233743A CN 103311128 A CN103311128 A CN 103311128A
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Abstract
The invention provides a self-aligning metal oxide thin film transistor and a manufacturing method thereof. The method includes depositing a metal oxide semiconductor layer, a gate dielectric layer and a conducting thin film on a substrate and photoetching for imaging, spin-coating a dopant layer on the surface of a device, performing heat treatment to enable doping atoms in the spin-coated dopant layer to be diffused into a lower-layer material. The graphical gate electrode and the graphic gate dielectric exist, so that the doping atoms can only be diffused into metal oxide semiconductor areas on two sides of a channel area, doping of the metal oxide semiconductor on two sides of a channel is realized, resistivity of the metal oxide semiconductor is greatly lowered, and a self-aligned source-drain area is formed. The spin-coated dopant layer can also serve as a passivating layer of the device and is combined with subsequent processes like photoetching of contact holes and leading-out of electrodes and a wiring layer to manufacture a complete TFT (thin film transistor) device. The metal oxide thin film transistor prepared by the method has a self-aligning structure and is simple in process and compatible with large-area substrate process.
Description
Technical field
The present invention relates to a kind of thin-film transistor and preparation method thereof, relate in particular to a kind of top grid self-alignment structure metal oxide thin-film transistor and preparation method thereof.
Background technology
As a kind MOS device, thin-film transistor (TFTs:thin-film transistors) is the core devices of flat panel display always, and it is mainly used in the control of panel display board image element circuit switch, image element circuit drives and the display floater peripheral drive circuit.In addition, thin-film transistor also is widely studied fields such as being applied to transducer, memory, processor.Thin-film transistor can be divided into a variety of according to the difference of active layer material, comprise traditional silicon-based film transistor, metal oxide thin-film transistor (Oxide TFTs) and OTFT (Organic TFTs) etc.In various different active layer material thin-film transistors, now by the industrial circle large-area applications mainly be the silicon-based film transistor that is risen the eighties in 20th century, such as hydrogenation non crystal silicon film transistor (a-Si:H TFTs) and polycrystalline SiTFT (poly-Si TFTs).But, development along with Display Technique, the shortcoming of these silicon-based film transistors becomes increasingly conspicuous, and is mainly manifested in the transistorized low mobility of hydrogenation non crystal silicon film and poor stability, and the device property consistency is poor on polycrystalline SiTFT complex process, the expensive and large tracts of land substrate.These all will seriously limit the application aspect following large scale, high-resolution, high frame frequency, transparent flexible demonstration of hydrogenation non crystal silicon film transistor and polycrystalline SiTFT.
The metal oxide thin-film transistor technology is a kind of new technology of rising in recent years, and compared to aforesaid silicon-based film transistor technology, it has obvious advantage.Be mainly manifested in high mobility, good device performance consistency, technique is simple, technological temperature is low, good stability, visible light transmissivity is high.Metal oxide thin-film transistor adopts be metal oxide semiconductor material as raceway groove, these materials mainly are Zinc oxide-base and indium oxide sill, comprise zinc oxide (ZnO), indium oxide (In
2O
3), aluminium-doped zinc oxide (AZO), boron doping zinc-oxide (BZO), magnesium doping zinc-oxide (MZO), indium oxide gallium zinc (IGZO), hafnium indium zinc oxygen (HIZO), gallium oxide zinc (GZO), tin indium oxide (ITO), tin oxide (SnO
2), stannous oxide (SnO), cuprous oxide (Cu
2O) etc.
In the thin-film transistor preparation technology and structure of routine, larger overlapping amount is arranged between gate electrode and the source-drain electrode, realize high device performance and work simplification with this.But, large parasitic capacitance is introduced in overlapping meeting large between gate electrode and the source leakage, and in the circuit working process take thin-film transistor as switching component, these parasitic capacitances can be coupled to drain electrode with the clock signal on the gate electrode, affect circuit working, i.e. clock feed-through effect; Large parasitic capacitance also can reduce operating rate and the cut-off frequency f of device simultaneously
TSelf-registered technology just in time can reduce the overlapping amount between the leakage of thin-film transistor gate electrode and source, reduces parasitic capacitance.
Compared to bottom grating structure, top gate structure is more easily realized autoregistration.How to realize that leak in the low-resistivity source is the key of top grid self-alignment structure always.The method that has been seen in the realization self-alignment structure thin-film transistor of report has a lot of disadvantages, as: and traditional large tracts of land panel production line compatibility issue, self-alignment structure stability problem, preparation efficiency and Cost Problems etc.So self-alignment structure thin-film transistor preparation technology and characteristic thereof have very high research and using value.
Summary of the invention
The object of the present invention is to provide a kind of new autoregistration metal oxide thin-film transistor and preparation method thereof, thin-film transistor source and drain areas and the channel region of this preparation method's preparation use the same layer metal oxide semiconductor material, by a sputter and graphical formation, source and drain areas is then take patterned gate electrode and gate medium as mask, by spin coating mix (SOD) mix to reduce resistivity.This preparation method can guarantee to form self-alignment structure between device gate electrode and the source-drain electrode, simultaneously simple, the preparation that can apply to the large-area displays panel of technique.
The metal oxide thin-film transistor of the inventive method made is formed on glass substrate or the flexible substrate, comprises a channel region, a source region, a drain region, a gate dielectric layer, a gate electrode, a passivation layer and contact electrode.Described channel region is metal oxide semiconductor material, is positioned on the substrate, and source region and drain region be metal-oxide film and be positioned at the channel region both sides, and gate medium is positioned on the raceway groove, and gate electrode is positioned on the gate medium.Passivation layer is positioned at whole device surface, and contact electrode is drawn each electrode of device.
The transistorized manufacture method of said film may further comprise the steps:
1) active area generates step: deposit layer of metal oxide semiconductor layer on substrate;
2) the graphical step of active area: photoetching and etching metal oxide semiconductor layer are formed with the source region figure;
3) gate dielectric layer generates step: generate the insulated gate dielectric layer that covers on the described metal oxide semiconductor layer at substrate;
4) gate electrode generates step: deposit one deck grid conducting layer on described insulated gate dielectric layer;
5) the graphical step of gate electrode and gate medium: photoetching and etching grid conductive layer and insulated gate dielectric layer form respectively gate electrode and gate medium figure;
6) source and drain areas treatment step: spin coating one deck spin coating dopant (SOD) layer on whole substrate, then it is heat-treated, impel the foreign atom in the dopant layer to diffuse into not by in the metal-oxide semiconductor (MOS) of the channel region both sides that gate electrode covered, reduce its resistivity, form the low resistance source drain region;
7) carry out the subsequent technique of transistor fabrication: comprise device passivation, opening contact hole and formation contact electrode etc.
In the above-mentioned manufacture method, can deposit one deck resilient coating on the employed substrate of step 1), this resilient coating is generally silica and/or silicon nitride, is formed by plasma body reinforced chemical vapor deposition method.
In the above-mentioned manufacture method, the metal oxide semiconductor layer of step 1) institute deposit is the metal oxide semiconductor films of amorphous, crystallite or polycrystalline, is generally zinc oxide (ZnO), indium oxide (In
2O
3), aluminium-doped zinc oxide (AZO), boron doping zinc-oxide (BZO), magnesium doping zinc-oxide (MZO), indium oxide gallium zinc (IGZO), hafnium indium zinc oxygen (HIZO), gallium oxide zinc (GZO), tin indium oxide (ITO) etc.Adopt direct current or radiofrequency magnetron sputtering technology or reactive sputtering technology growth.Use ceramic target or metal/alloy target, Chun Du＞=99.99%.
In the above-mentioned manufacture method, the insulating medium layer of step 3) institute deposit can be silicon nitride and/or silica etc., is formed by plasma enhanced CVD (PECVD) method; Also can for aluminium oxide and, the high dielectric constants such as tantalum oxide or hafnium oxide, formed by atomic layer deposition, rf magnetron sputtering or reactive sputtering method; Also can be organic media, be formed by spin coating method.Insulating medium layer can be the above-mentioned individual layer gate dielectric layer that waits material to form, and also can be the composite gate dielectric layer that several dielectric materials form.
In the above-mentioned manufacture method, the conductive layer of step 4) institute deposit is generally metal or nonmetal conductive film etc., and metal generally comprises molybdenum, chromium, titanium, aluminium etc., is formed by magnetron sputtering, electron beam evaporation or thermal evaporation method; Nonmetal conductive film generally comprises the nesa coatings such as tin indium oxide (ITO), aluminium-doped zinc oxide (AZO), boron doping zinc-oxide (BZO), is formed by methods such as magnetron sputtering or optical coatings; Can be the homogenous material conductive layer, also can be the composite conducting layer that bilayer or multilayer conductive material form.
In the above-mentioned manufacture method, the described heat treatment of step 6) is carried out under 150 ℃-600 ℃ temperature; The spin coating dopant layer that adopts (SOD) for containing the spin coating reagent of the foreign atom that can reduce metal-oxide semiconductor (MOS) resistivity, can be boron spin coating dopant layer, phosphorus spin coating dopant layer, arsenic spin coating dopant layer etc.
In the above-mentioned manufacture method, the contact electrode of step 7) institute deposit is generally metal or nonmetal conductive film, and metal generally comprises molybdenum, chromium, titanium, aluminium etc., is formed by magnetron sputtering, electron beam evaporation or thermal evaporation method; Nonmetal conductive film generally comprises the nesa coatings such as tin indium oxide (ITO), aluminium-doped zinc oxide (AZO), boron doping zinc-oxide (BZO), is formed by methods such as magnetron sputtering or optical coatings; Can be monolayer material, also can be the composite conducting layer material that bilayer or multilayer conductive material form.
In an embodiment of the present invention, after the spin coating doping heat treatment, the spin coating dopant layer is directly served as the passivation layer of device, the subsequent step such as then carry out that opening contact hole and electrode are drawn;
In an embodiment of the present invention, after the spin coating doping heat treatment, remove the spin coating dopant layer, growth of passivation layer then, the subsequent step such as then carry out that opening contact hole and electrode are drawn;
In an embodiment of the present invention, that channel region adopts is thick, and (that the high resistivity metal oxide semiconductor layer of 10nm～200nm) adds is thin, and (≤15nm) the double-deck raceway groove of low resistivity metal oxide layer can improve ON state current and the mobility of prepared device;
What in an embodiment of the present invention, gate dielectric layer adopted is the composite gate dielectric layer that the double hyer insulation medium consists of;
In the thin-film transistor of traditional structure, have larger overlappingly between leak in gate electrode and source, this is overlapping can introduce large parasitic capacitance, reduces the operating rate of device.In by the circuit of thin-film transistor as switch element, this parasitic capacitance also can cause clock feed-through effect, affects speed and the reliability of circuit, increases the complexity of circuit.Reduce the adverse effect that parasitic capacitance is brought than starting with from circuit design, self-alignment structure can be on structure and the technique be omitted living electric capacity with these grid and source and is significantly reduced.Compared to bottom grating structure, top gate structure is easy to realize self-aligned thin film transistor more.The key of autoregistration top-grate structure thin film transistor preparation is the formation technique that low resistance source is leaked.The method that has proposed, all incompatible with large tracts of land panel preparation technology such as plasma treatment, Implantation etc., and cost is high, efficient is low.The hydrogen doping method is easy to diffusion because the hydrogen atom atomic number is little, and can there be thermal stability problems in device.So a kind of and large tracts of land panel process compatible and technique autoregistration top gate structure device preparation technology simple, low-cost, good stability seems particularly important.
The metal oxide thin-film transistor of the present invention preparation is take patterned gate electrode and gate medium as mask, by be rich in the spin coating dopant layer of foreign atom in the surperficial spin coating of device, the foreign atom that orders about in the spin coating dopant layer by heat treatment does not diffuse into by the leakage metal-oxide semiconductor (MOS) zone, source of gate electrode and gate medium covering, and realization is mixed to source and drain areas and reduced the purpose of its resistivity.According to said method its advantage of metal oxide thin-film transistor of preparation is as follows:
The self-alignment structure that forms can effectively reduce the overlap capacitance between gate electrode and the source leakage; Foreign atom is the atomic number atoms large than hydrogen such as boron, phosphorus, arsenic, and its better heat stability in metal oxide semiconductor layer is therefore the device thermal stability of preparation is also better; Spin coating method is easy to realize at the large tracts of land substrate, so the method and large-area displays panel production line compatibility and technique is simple, cost is low, high efficiency; After the spin coating doping process was finished, the spin coating dopant layer can directly be served as the passivation layer of device and need not be removed, and technique further is simplified.Because source and drain areas and channel region adopt the same layer metal oxide semiconductor material, by a sputter and graphical formation, heat treatment process itself also is the reprocessing annealing process of device, so technique is simple.
Description of drawings
Fig. 1～7 figure show the main manufacturing process steps of the thin-film transistor in the embodiment of the invention one successively, wherein:
Fig. 1 has illustrated the formation processing step of metal oxide semiconductor layer;
Fig. 2 has illustrated the graphical processing step in active area island;
Fig. 3 has illustrated gate medium and gate electrode layer deposition process steps;
Fig. 4 has illustrated gate electrode and the graphical processing step of gate medium;
Fig. 5 has illustrated the spin coating dopant layer to form and the Technology for Heating Processing step;
Fig. 6 has illustrated contact hole to form processing step;
Fig. 7 has illustrated contact electrode to form processing step.
Fig. 8-15 shows the main manufacturing process steps of the thin-film transistor in the embodiment of the invention two successively, wherein:
Fig. 8 has illustrated the formation processing step of metal oxide semiconductor layer;
Fig. 9 has illustrated the graphical processing step in active area island;
Figure 10 has illustrated gate medium and gate electrode layer deposition process steps;
Figure 11 has illustrated gate electrode and the graphical processing step of gate medium;
Figure 12 has illustrated the spin coating dopant layer to form and the Technology for Heating Processing step;
Figure 13 has illustrated passivation layer to form processing step;
Figure 14 has illustrated contact hole to form processing step;
Figure 15 has illustrated contact electrode to form processing step.
Figure 16-22 shows the main manufacturing process steps of the thin-film transistor in the embodiment of the invention three successively, wherein:
Figure 16 has illustrated the double-level-metal oxide skin(coating) to form processing step;
Figure 17 has illustrated the graphical processing step in active area island;
Figure 18 has illustrated gate dielectric layer and gate electrode layer deposition process steps;
Figure 19 has illustrated gate electrode and the graphical processing step of gate medium;
Figure 20 has illustrated the spin coating dopant layer to form and the Technology for Heating Processing step;
Figure 21 has illustrated contact hole to form processing step;
Figure 22 has illustrated contact electrode to form processing step.
Figure 23～30 figure show the main manufacturing process steps of the thin-film transistor in the embodiment of the invention four successively, wherein:
Figure 23 has illustrated metal oxide semiconductor layer to form processing step;
Figure 24 has illustrated the graphical processing step of active area;
Figure 25 has illustrated double layer gate dielectric layer and gate electrode layer deposition process steps;
Figure 26 has illustrated gate electrode and the graphical processing step of gate medium;
Figure 27 has illustrated the spin coating dopant layer to form and the Technology for Heating Processing step;
Figure 28 has illustrated the passivation layer deposition process steps;
Figure 29 has illustrated contact hole to form processing step;
Figure 30 has illustrated contact electrode to form processing step.
Number in the figure explanation: 1-substrate, 2-metal oxide semiconductor films, 3-photoresist, 4-gate medium 1, the 5-gate electrode, 6-photoresist, 7-spin coating dopant layer, 8,9-source region and drain region, 10,11,12 contact holes, 13,14, the 15-contact electrode, the 16-passivation layer, the metal-oxide film of 17-low-resistivity, 18-gate medium 2.
Embodiment
Below by specific embodiment, and cooperate accompanying drawing, the present invention is described in detail.
Thin-film transistor manufacture method provided by the invention is characterised in that by spin coating one deck spin coating dopant layer (Spin-On Dopants:SOD) on the top gate structure device surface, the foreign atom that heat treatment is ordered about in the spin coating dopant layer is diffused in the source leakage metal oxide semiconductor layer of lower floor, reduces its resistivity to form the source and drain areas of low-resistance.Simultaneously, be take patterned gate electrode and gate dielectric layer as mask in the spin coating doping process, so leaking, gate electrode and source can realize autoregistration.This transistor is formed on glass substrate or the flexible substrate, can deposit one deck resilient coating on the substrate.Total comprises a gate electrode, a gate dielectric layer, a metal-oxide semiconductor (MOS) channel region, a source region, a drain region, a passivation layer and contact electrode.The zone that metal oxide semiconductor layer is positioned under gate electrode and the gate medium is channel region; The channel region two side areas is respectively source region and drain region.
Metal oxide semiconductor layer is deposited on glass substrate or the flexible substrate, and it is generally Zinc oxide-base or indium oxide based film material, is formed by magnetically controlled sputter method or reactive sputtering method, and thickness is 10nm～200nm.Gate medium can be the dielectrics such as silica, silicon nitride, aluminium oxide, hafnium oxide and organic media, is formed by methods such as plasma enhanced CVD (PECVD), atomic layer deposition (ALD), magnetron sputtering, reactive sputtering or spin coatings; Insulating medium layer can be the above-mentioned individual layer gate dielectric layer that waits material to form, and also can be the composite gate dielectric layer that several dielectric materials form; The thickness of gate medium is generally 50nm～400nm.Gate electrode is metal or non-metallic conducting material, such as metal materials such as molybdenum, chromium, titanium, aluminium, the nesa coatings such as tin indium oxide (ITO), aluminium-doped zinc oxide (AZO) and boron doping zinc-oxide (BZO), it can be the homogenous material conductive layer, it also can be the composite conducting layer that bilayer or multilayer conductive material form, its thickness is generally 50nm～300nm, is formed by magnetron sputtering, electron beam evaporation or thermal evaporation etc.Spin coating dopant layer thickness is generally 100nm～5000nm, is formed by spin-coating method.Contact electrode is generally metal or non-metallic conducting material, is generally molybdenum, aluminium, titanium and tin indium oxide (ITO) etc., can be the homogenous material conductive layer, also can be the composite conducting layer that bilayer or multilayer conductive material form; Thickness is generally 100nm～300nm, is formed by magnetron sputtering, electron beam evaporation or thermal evaporation etc.
By reference to the accompanying drawings the present invention is described in further detail below by embodiment.
Embodiment one:
One instantiation of the manufacture method of thin-film transistor of the present invention such as Fig. 1 may further comprise the steps to shown in Figure 7:
As shown in Figure 1, used substrate 1 is glass substrate, Grown by Magnetron Sputtering one deck 60nm metal-oxide semiconductor (MOS) indium oxide gallium zinc (IGZO) film 2 on substrate.
As shown in Figure 2, spin coating photoresist 3, photoetching and etching oxidation indium gallium zinc film 2; Adopt the ultrasonic removal photoresist 3 of acetone.
As shown in Figure 3, the silicon oxide film 4 of using plasma enhancing chemical vapor deposition (PECVD) method deposit one deck 200nm on patterned indium oxide gallium zinc film 2; Then adopt again the metal molybdenum film 5 of Grown by Magnetron Sputtering one deck 150nm.
As shown in Figure 4, spin coating photoresist 6, photoetching and etching molybdenum electrode, gate silicon oxide medium; Adopt the ultrasonic removal photoresist 6 of acetone.
As shown in Figure 5, adopt spin-coating method spin coating one BDC1-2000 boron spin coating dopant layer (Spin-On Dopants) 7; Device is placed heat treatment under 350 ℃ of conditions, impel the foreign atom in the spin coating dopant layer to diffuse into not by gate electrode and gate medium capping oxidation indium gallium zinc zone 8,9, reach this region doping to reduce the purpose of resistivity.
As shown in Figure 6, photoetching and etching form the contact hole 10,11,12 of each electrode.
As shown in Figure 7, with tin indium oxide (ITO) film of magnetically controlled sputter method deposit one deck 200nm, then photoetching and etching form the contact electrode 13,14,15 of each electrode of thin-film transistor.
Embodiment two:
Another instantiation of the manufacture method of thin-film transistor of the present invention such as Fig. 8 may further comprise the steps to shown in Figure 15:
As shown in Figure 8, used substrate 1 is glass substrate, Grown by Magnetron Sputtering one deck 80nm metal-oxide semiconductor (MOS) indium oxide gallium zinc (IGZO) film 2 on substrate.
As shown in Figure 9, spin coating photoresist 3, photoetching and etching oxidation indium gallium zinc film 2; Adopt the ultrasonic removal photoresist 3 of acetone.
As shown in figure 10, the silicon oxide film 4 of using plasma enhancing chemical vapor deposition (PECVD) method deposit one deck 300nm on patterned indium oxide gallium zinc film 2; Then adopt again the metal molybdenum film 5 of Grown by Magnetron Sputtering one deck 300nm.
As shown in figure 11, spin coating photoresist 6, photoetching and etching molybdenum electrode, gate silicon oxide medium; Adopt the ultrasonic removal photoresist 6 of acetone.
As shown in figure 12, adopt spin-coating method spin coating one BDC1-2000 boron spin coating dopant layer (Spin-On Dopants) 7; Device is placed heat treatment under 300 ℃ of conditions, impel the foreign atom in the spin coating dopant layer to diffuse into not by gate electrode and gate medium capping oxidation indium gallium zinc zone 8,9, reach this region doping to reduce the purpose of resistivity.
As shown in figure 13, remove spin coating dopant layer 7, using plasma strengthens chemical gaseous phase electrode method deposit 200nm silica passivation layer 16.
As shown in figure 14, photoetching and etching form the contact hole 10,11,12 of each electrode.
As shown in figure 15, with tin indium oxide (ITO) film of magnetically controlled sputter method deposit one deck 300nm, then photoetching and etching form the contact electrode 13,14,15 of each electrode of thin-film transistor.
Embodiment three:
Another instantiation of the manufacture method of thin-film transistor of the present invention such as Figure 16 may further comprise the steps to shown in Figure 22:
As shown in figure 16, used substrate 1 is flexible substrate, metal-oxide semiconductor (MOS) indium oxide gallium zinc (IGZO) film 2 of the high resistivity of Grown by Magnetron Sputtering one deck 40nm on substrate; Follow the again indium tin oxide films of the low-resistivity of Grown by Magnetron Sputtering one deck 5nm (ITO) 17.
As shown in figure 17, spin coating photoresist 3, photoetching and etching oxidation indium gallium zinc film 2, indium tin oxide films 17; Adopt the ultrasonic removal photoresist 3 of acetone.
As shown in figure 18, on patterned indium tin oxide films 17, adopt the aluminum oxide film 4 of atomic layer deposition (ALD) method deposit one deck 100nm; Then adopt again the metal molybdenum film 5 of Grown by Magnetron Sputtering one deck 50nm.
As shown in figure 19, spin coating photoresist 6, photoetching and etching molybdenum electrode, gate silicon oxide medium; Adopt the ultrasonic removal photoresist 7 of acetone.
As shown in figure 20, adopt spin-coating method spin coating one BDC1-2000 boron spin coating dopant layer (Spin-On Dopants) 7; Device is placed heat treatment under 150 ℃ of conditions, impel the foreign atom in the spin coating dopant layer to diffuse into not by gate electrode and gate medium capping oxidation indium gallium zinc zone 8,9, reach this region doping to reduce the purpose of resistivity.
As shown in figure 21, photoetching and etching form the contact hole 10,11,12 of each electrode.
As shown in figure 22, with tin indium oxide (ITO) film of magnetically controlled sputter method deposit one deck 100nm, then photoetching and etching form the contact electrode 13,14,15 of each electrode of thin-film transistor.
Embodiment four:
Another instantiation of the manufacture method of thin-film transistor of the present invention such as Figure 23 may further comprise the steps to shown in Figure 30:
As shown in figure 23, used substrate 1 is glass substrate, metal-oxide semiconductor (MOS) indium oxide gallium zinc (IGZO) film 2 of the high resistivity of Grown by Magnetron Sputtering one deck 60nm on substrate.
As shown in figure 24, spin coating photoresist 3, photoetching and etching oxidation indium gallium zinc film 2 adopt the ultrasonic removal photoresist 3 of acetone.
As shown in figure 25, the silicon oxide film 4 of using plasma enhancing chemical vapor deposition (PECVD) method deposit one deck 50nm on patterned indium tin oxide films 2; Then using plasma strengthens the silicon nitride film 18 of chemical vapor deposition (PECVD) method deposit one deck 150nm; Then adopt again the metal molybdenum film 5 of Grown by Magnetron Sputtering one deck 150nm.The adding of dielectric layer of high dielectric constant silicon nitride film 18 can the Effective Raise gate electrode to the control ability of raceway groove.
As shown in figure 26, spin coating photoresist 6, photoetching and etching molybdenum electrode, silica and nitride gate medium; Adopt the ultrasonic removal photoresist 6 of acetone.
As shown in figure 27, adopt spin-coating method spin coating one PDC1-2000 phosphorus spin coating dopant layer (Spin-On Dopants) 7; Device is placed heat treatment under 600 ℃ of conditions, impel the foreign atom in the spin coating dopant layer to diffuse into not by gate electrode and gate medium capping oxidation indium gallium zinc zone 8,9, reach this region doping to reduce the purpose of resistivity.
As shown in figure 28, remove the spin coating dopant layer, using plasma strengthens chemical vapor deposition (PECVD) method deposit one deck passivation layer 16, and this passivation layer is silica and/or silicon nitride.
As shown in figure 29, photoetching and etching form the contact hole 10,11,12 of each electrode.
As shown in figure 30, with tin indium oxide (ITO) film of magnetically controlled sputter method deposit one deck 200nm, then photoetching and etching form the contact electrode 13,14,15 of each electrode of thin-film transistor.
Above content is in conjunction with concrete execution mode further description made for the present invention, can not assert that implementation of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deductions, variation, modification or replacement, therefore, the present invention should not be limited to embodiment and the disclosed content of accompanying drawing.
Claims (10)
1. the manufacture method of an autoregistration metal oxide thin-film transistor, its step comprises:
1) depositing metal oxide semiconductor layer on substrate;
2) the described metal oxide semiconductor layer of photoetching and etching is formed with the source region figure;
3) generate the insulated gate dielectric layer that covers on the described metal oxide semiconductor layer at substrate;
4) deposit one deck grid conducting layer on described insulated gate dielectric layer;
5) the described grid conducting layer of photoetching and etching and insulated gate dielectric layer form respectively gate electrode and gate medium figure;
6) then spin coating one deck spin coating dopant layer on whole substrate heat-treats it, and the foreign atom in the spin coating dopant layer is diffused into not by in the metal-oxide semiconductor (MOS) of the channel region both sides that gate electrode covered, and forms the low resistance source drain region;
7) carry out the subsequent technique of transistor fabrication.
2. the method for claim 1, it is characterized in that: the described heat treatment of step 6) is carried out under 150 ℃-600 ℃ temperature.
3. method as claimed in claim 1 or 2 is characterized in that, described spin coating dopant layer is a kind of in following: boron spin coating doped layer, phosphorus spin coating doped layer, arsenic spin coating doped layer.
4. method as claimed in claim 1 or 2, it is characterized in that: described substrate is glass substrate or flexible substrate.
5. method as claimed in claim 1 or 2 is characterized in that: step 1) elder generation deposit one deck resilient coating on substrate, and then the described metal oxide semiconductor layer of deposit.
6. method as claimed in claim 1 or 2, it is characterized in that: described metal oxide semiconductor layer is Zinc oxide-base or the indium oxide sill of amorphous, crystallite or polycrystalline structure, adopts magnetically controlled sputter method or the described metal oxide semiconductor layer of reactive sputtering method deposit.
7. method as claimed in claim 1 or 2, it is characterized in that: the described metal oxide semiconductor layer of step 1) is thick high resistivity metal oxide semiconductor layer, the low resistivity metal oxide layer that deposit one deck is thin thereon forms double-deck raceway groove, and then the described double-deck raceway groove of photoetching and etching forms the active area figure.
8. method as claimed in claim 1 or 2, it is characterized in that: the material of described insulated gate dielectric layer is for by a kind of individual layer gate medium that forms in the high dielectric constants such as silicon nitride, silica, organic media and aluminium oxide or hafnium oxide, or the gate stack that is formed by bilayer or multilayered medium material; Adopt the described insulated gate dielectric layer of one or more deposits in the following method: plasma enhanced CVD, atomic layer deposition, magnetron sputtering, reactive sputtering and spin coating.
9. method as claimed in claim 1 or 2 is characterized in that: utilize the spin coating dopant layer that forms in the step 6) to serve as device passivation layer; Perhaps on the spin coating dopant layer again deposit one deck passivation layer form layer compound passivation; Perhaps the spin coating dopant layer that forms in the step 6) is removed, in addition deposit one deck passivation layer.
10. the metal oxide thin-film transistor that each described method is made in 9 according to claim 1.
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| CN104362098A (en) * | 2014-11-21 | 2015-02-18 | 昆山工研院新型平板显示技术中心有限公司 | Oxide thin-film transistor and preparation method thereof |
| CN106356306A (en) * | 2016-11-14 | 2017-01-25 | 深圳市华星光电技术有限公司 | Top gate type thin film transistor and production method thereof |
| WO2017202115A1 (en) * | 2016-05-26 | 2017-11-30 | 京东方科技集团股份有限公司 | Thin film transistor and manufacturing method therefor, base substrate and display device |
| CN107623040A (en) * | 2017-09-05 | 2018-01-23 | 华南理工大学 | A kind of indium gallium zinc oxide thin film transistor (TFT) and its manufacture method |
| CN107799604A (en) * | 2017-09-05 | 2018-03-13 | 华南理工大学 | A kind of autoregistration top-gated indium tin zinc oxide film transistor and its manufacture method |
| US10032924B2 (en) | 2014-03-31 | 2018-07-24 | The Hong Kong University Of Science And Technology | Metal oxide thin film transistor with channel, source and drain regions respectively capped with covers of different gas permeability |
| US10504939B2 (en) | 2017-02-21 | 2019-12-10 | The Hong Kong University Of Science And Technology | Integration of silicon thin-film transistors and metal-oxide thin film transistors |
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| CN112635332A (en) * | 2019-10-08 | 2021-04-09 | 东南大学 | IGZO thin film transistor and method for manufacturing the same |
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| CN103715267A (en) * | 2013-12-30 | 2014-04-09 | 京东方科技集团股份有限公司 | TFT, TFT array substrate, manufacturing method of TFT array substrate and display device |
| US10032924B2 (en) | 2014-03-31 | 2018-07-24 | The Hong Kong University Of Science And Technology | Metal oxide thin film transistor with channel, source and drain regions respectively capped with covers of different gas permeability |
| CN104362098A (en) * | 2014-11-21 | 2015-02-18 | 昆山工研院新型平板显示技术中心有限公司 | Oxide thin-film transistor and preparation method thereof |
| CN104362098B (en) * | 2014-11-21 | 2017-06-16 | 昆山工研院新型平板显示技术中心有限公司 | Oxide thin film transistor and preparation method thereof |
| WO2017202115A1 (en) * | 2016-05-26 | 2017-11-30 | 京东方科技集团股份有限公司 | Thin film transistor and manufacturing method therefor, base substrate and display device |
| CN106356306A (en) * | 2016-11-14 | 2017-01-25 | 深圳市华星光电技术有限公司 | Top gate type thin film transistor and production method thereof |
| US10504939B2 (en) | 2017-02-21 | 2019-12-10 | The Hong Kong University Of Science And Technology | Integration of silicon thin-film transistors and metal-oxide thin film transistors |
| WO2019047336A1 (en) * | 2017-09-05 | 2019-03-14 | 华南理工大学 | Self-aligned top gate itzo thin film transistor and manufacturing method therefor |
| CN107799604A (en) * | 2017-09-05 | 2018-03-13 | 华南理工大学 | A kind of autoregistration top-gated indium tin zinc oxide film transistor and its manufacture method |
| CN107799604B (en) * | 2017-09-05 | 2019-10-11 | 华南理工大学 | A kind of autoregistration top-gated indium tin zinc oxide film transistor and its manufacturing method |
| CN107623040A (en) * | 2017-09-05 | 2018-01-23 | 华南理工大学 | A kind of indium gallium zinc oxide thin film transistor (TFT) and its manufacture method |
| US11049881B2 (en) | 2017-09-05 | 2021-06-29 | South China University Of Technology | Method for manufacturing a top-gate self-aligned indium-tin-zinc oxide thin-film transistor |
| CN110660864A (en) * | 2018-06-29 | 2020-01-07 | 山东大学苏州研究院 | High-frequency semiconductor thin film field effect transistor and preparation method thereof |
| CN112635332A (en) * | 2019-10-08 | 2021-04-09 | 东南大学 | IGZO thin film transistor and method for manufacturing the same |
| WO2021068672A1 (en) * | 2019-10-08 | 2021-04-15 | 东南大学 | Igzo thin-film transistor and method for manufacturing same |
| CN115954273A (en) * | 2023-03-13 | 2023-04-11 | 山东科技大学 | Gas-phase iodine-doped metal oxide thin film transistor and preparation method thereof |
| CN115954273B (en) * | 2023-03-13 | 2023-06-16 | 山东科技大学 | Gas-phase iodine doped metal oxide thin film transistor and preparation method thereof |
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