CN105405893B - A kind of planar split dual gate thin film transistor (TFT) and preparation method thereof - Google Patents
A kind of planar split dual gate thin film transistor (TFT) and preparation method thereof Download PDFInfo
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- CN105405893B CN105405893B CN201510976409.1A CN201510976409A CN105405893B CN 105405893 B CN105405893 B CN 105405893B CN 201510976409 A CN201510976409 A CN 201510976409A CN 105405893 B CN105405893 B CN 105405893B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- Thin Film Transistor (AREA)
Abstract
The invention belongs to technical field of semiconductors, a kind of planar split dual gate thin film transistor (TFT) and preparation method thereof is disclosed.The method is：(1) insulating dielectric materials are deposited on substrate as transition zone；(2) conductive film is deposited on transition zone, is lithographically formed two gate electrodes；(3) insulation film is deposited on transition zone and gate electrode forms insulation gate dielectric layer；(4) deposition film on insulation gate dielectric layer, forms semiconductor active layer；(5) the spin coating photoresist layer on semiconductor active layer is lithographically formed the contact hole of source/drain electrode；(6) conductive film is deposited on contact hole and photoresist, stripping forms source electrode and drain electrode；(7) it makes annealing treatment.The transistor of the present invention can make TFT devices show different output and transfer characteristic by adjusting the bias of two grids, and two grids can be used as control gate and signal grid to use, so that circuit is simplified, effectively expand the application range of TFT simultaneously.
Description
Technical field
The invention belongs to technical field of semiconductors, more particularly to a kind of planar split dual gate thin-film transistor structure and its system
Preparation Method.
Background technology
In recent years, thin film transistor (TFT) (TFT) is applied to FPD, integrated sensor, intelligent recognition because more and more extensive
Card and the numerous areas such as integrated circuit and widely paid close attention to and studied.To meet more application demands, TFT devices must
Must have good device performance (high mobility, low off-state current, high switching current ratio, low threshold voltage, low subthreshold swing
Deng) and higher stability, reliability.For many years, the improvement for surrounding device performance has developed and a variety of can be used for the half of TFT
Conductor thin film material, mainly including non-crystalline silicon, polysilicon, using pentacene as the Organic micromolecular semiconductor material of representative, with poly-
Thiophene-based is the organic polymer semiconductor material of representative, the broad-band gap oxide semiconductor material etc. by representative of zinc oxide.
Non-crystalline silicon tft is restricted due to low mobility in terms of high-resolution is shown.Though multi-crystal TFT has higher mobility,
But has the shortcomings that complex process, cost of manufacture costliness, large area are difficult to realize, it is aobvious to be mainly used in small size high-performance at present
Show device.In addition, silicon is narrow bandgap semiconductor material, silicon substrate TFT is sensitive to visible light, exists under light environment apparent unstable
It is qualitative, it needs to introduce black matrix in flat panel display, to increase the complexity of technique, reduces aperture opening ratio.Organic tft exists
Wearable electronic has apparent advantage in terms of Flexible Displays, but its low mobility and the unstable deadly defect of performance influence
Its application prospect.In contrast, there is relatively high mobility, low-power consumption, environment friend by the oxide TFT of representative of zinc oxide
The many advantages such as good, visible transparent, low temperature process, in transparent electronics, liquid crystal display, solar cell, touch screen, soft
Property show, the numerous areas such as Electronic Paper, integrated circuit have broader practice foreground, it is considered to be the most promising next generation
TFT technology.
Although semiconductor active layer material takes decisive role to the electrical property of TFT devices, however, gate medium, grid and
The material of source-drain electrode and the preparation process of device also have an important influence on the electrical property of device, and the electrical property of device is bright
Material property, process conditions and parameter and the structure and parameter of device are depended on aobviously.In recent years, in order to improve TFT devices
Electrical property and its stability, carried out a large amount of research work, TFT devices in material selection, technique and interface optimization etc.
The performance parameters such as mobility, switching current ratio, off-state current, the subthreshold swing of part are improved significantly, and application is not only
It is limited to play switch and pixel driver in flat-panel monitor, is expected to be applied to the work(such as IC chip realization signal amplification
Energy.However, not as silicon substrate MOSFET element, it can be by silicon substrate substrate biasing come the partial properties parameter of adjusting means, existing TFT devices
The unit for electrical property parameters (such as threshold voltage, transadmittance gain, off-state current) of part tends not to need to carry out according to practical application
Flexible regulation and control, and threshold voltage shift, off-state current increase and mobil-ity degradation caused by generally existing operating voltage
Phenomena such as, to influence the stability and reliability of electronic system.
Invention content
In order to overcome the disadvantages mentioned above and deficiency of the prior art, the purpose of the present invention is to provide a kind of planar split dual gates
Thin film transistor (TFT).The device can neatly modulate its raceway groove electricity since there are two gate electrodes by changing two grid voltages
It leads, to the output characteristics and transfer characteristic of adjusting means, changes the performance parameters such as threshold voltage, off-state current, thus, it can root
It needs to obtain required threshold voltage, switching current ratio and transconductance value according to practical application, two grid ends can be used as control gate simultaneously
It is used with signal grid, circuit is made to be simplified, to effectively expand the application range of thin film transistor (TFT), threshold can be efficiently solved
The problems such as threshold voltage drift, big signal blockage, automatic growth control narrow dynamic range.
Another object of the present invention is to provide the preparation methods of above-mentioned planar split dual gate thin film transistor (TFT).
The purpose of the present invention is achieved through the following technical solutions：
The planar split dual gate thin film transistor (TFT) includes substrate, transition zone, gate electrode layer, insulation successively from bottom to top
Gate dielectric layer, semiconductor active layer, source/drain electrode, the source electrode and drain electrode, which is relatively arranged on the semiconductor, to be had
Above active layer；The gate electrode layer is made of two gate electrodes, and described two gate electrodes are relatively arranged on the top of transition zone；Institute
It is different from the direction that source/drain electrode is arranged to state gate electrode, it is preferable that the gate electrode direction and source/drain electrode institute
The channel direction of formation is vertical, and the gate electrode is arranged with source-drain electrode with class " # " type.
The insulated gate dielectric layer segments covering grid electrode layer and transition zone.Insulation is completely covered in the semiconductor active layer
Gate dielectric layer.
The semiconductor active layer is non-crystalline silicon, polysilicon, organic semiconductor thin-film and the oxide of 30~80 nanometer thickness
One kind in semiconductive thin film.
Described two gate electrodes, which are perpendicular among source electrode and drain electrode, is formed by channel direction (i.e. source electrode and leakage
The direction of electrode) end line two metal electrodes, be structurally and functionally equivalent；The width of two gate electrodes and they
Between distance can be adjusted according to the design requirement of device.
The insulation gate dielectric layer is silica, silicon nitride, aluminium oxide, hafnium oxide or the oxidation of 100~200 nanometer thickness
One kind in tantalum insulating dielectric materials, but not limited to this.
The gate electrode and source/drain electrode material are one kind in Al, Mo, Cr, Au or ITO conductive film, described
Source/drain electrode thickness is 100~200 nanometers, and the thickness of the gate electrode is 80~100 nanometers.
For the source electrode and drain electrode on semiconductor active layer, the length of source electrode and drain electrode is wide less than two gate electrodes
The summation of degree and its spacing, and there are overlapping regions with gate electrode at source electrode and drain electrode both ends.
The substrate is glass substrate or plastic supporting base.
The preparation method of the planar split dual gate thin film transistor (TFT), includes the following steps：
(1) insulating dielectric materials are deposited on substrate as transition zone；The thickness of the transition zone is 100~200 nanometers,
The transition zone is silica, silicon nitride or alumina insulation dielectric film；
(2) conductive film is deposited on transition zone, is lithographically formed two gate electrodes；The thickness of the gate electrode be 80~
100 nanometers；
(3) insulation film is deposited on transition zone and gate electrode forms insulation gate dielectric layer；The insulation gate dielectric layer portion
Divide covering transition zone and gate electrode；The thickness of the insulation gate dielectric layer is 100~200 nanometers；
(4) the deposited semiconductor film on insulation gate dielectric layer, forms semiconductor active layer；
(5) spin coating photoresist layer on the gate electrode and transition zone covered in semiconductor active layer, not by insulation gate dielectric layer,
The contact hole of source electrode and drain electrode is formed on semiconductor active layer by photoetching；
(6) conductive film is deposited on contact hole and photoresist, source electrode and drain electrode is formed by lift-off technology；And
By lift-off technology, also do not shelled by the conductive film on the photoresist and photoresist on gate electrode that insulation gate dielectric layer covers
From；The thickness of the source electrode and drain electrode is 100~200 nanometers；
(7) it is made annealing treatment in 150~250 DEG C in the atmosphere of nitrogen.The time of the annealing be 20~
40min。
Compared with prior art, the present invention has the following advantages and beneficial effect：
The present invention uses planar split dual gate structure, the bias by adjusting two grids in vertical-channel direction that can make
TFT devices work in different states, show different output and transfer characteristic, therefore, can obtain according to the actual application
Required threshold voltage, off-state current and transconductance value are obtained, two grids can be used as control gate and signal grid use, make circuit simultaneously
It is simplified, to effectively expand the application range of TFT, is expected to solve threshold voltage shift, automatic growth control dynamic model
Enclose the problems such as narrow.
Description of the drawings
Fig. 1 is the device architecture schematic diagram of the planar split dual gate thin film transistor (TFT) of the present invention；Wherein Fig. 1 (a), Fig. 1
(b), Fig. 1 (c) is respectively stereogram, vertical view and sectional view；Wherein 1- substrates, 2- transition zones, 3- gate electrode layers (301 and 302
Two gate electrodes), 4- insulation gate dielectric layer, 5- semiconductor active layers, 6- source/drain electrodes (602 and 601)；
Fig. 2 (a)~(e) sequentially shows the main technological steps of a production method of the thin film transistor (TFT) of the present invention,
Wherein：
Fig. 2 (a) illustrates the processing step of transition zone formation；
Fig. 2 (b) illustrates to prepare the processing step of double grid electrode layer；
Fig. 2 (c) illustrates the processing step that insulation gate dielectric layer is formed；
Fig. 2 (d) illustrates the processing step of semiconductor active layer formation；
Fig. 2 (e) illustrates the processing step of source-drain electrode formation.
Specific implementation mode
With reference to specific embodiments and the drawings, the present invention is described in further detail, but the embodiment party of the present invention
Formula and the substrate of adaptation are without being limited thereto.
Embodiment 1
The planar split dual gate thin film transistor (TFT) of the present embodiment uses bottom grating structure, includes substrate 1, mistake successively from bottom to top
Cross layer 2, gate electrode layer 3, insulation gate dielectric layer 4, semiconductor active layer 5, source/drain electrode 6；The gate electrode layer is by two
Gate electrode forms, and two gate electrodes are opposite to be arranged in parallel on transition zone；Described two gate electrode lines direction is perpendicular to source electricity
Pole/drain electrode line direction, is structurally and functionally equivalent；The source/drain electrode is opposite to be arranged in parallel.
The substrate of the present embodiment can be glass substrate or plastic supporting base.
The semiconductor active layer of the present embodiment is 30~80 nanometers and indium-doped sows zinc oxide (IGZO) semiconductive thin film.
The insulation gate dielectric layer of the present embodiment is the high-k insulating thin layer of 100~200 nanometer thickness, low to realize
Operating voltage and low-power consumption.
It is overlapping to constitute class " # " type perpendicular to source, drain electrode line direction for the line direction of the double grid termination electrode of the present embodiment
Region.
The preparation method of the planar split dual gate thin film transistor (TFT) of the present embodiment, includes the following steps：
(1) 100~200 are deposited on glass or plastic base using plasma-enhanced chemical vapor deposition (PECVD)
The silica membrane of nanometer thickness forms transition zone, as shown in Fig. 2 (a).
(2) use vacuum evaporation or sputtering technology deposited on transition zone 80~100 nanometer thickness ito thin film or Al it is thin
Film, and two gate electrodes are formed by photoetching process, as shown in Fig. 2 (b).
(3) 100~200 nanometer thickness are deposited on double grid electrode layer and transition zone using atomic layer deposition (ALD) technology
Aluminum oxide film forms insulation gate dielectric layer, and insulation gate dielectric layer can also select silicon nitride, hafnium oxide, lanthana, tantalum oxide
Equal insulation films, as shown in Fig. 2 (c).The insulated gate dielectric layer segments covering grid electrode and transition zone.
(4) magnetron sputtering method is used to deposit IGZO films on insulation gate dielectric layer as semiconductor active layer, such as Fig. 2
(d) shown in.
(5) spin coating photoresist layer on the gate electrode and transition zone covered in semiconductor active layer, not by insulation gate dielectric layer,
By being lithographically formed the contact hole in source and drain electrode, then one layer of 100~200 nanometer thickness is deposited in contact hole and photoresist layer
Al, Cr, Mo, Au or ITO conductive film form source, drain electrode by lift-off technology；And by lift-off technology, do not insulated
The conductive film on photoresist and photoresist on the gate electrode of gate dielectric layer covering is also stripped；As shown in Fig. 2 (e).It is described
The thickness of source electrode and drain electrode is 100~200 nanometers.
(6) it is made annealing treatment 30 minutes in 150~250 DEG C under nitrogen protection.
The present invention uses planar split dual gate structure, by adjusting the raceway groove side formed among vertical source electrode and drain electrode
To the biass of two gate electrodes thin film transistor (TFT) can be made to work in different states, adjust transfer characteristic, therefore can be according to reality
Border application need to obtain needed for threshold voltage, off-state current and transconductance value, and two gate electrodes can be used as simultaneously control gate and
Signal grid uses, and circuit is made to be simplified, and to effectively expand the application range of thin film transistor (TFT), can efficiently solve threshold value
The problems such as voltage drift, big signal blockage, automatic growth control narrow dynamic range.
The above embodiment is a preferred embodiment of the present invention, but embodiments of the present invention are not by the embodiment
Limitation, it is other it is any without departing from the spirit and principles of the present invention made by changes, modifications, substitutions, combinations, simplifications,
Equivalent substitute mode is should be, is included within the scope of the present invention.
Claims (7)
1. a kind of planar split dual gate thin film transistor (TFT), it is characterised in that：Include substrate, transition zone, grid electricity successively from bottom to top
Pole layer, insulation gate dielectric layer, semiconductor active layer, source/drain electrode, the source electrode and drain electrode is relatively arranged on described
Above semiconductor active layer；The gate electrode layer is made of two gate electrodes；Described two gate electrodes are relatively arranged on transition zone
Top；The gate electrode is different from the direction that source/drain electrode is arranged；The gate electrode direction and source/drain electrode
It is vertical to be formed by channel direction, the gate electrode is arranged with source/drain electrode with class " # " type；Two gate electrodes can be simultaneously
It is used as control gate and signal grid；
The source/drain electrode on semiconductor active layer, the length of source electrode and drain electrode be less than two gate electrode widths with
The summation of its spacing.
2. planar split dual gate thin film transistor (TFT) according to claim 1, it is characterised in that：The insulated gate dielectric layer segments
Covering grid electrode layer and transition zone；Insulation gate dielectric layer is completely covered in the semiconductor active layer.
3. planar split dual gate thin film transistor (TFT) according to claim 1, it is characterised in that：The thickness of the semiconductor active layer
Degree is 30~80 nanometers, and the semiconductor active layer is that non-crystalline silicon, polysilicon, organic semiconductor thin-film and oxide semiconductor are thin
One kind in film.
4. planar split dual gate thin film transistor (TFT) according to claim 1, it is characterised in that：The thickness of the insulation gate dielectric layer
Degree is 100~200 nanometers, and the insulation gate dielectric layer is silica, silicon nitride, aluminium oxide, hafnium oxide or tantalum oxide insulation
One kind in dielectric material；
The thickness of the transition zone is 100~200 nanometers, and the transition zone is silica, silicon nitride or alumina insulation medium
Film.
5. planar split dual gate thin film transistor (TFT) according to claim 1, it is characterised in that：The gate electrode and source electrode/
Drain electrode material is one kind in Al, Mo, Cr, Au or ITO conductive film, and the thickness of the gate electrode is 80~100 nanometers；
The source/drain electrode thickness is 100~200 nanometers；
The substrate is glass substrate or plastic supporting base.
6. according to the preparation method of any one of the claim 1 ~ 5 planar split dual gate thin film transistor (TFT), it is characterised in that packet
Include following steps：
（1）Deposition insulating dielectric materials are as transition zone on substrate；
（2）Conductive film is deposited on transition zone, is lithographically formed two gate electrodes；
（3）Insulation film is deposited on transition zone and gate electrode forms insulation gate dielectric layer；
（4）The deposited semiconductor film on insulation gate dielectric layer, forms semiconductor active layer；
（5）In semiconductor active layer, not by gate electrode that insulation gate dielectric layer covers and the mistake not covered by insulation gate dielectric layer
Spin coating photoresist layer on layer is crossed, forms the contact hole of source electrode and drain electrode on semiconductor active layer by photoetching；
（6）Conductive film is deposited on contact hole and photoresist, source electrode and drain electrode is formed by lift-off technology；And pass through
Lift-off technology is not also stripped by the conductive film on the photoresist and photoresist on gate electrode that insulation gate dielectric layer covers；
（7）It is made annealing treatment in 150~250 DEG C in the atmosphere of nitrogen.
7. the preparation method of planar split dual gate thin film transistor (TFT) according to claim 6, it is characterised in that：The insulated gate
Dielectric layer segments cover transition zone and gate electrode；The time of the annealing is 20 ~ 40min.
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