CN105449000A - Double-active layer Cu2O/SnOp channel thin film transistor and preparation method thereof - Google Patents
Double-active layer Cu2O/SnOp channel thin film transistor and preparation method thereof Download PDFInfo
- Publication number
- CN105449000A CN105449000A CN201510974464.7A CN201510974464A CN105449000A CN 105449000 A CN105449000 A CN 105449000A CN 201510974464 A CN201510974464 A CN 201510974464A CN 105449000 A CN105449000 A CN 105449000A
- Authority
- CN
- China
- Prior art keywords
- active layer
- semiconductor active
- film
- snop
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 25
- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- BERDEBHAJNAUOM-UHFFFAOYSA-N copper(I) oxide Inorganic materials [Cu]O[Cu] BERDEBHAJNAUOM-UHFFFAOYSA-N 0.000 title abstract description 5
- KRFJLUBVMFXRPN-UHFFFAOYSA-N cuprous oxide Chemical compound [O-2].[Cu+].[Cu+] KRFJLUBVMFXRPN-UHFFFAOYSA-N 0.000 title abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 239000010408 film Substances 0.000 claims description 45
- 238000009413 insulation Methods 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 239000004033 plastic Substances 0.000 claims description 3
- 229920003023 plastic Polymers 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 8
- 239000001301 oxygen Substances 0.000 abstract description 8
- 229910052760 oxygen Inorganic materials 0.000 abstract description 8
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 4
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 239000012528 membrane Substances 0.000 abstract 1
- 238000013508 migration Methods 0.000 abstract 1
- 230000005012 migration Effects 0.000 abstract 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 4
- 238000001755 magnetron sputter deposition Methods 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 230000001105 regulatory effect Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229920001621 AMOLED Polymers 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 229910006404 SnO 2 Inorganic materials 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229940112669 cuprous oxide Drugs 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention belongs to the technical field of semiconductors, and discloses a double-active layer Cu2O/SnOp channel thin film transistor and a preparation method thereof. The thin film transistor comprises a substrate, a grid electrode, a grid insulating medium layer, a first semiconductor active layer, a second semiconductor active layer, a source electrode and a drain electrode from bottom to top, wherein the first semiconductor active layer is a p-type SnO semiconductor active layer and the second semiconductor active layer is a Cu2O semiconductor active layer. According to the p-type SnO semiconductor active layer, oxygen vacancy is imported to properly optimize the valence band structure, so that the hole migration rate is improved; and through depositing a layer of Cu2O membrane on the SnO active layer, the surface leakage current is decreased, the switch current ratio is improved, the influences on the SnO layer from the external oxygen and water are decreased and the device stability is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of two active layer structure Cu
2o/SnOp channel thin-film transistor and preparation method thereof.
Background technology
In recent years, the flat panel display being representative with active matrix liquid crystal display (AM-LCD) and active matrix organic light emitting diode display (AMOLED) obtains development at a high speed.The Primary Component that thin-film transistor (TFT) drives as active flat panel display, plays an important role to the display effect of flat-panel monitor.Thin-film transistor mainly comprises silica-based TFT, organic tft and oxide TFT, wherein amorphous silicon film transistor (a-SiTFT) and polycrystalline SiTFT (p-SiTFT) are because of technique relative maturity, good stability, be widely used in flat-panel monitor, remain the TFT technology of main flow at present.
In recent years, based on the TFT of metal-oxide semiconductor (MOS) because having the advantages such as relatively high carrier mobility, high light transmission, low temperature process, be expected to become follow-on main flow TFT technology.Along with improving constantly of oxide TFT electrical property, its range of application is not only at the active matrix driving of flat-panel monitor, be expected to the peripheral driving circuit that alternative si-substrate integrated circuit serves as display, realize fully integratedization flat panel display, and be applied to the fields such as Intelligent Sensorsystem, Intelligent Recognition card, wearable electronic system.Realize these application demands, adopt a kind of complementary type integrated device simultaneously comprising n and p channel TFT device to be optimal selection.But the oxide semiconductor material be applied at present in TFT is mostly N-shaped conduction type, as ZnO, In
2o
3, SnO
2and doping oxide, but due to the compensating action of its intrinsic defect, these oxides are difficult to form p-type electric-conducting type, are thus difficult to realize p channel TFT device.Therefore, the research and development based on p channel metal-oxide TFT device are most important.Research finds, Cu
2the metal-oxide film materials such as O, CuO, SnO have p-type semiconductor characteristic, and utilize these materials to serve as semiconductor active layer successfully to prepare p channel TFT device.At present, based on Cu
2the problems such as the research of the p ditch TFT device of the metal oxides such as O, SnO has obtained certain progress, but this kind of device ubiquity hole mobility is low, and tracking current is large, and off-state current is large, and hole concentration is high.
Summary of the invention
In order to overcome the above-mentioned shortcoming of prior art with not enough, the object of the present invention is to provide a kind of two active layer structure Cu
2o/SnOp channel thin-film transistor, can improve hole mobility effectively, reduces tracking current, thus reduces off-state current, improves switch current ratio, reduces the impact of water and oxygen in environment, improves the stability of device.
Another object of the present invention is to provide above-mentioned Cu
2the preparation method of the two active layer structure p channel thin-film transistor of O/SnO.
Object of the present invention is achieved through the following technical solutions:
The Cu of a kind of pair of active layer structure
2o/SnOp channel thin-film transistor, comprises substrate, grid, gate insulation dielectric layer, the first semiconductor active layer, the second semiconductor active layer, source electrode and drain electrode from the bottom to top successively.
Described first semiconductor active layer is p-type SnO semiconductor active layer, and its thickness is 10 ~ 30nm; Described second semiconductor active layer is Cu
2o semiconductor active layer, its thickness is 20 ~ 30nm.
Described grid part covers substrate, and described gate insulation dielectric layer segments cover gate, the complete covering gate insulating medium layer of described first semiconductor active layer, described second semiconductor active layer covers the first semiconductor active layer completely.
Described source electrode and drain electrode are oppositely arranged.
Described gate insulation dielectric layer is HfO
2/ Al
2o
3bilayer film or AlN film, its thickness is 50 ~ 300nm.
Described source electrode, drain electrode are Pt/Ni double-layer metal film or Au/Ni double-layer metal film, when described source electrode, drain electrode are for Pt/Ni double-layer metal film, and the thickness of Ni: 30 ~ 50nm, the thickness of Pt: 50 ~ 150nm.The thickness of described source electrode, drain electrode is 80 ~ 200nm.Described Ni layer is near the second semiconductor active layer.
Described grid material is the one in Pt, Au, Mo, ITO conductive film, and the thickness of grid is 100 ~ 200nm.
Described substrate is plastics or glass.
The Cu of described pair of active layer structure
2the preparation method of O/SnOp channel thin-film transistor, comprising:
(1) growing metal conductive film in substrate, is then etched into grid;
(2) on grid, deposit insulation film, form gate insulation dielectric layer; Described insulation film is HfO
2/ Al
2o
3bilayer film or AlN film;
(3) on gate insulation dielectric layer, deposited semiconductor film forms the first semiconductor active layer; Described first semiconductor active layer is p-type SnO semiconductor active layer;
(4) on the first semiconductor active layer, deposited semiconductor film forms the second semiconductor active layer, and the second semiconductor active layer is Cu
2o semiconductor active layer;
(5) depositing electrically conductive film on the second semiconductor active layer, photoetching forms source electrode and drain electrode; Described conductive film is Pt/Ni bilayer film or Au/Ni bilayer film;
(6) in atmosphere in 150 DEG C ~ 200 DEG C annealing in process.
The invention has the beneficial effects as follows:
(1) the p-type SnO semiconductor active layer prepared, introducing Lacking oxygen defect suitably can optimize valence band structure, thus improves the mobility in hole;
(2) by depositing one deck Cu on SnO active layer
2o film, reduces tracking current, improves switch current ratio, decreases external oxygen and water to the impact of SnO layer, improves the stability of device;
(3) preparation temperature is lower, easily realizes the flexibility of display device; Preparation technology and n tunnel oxide TFT compatibility, easily realize the cmos device based on sull, thus be conducive to expanding its range of application.
Accompanying drawing explanation
Fig. 1 (a) and Fig. 1 (b) is respectively a kind of two active layer Cu of the present invention
2the profile of the device architecture of one example of O/SnOp channel thin-film transistor and vertical view;
Fig. 2 (a) ~ (e) sequentially show the main technological steps of a manufacture method of thin-film transistor of the present invention, wherein:
Fig. 2 (a) illustrates the processing step that grid is formed;
Fig. 2 (b) illustrates the processing step of gate insulation dielectric layer growth;
Fig. 2 (c) illustrates the processing step of ground floor tin oxide semiconductor active layer growth;
Fig. 2 (d) illustrates the processing step of second layer cuprous oxide semiconductor active layer growth;
Fig. 2 (e) illustrates source, drain regions deposit and patterned processing step.
Embodiment
Below in conjunction with specific embodiments and the drawings, the present invention is described in further detail, but the substrate of embodiments of the present invention and adaptation is not limited thereto.
Embodiment
The Cu of two active layer structure of the present embodiment
2o/SnOp channel thin-film transistor comprises substrate (1), grid (2), gate insulation dielectric layer (3), p-type SnO semiconductor active layer (4), Cu from the bottom to top successively
2o semiconductor active layer (5), source electrode and drain electrode (6); Its structural representation as shown in Figure 1.
Described grid part covers substrate, described gate insulation dielectric layer segments cover gate, the complete covering gate insulating medium layer of described p-type SnO semiconductor active layer, described Cu
2the complete blanket p-type SnO semiconductor active layer of O semiconductor active layer.
Described source electrode and the opposing parallel setting of drain electrode.
The embodiment of the present invention also proposed above-mentioned Cu
2the preparation method of O/SnOp channel thin-film transistor, comprising:
1, substrate is made: the substrate of the present embodiment is plastics (as PET) substrate or glass substrate;
2, grid is prepared on the substrate: adopt magnetically controlled sputter method to prepare 100 ~ 200nmITO film, form grid by photoetching, as shown in Fig. 2 (a);
3, on grid, HfO is prepared
2/ Al
2o
3or AlN gate insulation dielectric layer:
Magnetron sputtering method is adopted to prepare HfO
2/ Al
2o
3or AlN gate insulation dielectric layer, for HfO
2/ Al
2o
3gate insulation dielectric layer, successively with Al
2o
3and HfO
2for target, pass into a certain amount of argon gas and oxygen in sputter procedure, form two insulating medium layer, the thickness of every one deck is regulated and controled by sputtering power and sputtering time; For AlN gate insulation dielectric layer, employing Al is target, passes into a certain amount of argon gas and nitrogen in sputter procedure, and its thickness is regulated and controled by sputtering power and sputtering time; In the present embodiment, described gate insulation thickness of dielectric layers is 50 ~ 200nm; As shown in Fig. 2 (b);
4, at described HfO
2/ Al
2o
3or AlN gate insulation dielectric layer prepares p-type SnO semiconductor active layer:
Adopt magnetron sputtering method at described HfO
2/ Al
2o
3the p-type SnO semiconductor active layer that one deck 10 ~ 20nm is thick prepared by the gate insulation dielectric layer of bilayer film or AlN film, as shown in Fig. 2 (c); Employing Sn is target, by regulating suitable argon gas and oxygen flow ratio, makes to there is appropriate Sn interstitial atom and O room in the SnO active layer film of deposition;
5, on described p-type SnO semiconductor active layer, one deck Cu is prepared
2o semiconductor active layer:
In the present embodiment, magnetron sputtering method is adopted, with Cu
2o is target, by regulating suitable argon flow amount, and the Cu that sputtering sedimentation one deck 20 ~ 30nm is thick on described p-type SnO semiconductor active layer
2o semiconductor active layer, as shown in Fig. 2 (d);
6, source electrode and drain electrode is prepared:
In the present embodiment, at described Cu
2o semiconductor active layer adopts magnetron sputtering method prepare the Pt/Ni metallic film of 100 ~ 200nm, wherein Ni thickness is 30 ~ 50nm, Pt thickness is that 50 ~ 150nm, Ni layer is near Cu
2o layer, and form source, drain electrode, as shown in Fig. 2 (e) by photoetching;
7, anneal:
In the present embodiment, by described Cu
2o/SnOp channel thin-film transistor is put in atmosphere, 150 DEG C ~ 200 DEG C annealing 30min.
The Cu proposed in embodiments of the present invention
2o/SnOp channel thin-film transistor and preparation method thereof has the following advantages: the SnO semiconductor active layer containing O room prepared by (1), and the defect of formation changes valence band structure, thus effectively improves the mobility in hole; (2) on SnO semiconductor active layer, one deck Cu is deposited
2o film, reduces tracking current, improves switch current ratio, decreases external oxygen and water to the impact of SnO layer, improves device stability; (3) preparation temperature is low, easily realizes the flexibility of active display; Preparation technology and n tunnel oxide TFT compatibility, easily realize the cmos device based on sull, thus be conducive to expanding its range of application.。
Above-mentioned concrete execution mode is detailed description made for the present invention, is the present invention's preferably execution mode, but does not assert that specific embodiment of the invention is only limited to this explanation.To the technical field of the invention, without departing from the inventive concept of the premise, the change done, replaces, and combination etc. are the substitute mode of equivalence, are included within protection scope of the present invention.
Claims (8)
1. the Cu of a two active layer structure
2o/SnOp channel thin-film transistor, is characterized in that: comprise substrate, grid, gate insulation dielectric layer, the first semiconductor active layer, the second semiconductor active layer, source electrode and drain electrode from the bottom to top successively; Described first semiconductor active layer is p-type SnO semiconductor active layer; Described second semiconductor active layer is Cu
2o semiconductor active layer.
2. the Cu of two active layer structure according to claim 1
2o/SnOp channel thin-film transistor, is characterized in that: the thickness of described first semiconductor active layer is 10 ~ 30nm; The thickness of described second semiconductor active layer is 20 ~ 30nm.
3. the Cu of two active layer structure according to claim 1
2o/SnOp channel thin-film transistor, is characterized in that: described gate insulation dielectric layer is HfO
2/ Al
2o
3bilayer film or AlN film, the thickness of described gate insulation dielectric layer is 50 ~ 300nm.
4. the Cu of two active layer structure according to claim 1
2o/SnOp channel thin-film transistor, is characterized in that: described source electrode, drain electrode are Pt/Ni double-layer metal film or Au/Ni double-layer metal film; The thickness of described source electrode, drain electrode is 80 ~ 200nm.
5. the Cu of two active layer structure according to claim 4
2o/SnOp channel thin-film transistor, is characterized in that: when described source electrode, drain electrode are for Pt/Ni double-layer metal film, the thickness of Ni film: 30 ~ 50nm, the thickness of Pt film: 50 ~ 150nm.
6. the Cu of two active layer structure according to claim 1
2o/SnOp channel thin-film transistor, it is characterized in that: described grid part covers substrate, described gate insulation dielectric layer segments cover gate, the complete covering gate insulating medium layer of described first semiconductor active layer, described second semiconductor active layer covers the first semiconductor active layer completely.
7. the Cu of two active layer structure according to claim 1
2o/SnOp channel thin-film transistor, is characterized in that: described grid material is the one in Pt, Au, Mo, ITO conductive film, and the thickness of described grid is 100 ~ 200nm;
Described substrate is plastics or glass.
8. the Cu of two active layer structure according to any one of claim 1 ~ 7
2the preparation method of O/SnOp channel thin-film transistor, is characterized in that comprising the steps:
(1) growing metal conductive film in substrate, is then etched into grid;
(2) on grid, deposit insulation film, form gate insulation dielectric layer; Described insulation film is HfO
2/ Al
2o
3bilayer film or AlN film;
(3) on gate insulation dielectric layer, deposited semiconductor film forms the first semiconductor active layer; Described first semiconductor active layer is p-type SnO semiconductor active layer;
(4) on the first semiconductor active layer, deposited semiconductor film forms the second semiconductor active layer, and the second semiconductor active layer is Cu
2o semiconductor active layer;
(5) depositing electrically conductive film on the second semiconductor active layer, photoetching forms source electrode and drain electrode; Described conductive film is Pt/Ni bilayer film or Au/Ni bilayer film;
(6) in atmosphere in 150 DEG C ~ 200 DEG C annealing in process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510974464.7A CN105449000A (en) | 2015-12-21 | 2015-12-21 | Double-active layer Cu2O/SnOp channel thin film transistor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510974464.7A CN105449000A (en) | 2015-12-21 | 2015-12-21 | Double-active layer Cu2O/SnOp channel thin film transistor and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105449000A true CN105449000A (en) | 2016-03-30 |
Family
ID=55558987
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510974464.7A Pending CN105449000A (en) | 2015-12-21 | 2015-12-21 | Double-active layer Cu2O/SnOp channel thin film transistor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105449000A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107204284A (en) * | 2017-05-09 | 2017-09-26 | 西北大学 | The method that cuprous oxide semiconductor conductivity types are controlled based on deposition potential |
| CN108011042A (en) * | 2017-06-17 | 2018-05-08 | 电子科技大学 | Double-deck active layer thin film transistor (TFT) and preparation method |
| CN110739221A (en) * | 2019-10-23 | 2020-01-31 | 昆明物理研究所 | Preparation method of tin oxide film with adjustable band gap |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102254950A (en) * | 2011-07-12 | 2011-11-23 | 北京大学深圳研究生院 | Cuprous oxide thin film transistor and preparing method thereof |
| CN102263134A (en) * | 2011-07-22 | 2011-11-30 | 北京大学深圳研究生院 | Bipolar thin film transistor and preparation method thereof |
| CN205335261U (en) * | 2015-12-21 | 2016-06-22 | 华南理工大学 | Two active layer cu2OSnO p channel thin film transistor |
-
2015
- 2015-12-21 CN CN201510974464.7A patent/CN105449000A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102254950A (en) * | 2011-07-12 | 2011-11-23 | 北京大学深圳研究生院 | Cuprous oxide thin film transistor and preparing method thereof |
| CN102263134A (en) * | 2011-07-22 | 2011-11-30 | 北京大学深圳研究生院 | Bipolar thin film transistor and preparation method thereof |
| CN205335261U (en) * | 2015-12-21 | 2016-06-22 | 华南理工大学 | Two active layer cu2OSnO p channel thin film transistor |
Non-Patent Citations (1)
| Title |
|---|
| H.A.AI-JAWHARI ETC: "Tunable Performance of P-Type Cu2O/SnO Bilayer Thin Film Transistors", 《ADVANCES IN SCIENCE AND TECHNOLOGY》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107204284A (en) * | 2017-05-09 | 2017-09-26 | 西北大学 | The method that cuprous oxide semiconductor conductivity types are controlled based on deposition potential |
| CN108011042A (en) * | 2017-06-17 | 2018-05-08 | 电子科技大学 | Double-deck active layer thin film transistor (TFT) and preparation method |
| CN110739221A (en) * | 2019-10-23 | 2020-01-31 | 昆明物理研究所 | Preparation method of tin oxide film with adjustable band gap |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103346089B (en) | A kind of autoregistration bilayer channel metal-oxide thin film transistor (TFT) and preparation method thereof | |
| WO2012044344A1 (en) | Method of making oxide thin film transistor array, and device incorporating the same | |
| CN102263134B (en) | Bipolar thin film transistor and preparation method thereof | |
| CN103311128A (en) | Self-aligning metal oxide thin film transistor and manufacturing method thereof | |
| CN102842619A (en) | Semiconductor device and manufacturing method thereof | |
| CN105405893B (en) | A kind of planar split dual gate thin film transistor (TFT) and preparation method thereof | |
| CN102522429A (en) | Thin film transistor on basis of metal oxide and preparation method and application thereof | |
| CN105006487A (en) | Top gate self-aligned metal oxide semiconductor thin-film transistor and preparation method thereof | |
| CN101567390A (en) | Transparent oxide semiconductor thin film transistor and manufacturing method thereof | |
| CN105789117A (en) | Manufacturing method of TFT substrate and manufactured TFT substrate | |
| CN104992981B (en) | Oxide thin film transistor and preparation method thereof and phase inverter and preparation method thereof | |
| JP2007123699A (en) | Thin-film transistor and method of manufacturing same | |
| CN104241299A (en) | Oxide semiconductor TFT substrate manufacturing method and oxide semiconductor TFT substrate structure | |
| CN105449000A (en) | Double-active layer Cu2O/SnOp channel thin film transistor and preparation method thereof | |
| CN103022083B (en) | Array substrate, display device and preparing method of array substrate | |
| CN102709316B (en) | Three-dimensional (3D) oxide semiconductor thin film transistor and preparation method thereof | |
| CN107104151A (en) | A kind of double grid electrode metal oxide thin-film transistor and preparation method thereof | |
| CN104157610A (en) | Manufacture method of oxide semiconductor TFT substrate, and structure of the oxide semiconductor TFT substrate | |
| CN102254950B (en) | Cuprous oxide thin film transistor and preparing method thereof | |
| JP6928333B2 (en) | Oxide semiconductor thin film, thin film transistor, thin film transistor manufacturing method and sputtering target | |
| CN205335261U (en) | Two active layer cu2OSnO p channel thin film transistor | |
| CN207503977U (en) | array substrate, display panel and display device | |
| CN104900707A (en) | Double-active layer structured zinc oxide-based thin film transistor and preparation method thereof | |
| CN102637742A (en) | Oxide semiconductor thin-film transistor and preparation method thereof | |
| CN102779855B (en) | Two schottky junction zinc oxide semiconductor thin film transistor and manufacture method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160330 |