CN105977306A - Self-aligned thin-film transistor and preparation method thereof - Google Patents

Self-aligned thin-film transistor and preparation method thereof Download PDF

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Publication number
CN105977306A
CN105977306A CN201610451662.XA CN201610451662A CN105977306A CN 105977306 A CN105977306 A CN 105977306A CN 201610451662 A CN201610451662 A CN 201610451662A CN 105977306 A CN105977306 A CN 105977306A
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layer
active layer
gate electrode
gate
drain region
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张盛东
邵阳
肖祥
周晓梁
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention discloses a self-aligned thin-film transistor and a preparation method thereof. The method comprises the steps as follows: a substrate deposited with an active layer, a gate dielectric and a gate electrode is put into an electrolyte, wherein the gate dielectric covers one part of the active layer; the gate electrode at least covers one part of the gate dielectric and hydrogen mixing treatment is carried out on the active layer exposed in the electrolyte through a water electrolysis method; an active region comprising a source region, a drain region and a channel region is formed by photoetching and etching the active layer; the channel region is located at the lower part of the gate dielectric; the source region and the drain region are formed by the remaining part of the active layer which is subjected to electrochemical hydrogen mixing treatment after being photoetched and etched, and are located at two sides of the channel region respectively; an insulated dielectric layer covering the substrate, the gate electrode, the source region and the drain region is formed; and a source region metal contact electrode and a drain region metal contact electrode which are in contact with the source region and the drain region respectively are formed.

Description

A kind of self-aligned thin film transistor and preparation method thereof
Technical field
The present invention relates to thin film transistor (TFT), particularly relate to a kind of self-aligned thin film transistor and preparation method thereof.
Background technology
Thin film transistor (TFT) (TFT) technology is the core technology in flat pannel display, any active array addressing mode Flat pannel display such as liquid crystal display (LCD), organic light-emitting diode display (OLED) all rely on TFT Control and drive.As a example by TFT-LCD, on each pixel, at least a thin film transistor (TFT) is automatically controlled Switch, each pixel is exactly a little liquid crystal display, and the bright of each pixel is secretly to be come by this switch Control.
Non-crystalline silicon (a-Si:H) TFT technology is the mainstream technology that current LCD shows, low temperature polycrystalline silicon (LTPS) TFT is mainly directed towards small-medium size OLED and LCD screen.It is low, equal that a-Si:H TFT technology has technological temperature Even property is good, the advantage of low cost.Therefore can realize large-area colour on the glass substrate to show.But it lacks Point is carrier mobility as little as 0.5cm2/ Vs, it is impossible to meet drives, particularly high definition display drives The rate request of circuit, can not meet OLED current type and drive the requirement of display screen.Simultaneously as rely on In the passivation of H, the bond energy of Si-H is relatively low, and the long-term reliability of device is poor, it is impossible to adapt to drive circuit The requirement of work.The carrier mobility of LTPS TFT device than traditional high two orders of magnitude of a-Si:H TFT, It is readily available high aperture, it is achieved the high-resolution of display system and quickly response.LTPS based on high mobility TFT, can prepare active matrix and peripheral driving circuit simultaneously.But, the LTPS technology of current main-stream is deposited At homogeneity question, it is impossible to be applied to large screen display.Current application is mainly directed towards small-medium size OLED and LCD Screen, additionally processing step is complicated, and cost of manufacture is high is also the key factor restricting LTPS TFT application.
Oxide semiconductor material with IGZO as representative, greatly and carrier mobility is permissible to have energy gap Reach 10cm2The advantage of/Vs, owing to it is non crystalline structure, uniformity is good, and leakage current is low.Meanwhile, IGZO Depositing technics be direct current or high frequency magnetron sputter, this technology and existing industrial circle process compatible.Additionally, The processing technology temperature of IGZO TFT is relatively low, therefore can use flexible plastic substrate, it is achieved Flexible Displays.
The channel layer materials that metal oxide thin-film transistor uses mainly has zinc oxide (ZnO), Indium sesquioxide. (In2O3), indium gallium zinc (IGZO), zinc-tin oxide (ZTO), indium zinc oxide (IZO), indium zinc oxide Stannum (TIZO), stannum oxide (SnO2), Tin monoxide (SnO) and Red copper oxide (Cu2O) etc..Metal oxygen The structure that thin film transistor is most frequently with is non-self aligned bottom gate stacked structure, has been divided into the most again quarter Erosion barrier layer structure (ESL) and back of the body channel etching structure (BCE).In order to make oxide semiconductor carry on the back interfacial characteristics Not destroyed by source/drain etching technics, what industrial quarters was most frequently with is etching barrier layer structure.Due to traditional In ESL structure, source/drain region and gate electrode are non-self aligned, and source/drain region and etching barrier layer also right and wrong Self aligned.The structure of non-self-aligned causes transistor to there is big parasitic capacitance, and big alignment tolerance Limit the preparation of small-geometry transistor (L < 10 μm).And self-alignment structure can effectively reduce parasitic capacitance. In order to realize self-alignment structure, conventional is that source/drain region carries out Cement Composite Treated by Plasma, improves source/drain region Electrical conductivity.But, Cement Composite Treated by Plasma needs the vacuum equipment of complex and expensive, and is difficult to ensure that large area is raw The uniformity produced.
Summary of the invention
The present invention provides a kind of self-aligned thin film transistor and preparation method thereof, and this preparation method has minimizing crystalline substance Body pipe parasitic capacitance, the electrical conductivity improving source/drain region and the advantage simplifying preparation technology.
The preparation method of a kind of self-aligned thin film transistor, comprises the following steps:
Being placed in electrolyte by the substrate that deposited active layer, gate medium and gate electrode, wherein gate medium covers A part for active layer, gate electrode at least covers a part for gate medium, to exposing in the electrolytic solution active Layer carries out hydrogen loading process by the method for electrolysis water；
By photoetching be etched with active layer, form the active area comprising source region, drain region and channel region；Channel region Being made up of the active layer processed without electrochemistry hydrogen loading, channel region is positioned at immediately below gate medium, source region and leakage District is by the active layer processed through electrochemistry hydrogen loading remaining part composition after photoetching and etching, and divides It is not positioned at channel region both sides；
Formed and cover substrate, gate electrode, source region and one layer of insulating medium layer in drain region, and formed respectively with The source region Metal contact electrode of source region and drain contact and drain region Metal contact electrode.
Further, step 1) in, substrate is glass substrate or flexible plastic substrate.
Further, step 1) in, active layer is silicon oxide, silicon nitride, Indium sesquioxide., zinc oxide, oxidation At least one in indium stannum and indium zinc oxide, active layer thickness is 5nm～200nm.
Further, step 2) in, gate dielectric layer is silicon oxide, silicon nitride, high-k burning At least one in thing medium and organic media, its thickness is 5nm～800nm.
Further, step 8) in, metal level uses the simple substance in molybdenum, copper, aluminum, titanium and chromium or alloy structure Becoming single metal level or complex metal layer, the thickness of metal level is 10nm～800nm.
Further, comprise the following steps:
1) at one layer of oxide semiconductor thin-film of Grown, as active layer；
2) on active layer, one layer of dielectric is grown, as gate dielectric layer；
3) on gate dielectric layer, layer of metal thin film or transparent conductive film are grown, as gate electrode layer；
4) photoetching and etching gate electrode layer and gate dielectric layer, form gate electrode and gate medium；
5) at atmospheric pressure and room temperature the substrate that deposited active layer, gate medium and gate electrode is placed in electrolyte, The active layer exposed in the electrolytic solution is carried out hydrogen loading process by the method for electrolysis water；
6) pass through photoetching and be etched with active layer, forming the active area comprising source region, drain region and channel region；Raceway groove District is made up of the active layer processed without electrochemistry hydrogen loading, and channel region is positioned at immediately below gate medium, source region and Drain region is formed by the active layer processed through electrochemistry hydrogen loading and lays respectively at channel region both sides；
7) on substrate, gate electrode, source region and drain region, one layer of insulating medium layer is covered, on insulating medium layer It is positioned at source region side and side, drain region and uses photoetching and etching, form two contact holes of electrode；
8) the upper surface deposit layer of metal film in insulating medium layer, the source region of exposure and drain region, uses photoetching Be etched into source region Metal contact electrode and drain region Metal contact electrode.
Further, step 4) in, the preparation method of gate electrode and gate medium is: on whole gate electrode layer Spin coating photoresist, by single exposure, development, continuously etching gate electrode layer and the grid being positioned under gate electrode layer Dielectric layer, the litho pattern forming gate electrode and gate medium, gate electrode and gate medium is identical, and gate medium is positioned at The underface of gate electrode.
Further, step 5) it is that dual-electrode electrolysis pond at atmospheric pressure and room temperature is carried out, electrolyte is adopted With water, aqueous solution containing electrolyte or water and the mixed liquor of organic solution, active layer is negative with external power source The most connected, as negative electrode, the water electrolysis in electrolyte forms hydrion, moves to active layer and enter exposure Active layer in the electrolytic solution.
Further, step 4)～step 5) in, photoetching and etching gate electrode layer and gate dielectric layer, formed Gate electrode and gate medium, cover after the photoresist of surface gate electrode after removing etching, then carry out hydrogen loading process.
Further, step 4)～step 5) in, photoetching and etching gate electrode layer and gate dielectric layer, formed Gate electrode and gate medium, cover after the photoresist of surface gate electrode after retaining etching, then carry out hydrogen loading process, Hydrogen loading removes after processing and covers the photoresist at surface gate electrode.
Further, step 1)～step 3) in, consecutive deposition active layer, gate dielectric layer successively on substrate And gate electrode layer.
A kind of self-aligned thin film transistor, including:
Substrate；
Active layer, active layer is created on substrate, and active layer is oxide semiconductor thin-film, and active layer includes Source region, drain region and the channel region obtained after hydrogen loading process, photoetching and etching；
Gate medium, gate medium is created on active layer, and gate dielectric layer is obtained by photoetching and etching dielectric；
Gate electrode layer, gate electrode layer is created on gate medium, and gate electrode layer is by photoetching and etching metallic film Or transparent conductive film obtains；
Insulating medium layer, is covered on substrate, gate electrode, source region and drain region；
Source region Metal contact electrode and drain region Metal contact electrode, source region Metal contact electrode and source region and insulation Dielectric layer contacts, and drain region Metal contact electrode contacts with drain region and insulating medium layer, source region Metal contact electrode Make by metal membrane material with drain region Metal contact electrode.
Contrast prior art, due to the fact that and take above technical scheme, have the advantage that
1, owing to using the active layer to exposing in the electrolytic solution to carry out negative electrode hydrogen loading process, the hydrion of incorporation Carrier is provided in active layer, improves the carrier concentration of active layer, reduce the resistance of active layer, Make it as the source region of device and drain region.This processing method, channel region and source region, drain region is used to be formed sediment by a step Long-pending technique is formed, it is not necessary to separately adds source drain metal layer technique, simplifies the preparation technology of transistor；
2, the present invention uses electrochemical process to carry out hydrogen loading process, only need to carry out under normal pressure, room temperature environment, Without using vacuum equipment costly, therefore, equipment is cheap, simple to operate, reduces transistor Production cost；
3, substrate can select the flexible material of non-refractory, thus is conducive to being applied in Flexible Displays；
The preparation method of the self-aligned thin film transistor that the present invention provides, makes the source/drain region of transistor be formed with grid Autoregistration, reduces ghost effect.Based on above advantage, the present invention can be extensively in field of thin film transistors Application.
Accompanying drawing explanation
Fig. 1 to Fig. 7 shows the main manufacturing process steps of the thin film transistor (TFT) of the embodiment of the present invention one, its In:
Fig. 1 is the schematic diagram being deposited with active layer；
Fig. 2 is the schematic diagram of deposit gate dielectric layer；
Fig. 3 is the schematic diagram of deposit grid layer；
Fig. 4 is to form gate electrode and the schematic diagram of gate medium；
Fig. 5 is the schematic diagram that the active layer exposed in the electrolytic solution carries out hydrogen loading process；
Fig. 6 is to form source region and the schematic diagram in drain region；
Fig. 7 is the schematic diagram of the contact hole forming electrode after deposit insulating medium layer photoetching and etching；
Fig. 8 is the self-aligned thin film transistor generalized section in the embodiment of the present invention one；
Fig. 9 to Figure 15 shows the main manufacturing process steps of the thin film transistor (TFT) of the embodiment of the present invention two, its In:
Fig. 9 is the schematic diagram being deposited with active layer；
Figure 10 is the schematic diagram of deposit gate dielectric layer；
Figure 11 is the schematic diagram of deposit grid layer；
Figure 12 is to form gate electrode and the schematic diagram of gate medium；
Figure 13 is to retain the photoresist covered on gate electrode, mixes the active layer exposed in the electrolytic solution The schematic diagram that hydrogen processes；
Figure 14 is to make source region and the schematic diagram in drain region；
Figure 15 is the schematic diagram of the contact hole forming electrode after deposit insulating medium layer photoetching and etching；
Figure 16 is the generalized section of the self-aligned thin film transistor in the embodiment of the present invention two.
Detailed description of the invention
Combine accompanying drawing below by detailed description of the invention the present invention is described in further detail.
The present invention provides a kind of self-aligned thin film transistor and preparation method thereof, and this preparation method utilizes electrochemistry Method carries out hydrogen loading process at the oxide semiconductor active layer being positioned at source region and drain region, makes the source/drain of transistor District forms autoregistration with grid, prepares the thin film transistor (TFT) of self-alignment structure.
Embodiment one:
Referring to Fig. 8, the thin film transistor (TFT) of the present invention includes substrate 1, channel region 2, gate medium 3, grid electricity Pole 4, source region 5, drain region 6, insulating medium layer 7, source contact electrode 8 and drain contact electrode 9.Wherein, Channel region 2 on substrate 1, gate medium 3 on channel region 2, gate electrode 4 on gate medium 3, source region 5 With drain region 6 the most on substrate 1, and respectively in channel region 2 both sides, insulating medium layer 7 cover substrate 1, On gate electrode 4, source region 5 and drain region 6, the bottom of source contact electrode 8 connects source region 5, and its both sides connect Insulating medium layer 7, the connection drain region, bottom 6 of drain contact electrode 9, its both sides connect insulating medium layer 7.
In the present embodiment, substrate 1 uses glass substrate or polyimides, PEN, gathers The flexible plastic materials such as ethylene glycol terephthalate.The substrate 1 using flexible plastic material to make can be applied In field of flexible display.Channel region 2 is metal oxide semiconductor material, as containing Zinc oxide-base or oxygen Changing the oxide semiconductor material of indio, its thickness is 5nm～200nm.Gate medium 3 uses nitridation The dielectric such as silicon, silicon oxide, it is possible to use the metal-oxide height K such as aluminium oxide, tantalum oxide or hafnium oxide Medium, it would however also be possible to employ organic media.The thickness of gate medium 3 is 5nm～800nm.Gate electrode 4 can To use at least one in the metal materials such as molybdenum, copper, aluminum, titanium and chromium, it would however also be possible to employ tin indium oxide, The transparent conductive film materials such as aluminium-doped zinc oxide and boron doping zinc-oxide, its thickness is 30nm～300nm. Insulating medium layer 7 use the one in the inorganic mediums such as silicon oxide, silicon nitride, aluminium oxide or organic media or Multiple combination, its thickness is 50nm～1000nm.
Refer to Fig. 1 to Fig. 7, it is shown that the preparation method of a kind of self-aligned thin film transistor, including following step Rapid:
As it is shown in figure 1, choose substrate 1, one layer of oxide semiconductor film materials of growth on substrate 1, make For active layer 20.Active layer 20 can use Indium sesquioxide., zinc oxide, tin indium oxide, indium zinc oxide, oxidation At least one in zinc-tin, indium gallium zinc, Indium sesquioxide. zinc-tin etc., can be as monolayer, bilayer or multilamellar material Material, and formed by the method such as magnetron sputtering or solwution method.
As in figure 2 it is shown, grow one layer of dielectric on active layer 20, as gate dielectric layer 30；Gate medium Layer 30 can use the dielectric such as silicon oxide, silicon nitride, and passes through plasma enhanced CVD Method is formed.The high dielectric constants such as aluminium oxide, hafnium oxide, tantalum oxide can also be used, and by former The methods such as sublayer deposit, anodic oxidation, magnetron sputtering are formed.Organic dielectric material can also be used and pass through Spin coating method is formed.Gate dielectric layer can be made up of the material that monolayer, bilayer or multilamellar are different.
As it is shown on figure 3, grow one layer of grid layer 40 on gate dielectric layer 30, grid layer 40 is metal material Or transparent conductive film material, can be at least one in metal material or transparent conductive film material, can Form monolayer, bilayer or multilayer material.Simple substance or the alloys such as metal material such as molybdenum, copper, aluminum, titanium and chromium, And formed by methods such as magnetron sputtering, electron beam evaporation or thermal evaporations, it would however also be possible to employ tin indium oxide, The nesa coatings such as aluminium-doped zinc oxide, boron doping zinc-oxide, and formed by methods such as magnetron sputterings.
As shown in Figure 4, at the upper spin coating photoresist of whole grid layer 40 (Fig. 3), by single exposure, show Shadow, forms photoetching offset plate figure, continuous etching grid layer 40 and the gate dielectric layer 30 (figure being positioned under grid layer 40 3), forming gate electrode 4 and gate medium 3, the litho pattern of gate electrode 4 and gate medium 3 is just the same, and grid are situated between Matter 3 is positioned at the underface of gate electrode 4.After having etched, remove the photoresist covered on gate electrode 4.
Shown in Fig. 5, the substrate 1 that deposited active layer 20 (Fig. 3), gate medium 3 and gate electrode 4 is placed in In electrolyte, carry out electrochemistry hydrogen loading process to exposing active layer 20 in the electrolytic solution, formed source region 5, Drain region 6 and channel region 2.Source region 5, drain region 6 and channel region 2 two ends connecting place just with gate electrode 4 liang End alignment, therefore, source region 5, drain region 6 and gate electrode 4 autoregistration.Source region 5 and drain region 6 are active layer 20 are mixed with hydrionic material through electrochemical treatments, and channel region 2 is the oxidation without electrochemical treatments Thing semi-conducting material.Use this processing method, channel region 2 and source region 5, drain region 6 by a step depositing technics shape Become, it is not necessary to separately add source drain metal layer technique, simplify the preparation technology of transistor, improve production efficiency. Mix hydrion to carry out in dual-electrode electrolysis pond, electrolyte use water, aqueous solution containing electrolyte or Person's water and the mixed liquor of organic solution.Wherein active layer 20 forms hydrogen as negative electrode, the water electrolysis in electrolyte Ion, hydrion moves to the active layer 20 as negative electrode, and enters the active layer 20 being exposed in electrolyte, Reduce the resistivity of active layer 20.The electrochemical treatments used due to the present invention is to enter at atmospheric pressure and room temperature OK, therefore it is a kind of simple to operate, low temperature process of low cost.
As shown in Figure 6, use photoetching and etching technics to make source region 5 and drain region 6, formed comprise source region 5, Drain region 6 and the active area of channel region 2.Source region 5 and drain region 6 are that active layer 20 (such as Fig. 4) is through electrification Learn the material after hydrogen loading processes, be positioned at the two ends of channel region 2 and be connected with channel region 2, and be all located at lining At at the end 1.Owing to the channel region 2 below gate medium 3 is protected by gate medium 3, at electrochemical treatment process In not with electrolyte contacts, be therefore not incorporated into hydrion.
As it is shown in fig. 7, one layer of insulating medium layer 7 of growth, this insulating medium layer 7 covers and is situated between at substrate 1, grid Matter 3, gate electrode 4, source region 5 and the surface in drain region 6, be then positioned at source region 5 He on insulating medium layer 7 Drain region 6 all uses photoetching and etching to form two contact holes of electrode.Insulating medium layer 7 can use oxygen The dielectric such as SiClx, silicon nitride, and formed by plasma body reinforced chemical vapor deposition method, it is possible to To use the high dielectric constants such as aluminium oxide, hafnium oxide and tantalum oxide and to be spattered by atomic layer deposition and magnetic control The method such as penetrate is formed, it would however also be possible to employ organic dielectric material is also formed by spin coating method.
As shown in Figure 8, the upper surface at whole device uses magnetically controlled sputter method deposit layer of metal thin film material Material, then photoetching and etching are respectively prepared source region Metal contact electrode 8 and the drain region gold of film crystal pipe electrode Belonging to contact electrode 9, source region Metal contact electrode 8 and drain region Metal contact electrode 9 are by each electricity of thin film transistor (TFT) Pole is drawn, and completes metal oxide thin-film transistor and prepares.Wherein, metallic film material can use as molybdenum, Simple substance or the alloys such as copper, aluminum, titanium and chromium, can be the monolayer of previous materials, bilayer or multilayer material composition, And formed by methods such as magnetron sputtering, electron beam evaporation or thermal evaporations.
Embodiment two:
Refer to Figure 16, Figure 16 and show the thin film transistor (TFT) of the embodiment of the present invention two.Thin film in Figure 16 The structure of the thin film transistor (TFT) in transistor AND gate embodiment one is identical, and difference is its preparation method.
Refer to Fig. 9 to Figure 15, it is shown that the preparation method of a kind of self-aligned thin film transistor.The present embodiment Disclosed in self-aligned thin film transistor manufacture method similar with the method disclosed in embodiment one, Fig. 9～11 And its preparation process of Figure 14～15 is identical with embodiment one Fig. 1～3 and Fig. 6～7 respectively.Its difference Place is its preparation process of Figure 12 and Figure 13, specific as follows:
As it is shown in figure 9, choose substrate 1, one layer of oxide semiconductor film materials of growth on substrate 1, make For active layer 20.Active layer 20 can use Indium sesquioxide., zinc oxide, tin indium oxide, indium zinc oxide, oxidation At least one in zinc-tin, indium gallium zinc, Indium sesquioxide. zinc-tin etc., can be as monolayer, bilayer or multilamellar material Material, and formed by the method such as magnetron sputtering or solwution method.
As shown in Figure 10, active layer 20 grows one layer of dielectric, as gate dielectric layer 30；Grid are situated between Matter layer 30 can use the dielectric such as silicon oxide, silicon nitride, and is formed sediment by PECVD Long-pending method is formed.The high dielectric constants such as aluminium oxide, hafnium oxide, tantalum oxide can also be used, and pass through The methods such as atomic layer deposition, anodic oxidation, magnetron sputtering are formed.Organic dielectric material can also be used and lead to Cross spin coating method to be formed.Gate dielectric layer can be made up of the material that monolayer, bilayer or multilamellar are different.
As shown in figure 11, growing one layer of grid layer 40 on gate dielectric layer 30, grid layer 40 is metal material Or transparent conductive film material, can be at least one in metal material or transparent conductive film material, and Can be monolayer, bilayer or multilayer material.Simple substance or the alloys such as metal material such as molybdenum, copper, aluminum, titanium and chromium, And formed by methods such as magnetron sputtering, electron beam evaporation or thermal evaporations, it would however also be possible to employ tin indium oxide, The nesa coatings such as aluminium-doped zinc oxide, boron doping zinc-oxide, and formed by methods such as magnetron sputterings.
As shown in figure 12, spin coating photoresist on whole gate electrode layer, by single exposure, development, formed Photoetching offset plate figure, continuous etching grid layer 40 (Figure 11) and the gate dielectric layer 30 (figure being positioned under grid layer 40 11), forming gate electrode 4 and gate medium 3, the litho pattern of gate electrode 4 and gate medium 3 is just the same, grid Medium 3 is positioned at the underface of gate electrode 4.After having etched, retain the photoresist covered on gate electrode 4 41。
Shown in Figure 13, active layer 20 (Figure 11), gate medium 30 (Figure 11), gate electrode 40 will be deposited (Figure 11) it is placed in electrolyte with the substrate 1 of photoresist-covered 41, active to expose in the electrolytic solution Layer 20 carries out electrochemistry hydrogen loading process, forms source region 5, drain region 6 and channel region 2.Source region 5, drain region 6 with The connecting place at channel region 2 two ends just aligns with gate electrode 4 two ends, therefore, and source region 5, drain region 6 and grid electricity Pole 4 autoregistration.Source region 5 and drain region 6 are mixed with hydrionic material for active layer 20 through electrochemical treatments, Channel region 2 is the oxide semiconductor material without electrochemical treatments.Use this processing method, channel region Formed by a step depositing technics with source region, drain region, it is not necessary to separately add source drain metal layer technique, simplify crystal The preparation technology of pipe, improves production efficiency.Mixing hydrionic concrete grammar is to enter in dual-electrode electrolysis pond Row, electrolyte uses water, aqueous solution containing electrolyte or water and the mixed liquor of organic solution.Wherein have Active layer 20 (such as Figure 12) forms hydrion as negative electrode, the water electrolysis in electrolyte, and hydrion is to as the moon The active layer 20 of pole moves, and enters the active layer 20 being exposed in electrolyte, reduces active layer 20 Resistivity.After electrochemical treatments completes, remove the photoresist 41 covered on gate electrode 3.
As shown in figure 14, use photoetching and etching technics to make source region 5 and drain region 6, formed comprise source region 5, Drain region 6 and the active area of channel region 2.Source region 5 and drain region 6 are that active layer 20 (such as Figure 12) is through electrification Learn the material after hydrogen loading processes, be positioned at the two ends of channel region 2 and be connected with channel region 2, and be all located at lining At at the end 1.Owing to the channel region 2 below gate medium 3 is protected by gate medium 3, at electrochemical treatment process In not with electrolyte contacts, be therefore not incorporated into hydrion.
As shown in figure 15, growing one layer of insulating medium layer 7, this insulating medium layer 7 covers at substrate 1, grid Medium 3, gate electrode 4, source region 5 and the surface in drain region 6, be then positioned at source region 5 on insulating medium layer 7 All use photoetching and etching to form two contact holes of electrode with drain region 6.Insulating medium layer 7 can use The dielectric such as silicon oxide, silicon nitride, and formed by plasma body reinforced chemical vapor deposition method, also The high dielectric constants such as aluminium oxide, hafnium oxide and tantalum oxide can be used and by atomic layer deposition and magnetic control The methods such as sputtering are formed, it would however also be possible to employ organic dielectric material is also formed by spin coating method.
As shown in figure 16, the upper surface at whole device uses magnetically controlled sputter method deposit layer of metal thin film material Material, then photoetching and etching are respectively prepared source region Metal contact electrode 8 and the drain region gold of film crystal pipe electrode Belonging to contact electrode 9, source region Metal contact electrode 8 and drain region Metal contact electrode 9 are by each electricity of thin film transistor (TFT) Pole is drawn, and completes metal oxide thin-film transistor and prepares.Wherein, metallic film material can use as molybdenum, Simple substance or the alloys such as copper, aluminum, titanium and chromium, can be the monolayer of previous materials, bilayer or multilayer material composition, And formed by methods such as magnetron sputtering, electron beam evaporation or thermal evaporations.
Above content is to combine specific embodiment further description made for the present invention, it is impossible to recognize Determine the present invention be embodied as be confined to these explanations.Ordinary skill for the technical field of the invention For personnel, without departing from the inventive concept of the premise, it is also possible to make some simple deduction or replace, All should be considered as belonging to protection scope of the present invention.

Claims (10)

1. the preparation method of a self-aligned thin film transistor, it is characterised in that comprise the following steps:
The substrate that deposited active layer, gate medium and gate electrode is placed in electrolyte, wherein said gate medium covers a part for described active layer, described gate electrode at least covers a part for described gate medium, and by the method for electrolysis water, the described active layer being exposed in described electrolyte is carried out hydrogen loading process；By photoetching and the described active layer of etching, form the active area comprising source region, drain region and channel region；Described channel region is made up of the described active layer processed without electrochemistry hydrogen loading, described channel region is positioned at immediately below gate medium, described source region and described drain region are by the active layer processed through electrochemistry hydrogen loading remaining part composition after described photoetching and etching, and lay respectively at described channel region both sides；Formed and cover described substrate, described gate electrode, described source region and one layer of insulating medium layer in described drain region, and formed respectively with source region Metal contact electrode and the drain region Metal contact electrode of described source region and drain contact.
The preparation method of a kind of self-aligned thin film transistor the most as claimed in claim 1, it is characterised in that: described substrate is glass substrate or flexible plastic substrate.
The preparation method of a kind of self-aligned thin film transistor the most as claimed in claim 1, it is characterized in that: described active layer is at least one in silicon oxide, silicon nitride, Indium sesquioxide., zinc oxide, tin indium oxide and indium zinc oxide, described active layer thickness is 5 nm～200 nm；Described gate medium is at least one in silicon oxide, silicon nitride, high-k metal oxide dielectric and organic media, and its thickness is 5 nm～800 nm.
The preparation method of a kind of self-aligned thin film transistor the most as claimed in claim 1, it is characterised in that comprise the following steps:
1) at one layer of oxide semiconductor thin-film of Grown, as active layer；
2) on described active layer, one layer of dielectric is grown, as gate dielectric layer；
3) on described gate dielectric layer, layer of metal thin film or transparent conductive film are grown, as gate electrode layer；
4) photoetching and the described gate electrode layer of etching and described gate dielectric layer, form gate electrode and gate medium；
5) at atmospheric pressure and room temperature the substrate that deposited described active layer, described gate medium and described gate electrode is placed in electrolyte, the described active layer being exposed in described electrolyte is carried out hydrogen loading process by the method for electrolysis water；
6) by photoetching and the described active layer of etching, the active area comprising source region, drain region and channel region is formed；Described channel region is made up of the described active layer processed without electrochemistry hydrogen loading, and described channel region is positioned at immediately below gate medium, and described source region and described drain region are formed by the described active layer processed through electrochemistry hydrogen loading and lay respectively at described channel region both sides；
7) on described substrate, described gate electrode, described source region and described drain region, cover one layer of insulating medium layer, described insulating medium layer is positioned at described source region side and side, described drain region and uses photoetching and etching, form two contact holes of electrode；
8) the upper surface deposit layer of metal film in described insulating medium layer, the described source region of exposure and described drain region, uses photoetching and is etched into source region Metal contact electrode and drain region Metal contact electrode.
The preparation method of a kind of self-aligned thin film transistor the most as claimed in claim 4, it is characterized in that: in described step 4), the preparation method of described gate electrode and described gate medium is: spin coating photoresist on whole described gate electrode layer, pass through single exposure, development, etch described gate electrode layer and the described gate dielectric layer being positioned under described gate electrode layer continuously, form described gate electrode and described gate medium, described gate electrode is identical with the litho pattern of described gate medium, and described gate medium is positioned at the underface of described gate electrode.
The preparation method of a kind of self-aligned thin film transistor the most as claimed in claim 4, it is characterized in that: described step 5) is to carry out in dual-electrode electrolysis pond at atmospheric pressure and room temperature, described electrolyte uses water, aqueous solution containing electrolyte, or water and the mixed liquor of organic solution, described active layer is connected with the negative pole of external power source, as negative electrode, the water electrolysis in electrolyte forms hydrion, moves and enter the described active layer being exposed in described electrolyte to described active layer.
The preparation method of a kind of self-aligned thin film transistor the most as claimed in claim 4, it is characterized in that: in described step 4)～step 5), photoetching and the described gate electrode layer of etching and described gate dielectric layer, form described gate electrode and described gate medium, cover after the photoresist of described surface gate electrode after removing etching, then carry out hydrogen loading process.
The preparation method of a kind of self-aligned thin film transistor the most as claimed in claim 4, it is characterized in that: in described step 4)～step 5), photoetching and the described gate electrode layer of etching and described gate dielectric layer, form described gate electrode and described gate medium, the photoresist at described surface gate electrode is covered after retaining etching, carrying out hydrogen loading process again, hydrogen loading removes after processing and covers the described photoresist at described surface gate electrode.
The preparation method of a kind of self-aligned thin film transistor the most as claimed in claim 4, it is characterised in that: in described step 1)～step 3), active layer, described gate dielectric layer and described gate electrode layer described in consecutive deposition successively on described substrate.
10. a self-aligned thin film transistor, it is characterised in that including:
Substrate；
Active layer, described active layer is created on described substrate, and described active layer is oxide semiconductor thin-film, and described active layer includes source region, drain region and the channel region obtained after hydrogen loading process, photoetching and etching；
Gate medium, described gate medium is created on described active layer, and described gate dielectric layer is obtained by photoetching and etching dielectric；
Gate electrode, described gate electrode is created on described gate medium, and described gate electrode is obtained by photoetching and etching metallic film or transparent conductive film；
Insulating medium layer, is covered on described substrate, described gate electrode, described source region and described drain region；
Source region Metal contact electrode and drain region Metal contact electrode, described source region Metal contact electrode contacts with described source region and described insulating medium layer, described drain region Metal contact electrode contacts with described drain region and described insulating medium layer, and described source region Metal contact electrode and described drain region Metal contact electrode are made by metal membrane material.
CN201610451662.XA 2016-06-21 2016-06-21 Self-aligned thin-film transistor and preparation method thereof Pending CN105977306A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019109310A1 (en) * 2017-12-07 2019-06-13 深圳市柔宇科技有限公司 Thin film transistor and manufacturing method thereof, array substrate, and display device
CN110660864A (en) * 2018-06-29 2020-01-07 山东大学苏州研究院 High-frequency semiconductor thin film field effect transistor and preparation method thereof
CN111415993A (en) * 2020-03-16 2020-07-14 中国科学院微电子研究所 Multi-medium detection sensor and manufacturing method thereof
CN111682074A (en) * 2020-06-24 2020-09-18 中国科学院微电子研究所 Coplanar indium gallium zinc oxide thin film transistor and preparation method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1078068A (en) * 1992-04-07 1993-11-03 株式会社半导体能源研究所 Form the method for semiconductor device
CN101401213A (en) * 2006-03-17 2009-04-01 佳能株式会社 Field effect transistor using oxide film for channel and method of manufacturing the same
US20140306181A1 (en) * 2013-04-16 2014-10-16 Lg Electronics Inc. Nitride semiconductor device and fabricating method thereof
CN105006487A (en) * 2015-07-14 2015-10-28 北京大学 Top gate self-aligned metal oxide semiconductor thin-film transistor and preparation method thereof
CN105206677A (en) * 2015-07-03 2015-12-30 友达光电股份有限公司 Oxide semiconductor thin film transistor and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1078068A (en) * 1992-04-07 1993-11-03 株式会社半导体能源研究所 Form the method for semiconductor device
CN101401213A (en) * 2006-03-17 2009-04-01 佳能株式会社 Field effect transistor using oxide film for channel and method of manufacturing the same
US20140306181A1 (en) * 2013-04-16 2014-10-16 Lg Electronics Inc. Nitride semiconductor device and fabricating method thereof
CN105206677A (en) * 2015-07-03 2015-12-30 友达光电股份有限公司 Oxide semiconductor thin film transistor and manufacturing method thereof
CN105006487A (en) * 2015-07-14 2015-10-28 北京大学 Top gate self-aligned metal oxide semiconductor thin-film transistor and preparation method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019109310A1 (en) * 2017-12-07 2019-06-13 深圳市柔宇科技有限公司 Thin film transistor and manufacturing method thereof, array substrate, and display device
CN110660864A (en) * 2018-06-29 2020-01-07 山东大学苏州研究院 High-frequency semiconductor thin film field effect transistor and preparation method thereof
CN111415993A (en) * 2020-03-16 2020-07-14 中国科学院微电子研究所 Multi-medium detection sensor and manufacturing method thereof
CN111415993B (en) * 2020-03-16 2023-11-21 中国科学院微电子研究所 Multi-medium detection sensor and manufacturing method thereof
CN111682074A (en) * 2020-06-24 2020-09-18 中国科学院微电子研究所 Coplanar indium gallium zinc oxide thin film transistor and preparation method thereof

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