CN105552114A - Thin film transistor based on amorphous oxide semiconductor material and preparation method thereof - Google Patents
Thin film transistor based on amorphous oxide semiconductor material and preparation method thereof Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 48
- 239000000463 material Substances 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000002360 preparation method Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 230000008569 process Effects 0.000 claims abstract description 18
- 238000002161 passivation Methods 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 120
- 229910052751 metal Inorganic materials 0.000 claims description 51
- 239000002184 metal Substances 0.000 claims description 51
- 239000010408 film Substances 0.000 claims description 33
- 238000000137 annealing Methods 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 18
- 239000012212 insulator Substances 0.000 claims description 16
- 239000000203 mixture Substances 0.000 claims description 15
- 239000000126 substance Substances 0.000 claims description 15
- 238000004544 sputter deposition Methods 0.000 claims description 14
- 230000008021 deposition Effects 0.000 claims description 13
- 239000007789 gas Substances 0.000 claims description 13
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 12
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 12
- 238000009413 insulation Methods 0.000 claims description 11
- 229910006404 SnO 2 Inorganic materials 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- 229910052750 molybdenum Inorganic materials 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 229910000838 Al alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 229910052786 argon Inorganic materials 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 6
- 239000002356 single layer Substances 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- VAJVDSVGBWFCLW-UHFFFAOYSA-N 3-Phenyl-1-propanol Chemical compound OCCCC1=CC=CC=C1 VAJVDSVGBWFCLW-UHFFFAOYSA-N 0.000 claims description 3
- 229910001316 Ag alloy Inorganic materials 0.000 claims description 3
- 229910000599 Cr alloy Inorganic materials 0.000 claims description 3
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- PMPVIKIVABFJJI-UHFFFAOYSA-N Cyclobutane Chemical compound C1CCC1 PMPVIKIVABFJJI-UHFFFAOYSA-N 0.000 claims description 3
- 229910001182 Mo alloy Inorganic materials 0.000 claims description 3
- DYUQAZSOFZSPHD-UHFFFAOYSA-N Phenylpropyl alcohol Natural products CCC(O)C1=CC=CC=C1 DYUQAZSOFZSPHD-UHFFFAOYSA-N 0.000 claims description 3
- 239000004642 Polyimide Substances 0.000 claims description 3
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 3
- 229910001080 W alloy Inorganic materials 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
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- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 19
- 230000006378 damage Effects 0.000 abstract description 5
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- UZLYXNNZYFBAQO-UHFFFAOYSA-N oxygen(2-);ytterbium(3+) Chemical compound [O-2].[O-2].[O-2].[Yb+3].[Yb+3] UZLYXNNZYFBAQO-UHFFFAOYSA-N 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000010944 silver (metal) Substances 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 2
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- 239000010937 tungsten Substances 0.000 description 2
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- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
- H01L29/247—Amorphous materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
Abstract
The present invention discloses a thin film transistor based on an amorphous oxide semiconductor material and a preparation method thereof. The thin film transistor comprises a substrate, a gate, a gate insulating layer, an active layer, source and drainage electrodes and a passivation layer from a bottom to a top. The active layer is an amorphous oxide SiSnO thin film. According to the etching type thin film transistor structure based on a back channel of the invention, the amorphous oxide SiSnO is introduced as the active layer. The oxide has strong etch-resistant ability, the damage of the thin film transistor back channel can be greatly reduced in the process of etching the source and drainage electrodes, and the threshold voltage is good. By using the back channel etching type thin film transistor prepared by the invention, the stability is greatly enhanced, the requirement of thin film transistor productivization is satisfied, and the application value is high.
Description
Technical field
The invention belongs to field of semiconductor manufacture, particularly relate to a kind of thin-film transistor based on amorphous oxide semiconductor material and preparation method thereof.
Background technology
In recent years, novel flat-plate display (FPD) industry development is swift and violent.Consumer stimulates whole industry constantly to promote Display Technique for the high demand of large scale, high resolution flat display.And as thin-film transistor (TFT) backplane technology of FPD industry core technology, also experiencing deep change.
Traditional amorphous silicon (a-Si) TFT (is generally less than 0.5cm because mobility is lower
2/ (Vs)), be difficult to realize high-resolution display, be faced with by the destiny of market; Low temperature polycrystalline silicon (LTPS) is although the high (50 ~ 150cm of TFT mobility
2/ (Vs)), but on the one hand complex manufacturing, equipment investment are expensive, there is the problems such as lack of homogeneity, yields are low on the one hand, cause LTPS to have difficulty in taking a step further developing of large scale FPD field in large scale display.By contrast, oxide TFT not only has higher mobility (at 5 ~ 50cm
2/ (Vs) left and right), manufacture craft is simple, and manufacturing cost is lower, and has excellent large-area uniformity.Therefore oxide TFT technology has just attracted much industry attention since birth.
The structure that current oxide TFT mainly uses has back of the body channel etching structure and etching barrier layer structure.Back of the body channel etching structure is after generation active layer, directly photoetching source-drain electrode on active layer.And etching barrier layer structure be active layer generate after, first photoetching one deck etching barrier layer, then on again deposition and photolithographic source drain electrode.
Back of the body channel etching structure fabrication processes is comparatively simple, and identical with traditional amorphous silicon manufacture craft, and equipment investment and production cost are all cheaper.This structure is considered to, and amorphous oxide thin film transistor realizes scale of mass production and can widely used inevitable development direction.But when etching source-drain electrode on active layer, oxide can be subject to ion dam age, cause the channel surface exposed to have carrier traps to generate and oxygen vacancy concentration increase, thus make device stability poor.The oxide TFT of this structure also cannot realize commercialization.
On the other hand, use the oxide TFT of etching barrier layer structure can avoid the problems referred to above largely, therefore its stability is relatively good, this configuration thin film transistor commercialization at present.But because it needs to increase extra lithography mask version make etching barrier layer, cause complex process, cost of manufacture is high.
Summary of the invention
In order to overcome the shortcoming of prior art with not enough, primary and foremost purpose of the present invention is to provide a kind of thin-film transistor based on amorphous oxide semiconductor material.This thin-film transistor is using amorphous oxide semiconductor material as active layer material, and this new oxide is relative to traditional oxide etch resistant more, and make the stability of device stronger, performance is better.
Another object of the present invention is to provide the preparation method of the described thin-film transistor based on amorphous oxide semiconductor material.
Object of the present invention is achieved through the following technical solutions:
Based on a thin-film transistor for amorphous oxide semiconductor material, comprise substrate, grid, gate insulator, active layer, source-drain electrode and passivation layer successively from the bottom to top;
Described active layer is using amorphous oxides SiSnO film as active layer.
The semi-conducting material of described active layer is amorphous tin Si oxide (SiO
2)
x(SnO
2)
y, SiO
2and SnO
2weight ratio be (5 ~ 15): (85 ~ 95) wt%; Be preferably 5: 95wt%.
The thickness of described active layer is 5nm ~ 30nm; Be more preferably 10nm ~ 30nm;
Optionally, described substrate comprises: the glass substrate with resilient coating, or the flexible substrate with water oxygen barrier layer;
Optionally, described flexible substrate comprises: PEN, PET, PI or metal forming;
Described grid is metal conducting layer, and the metal that described metal conducting layer uses comprises:
Aluminium (Al), copper (Cu), molybdenum (Mo), titanium (Ti), silver (Ag), gold (Au), tantalum (Ta), tungsten (W), chromium (Cr) simple substance or aluminium alloy;
Described metal conducting layer is single layer metal firms, or by individual layer Al, the plural layers of any two-layer above composition in Cu, Mo, Ti, Ag, Au, Ta, W, Cr or aluminium alloy;
The thickness of described grid is 100nm ~ 2000nm;
Described gate insulator is based on SiO
2, Si
3n
4, Al
2o
3, tantalum pentoxide (Ta
2o
5) or ytterbium oxide (Y
2o
3) single thin film of insulation film, or the plural layers of above insulating material composition;
The thickness of described gate insulator is 50nm ~ 500nm;
Optionally, the metal that described source-drain electrode uses comprises: Al, Cu, Mo, Ti simple substance, or more state the alloy material of metal simple-substance as main body;
Described source-drain electrode is single layer metal firms, or by individual layer Al, Cu, Mo, Ti simple substance, or more state the plural layers of metal simple-substance as any two-layer above composition of alloy material of main body;
The thickness of described source-drain electrode is 100nm ~ 2000nm;
Optionally, the material of described passivation layer is SiO
2, Si
3n
4, Al
2o
3, Y
2o
3, polyimides, photoresist, phenylpropyl alcohol cyclobutane or polymethyl methacrylate, or the plural layers of above insulating material composition; Described passivation layer thickness is 50nm ~ 2000nm.
Based on a preparation method for the thin-film transistor of amorphous oxide semiconductor material, comprise the steps:
(1) on substrate preparation and patterned metal conductive layer as grid;
(2) on described metal conducting layer, insulation film is deposited as gate insulator;
(3) on described gate insulator, deposited amorphous oxide S iSnO film is also graphical, as active layer;
(4) depositing metal layers on described active layer, is then patterned into as source-drain electrode figure; Due to the existence of SiSnO film, make when carrying out back of the body channel etching, the damage of etching process to active layer alleviates greatly;
(5) on described source-drain electrode, insulation film is deposited as passivation layer; Obtain the thin-film transistor based on amorphous oxide semiconductor material.
Described active layer passes through radio frequency sputtering; Sputtering power is 140 ~ 300W, and operating pressure is 2mTorr ~ 10mTorr, and sputter gas is argon gas, or argon gas and oxygen mix;
Carry out front annealing in process after described active layer deposition, front annealing temperature is 150 DEG C ~ 450 DEG C, and front annealing time is 5 ~ 60min;
Carry out after annealing process after described source-drain electrode is graphical, after annealing temperature is 150 DEG C ~ 450 DEG C, and the after annealing time is 5 ~ 60min.
The present invention has following advantage and effect relative to prior art:
The present invention is based on back of the body channel-etch type thin film transistor structure, introduce amorphous tin Si oxide SiSnO as active layer.The anti-etching ability of this oxide is strong, can greatly reduce the damage to thin-film transistor back of the body raceway groove in the process of etching source-drain electrode, and threshold voltage is better.Use the present invention to make back of the body channel-etch type thin film transistor stability greatly to promote, meet the requirement of thin-film transistor commercialization, therefore there is very high using value.
Accompanying drawing explanation
Fig. 1 is the TFT structure schematic diagram under fabrication processing the 1st step.
Fig. 2 is the TFT structure schematic diagram under fabrication processing the 2nd step.
Fig. 3 is the TFT structure schematic diagram under fabrication processing the 3rd step.
Fig. 4 is the TFT structure schematic diagram under fabrication processing the 4th step, now completes the deposition of metal level.
Fig. 5 is the TFT structure schematic diagram under fabrication processing the 4th step, now patterned source-drain electrode.
Fig. 6 is the TFT structure schematic diagram under fabrication processing the 5th step.
Wherein, 01 is substrate; 02 is the metal conducting layer as grid; 03 is the insulation film as gate insulator; 04 is the amorphous SiSnO sull as active layer; 05 is the metal level of source-drain electrode; 06 is source-drain electrode; 07 is the insulation film as passivation layer.
Fig. 7 is that active layer thickness is respectively 10nm, 20nm and 30nm film transistor device results of property figure; Wherein, Fig. 7 A is 10nm; Fig. 7 B is 20nm; Fig. 7 C is 30nm.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
Embodiment 1
A preparation method for thin-film transistor, comprises following operation:
(1) on substrate preparation and patterned metal conductive layer as grid; ;
(2) on described metal conducting layer, insulation film is deposited as gate insulator;
(3) on described gate insulator, deposited amorphous oxide S iSnO film is also graphical, as active layer;
(4) depositing metal layers on described active layer, is then patterned into as source-drain electrode figure; Due to the existence of SiSnO film, make when carrying out back of the body channel etching, the damage of etching process to active layer alleviates greatly;
(5) on described source-drain electrode, insulation film is deposited as passivation layer; Obtain the thin-film transistor based on amorphous oxide semiconductor material.
Described active layer passes through radio frequency sputtering; Sputtering power is 140 ~ 300W, and operating pressure is 2mTorr ~ 10mTorr, and sputter gas is argon gas, or argon gas and oxygen mix;
Carry out front annealing in process after described active layer deposition, front annealing temperature is 150 DEG C ~ 450 DEG C, and front annealing time is 5 ~ 60min;
Carry out after annealing process after described source-drain electrode is graphical, after annealing temperature is 150 DEG C ~ 450 DEG C, and the after annealing time is 5 ~ 60min.
Described active layer is using amorphous oxides SiSnO film as active layer.
The semi-conducting material of described active layer is amorphous tin Si oxide (SiO
2)
x(SnO
2)
y, SiO
2and SnO
2weight ratio be (5 ~ 15): (85 ~ 95) wt%; Be preferably 5: 95wt%.
The thickness of described active layer is 5nm ~ 30nm;
Optionally, described substrate comprises: the glass substrate with resilient coating, or the flexible substrate with water oxygen barrier layer;
Optionally, described flexible substrate comprises: PEN, PET, PI or metal forming;
Described grid is metal conducting layer, and the metal that described metal conducting layer uses comprises:
Aluminium (Al), copper (Cu), molybdenum (Mo), titanium (Ti), silver (Ag), gold (Au), tantalum (Ta), tungsten (W), chromium (Cr) simple substance or aluminium alloy;
Described metal conducting layer is single layer metal firms, or by individual layer Al, the plural layers of any two-layer above composition in Cu, Mo, Ti, Ag, Au, Ta, W, Cr or aluminium alloy;
The thickness of described grid is 100nm ~ 2000nm;
Described gate insulator is based on SiO
2, Si
3n
4, Al
2o
3, tantalum pentoxide (Ta
2o
5) or ytterbium oxide (Y
2o
3) single thin film of insulation film, or the plural layers of above insulating material composition;
The thickness of described gate insulator is 50nm ~ 500nm;
Optionally, the metal that described source-drain electrode uses comprises: Al, Cu, Mo, Ti simple substance, or more state the alloy material of metal simple-substance as main body;
Described source-drain electrode is single layer metal firms, or by individual layer Al, Cu, Mo, Ti simple substance, or more state the plural layers of metal simple-substance as any two-layer above composition of alloy material of main body;
The thickness of described source-drain electrode is 100nm ~ 2000nm;
Optionally, the material of described passivation layer is SiO
2, Si
3n
4, Al
2o
3, Y
2o
3, polyimides, photoresist, phenylpropyl alcohol cyclobutane or polymethyl methacrylate, or the plural layers of above insulating material composition; Described passivation layer thickness is 50nm ~ 2000nm.
As shown in Figure 1, the SiO with 200nm is used
2the alkali-free glass of resilient coating is as substrate 01.Use PVD (PhysicalVaporDeposition) method to deposit Mo/Al/Mo three-layer metal film successively, thickness is respectively 25nm/100nm/25nm.Use photoetching process that it is graphically formed gate metal conductive layer 02.It should be noted that, the thickness range of metal conducting layer is within the scope of 100nm ~ 2000nm, and its concrete size can be arranged according to actual needs flexibly, is not limited to the size of the present embodiment.The constituent material of metal conducting layer is also not limited to the situation of the present embodiment.
As shown in Figure 2, on patterned Gate Electrode Conductive metal level, use PECVD method (PlasmaEnhancedChemicalVaporDeposition) depositing insulating films, dielectric film is by the SiN of 300nm
xwith the SiO of 30nm
2lamination forms as gate insulator 03.It should be noted that, the thickness range of the first insulating film layer is within the scope of 50nm ~ 500nm, and its concrete size can be arranged according to actual needs flexibly, is not limited to the size of the present embodiment.The constituent material of the first insulating film layer is also not limited to the situation of the present embodiment.
As shown in Figure 3, radio frequency sputtering method deposition 10nm, 20nm, 30nm (sample A1, A2, A3) amorphous oxides SiSnO film (SiO is used respectively
2: SnO
2=5%:95wt%)) as active layer 04, sputtering power is 140w, operating pressure is 2mTorr, sputter gas Ar: O
2=25: 0sccm.It should be noted that, the thickness range of active layer is within the scope of 5nm ~ 30nm, and its concrete size can be arranged according to actual needs flexibly, is not limited to the size of the present embodiment.After deposition, with 330 DEG C of after annealing process 0.5 hour.The results are shown in Table 1.Fig. 7 is that active layer thickness is respectively 10nm, 20nm and 30nm film transistor device results of property figure.
The performance parameter of table 1 sample A1, A2, A3
| Sample | Mobility (cm 2/Vs) | Threshold voltage (V) | Switch current ratio Ion/Ioff |
| A1 | 6.81 | 0.8 | 1.2e6 |
| A2 | 10.22 | 3.8 | 1.1e5 |
| A3 | 10.19 | -8.5 | 3.4e5 |
Embodiment 2
A preparation method for thin-film transistor, with reference to embodiment 1.Difference is active layer.
As shown in Figure 3, radio frequency sputtering method deposition 10nm amorphous oxides SiSnO film (SiO is used
2: SnO
2=5%:95wt%)) as active layer 04, sputtering power is 300w, operating pressure is 5mTorr, and the ratio of sputter gas is respectively Ar: O
2=60: 0sccm, 60:3sccm, 60:6sccm (sample B1, B2, B3).After deposition, with 300 DEG C of after annealing process 0.5 hour.The results are shown in Table 2.
The performance parameter of table 2 sample B1, B2, B3
| Sample | Mobility (cm 2/Vs) | Carrier concentration (cm -3) |
| B1 | 2.65 | 6.75E+19 |
| B2 | 3.38 | 9.32E+19 |
| B3 | 2.58 | 8.44E+19 |
Embodiment 3
A preparation method for thin-film transistor, with reference to embodiment 1.Difference is active layer.
As shown in Figure 3, radio frequency sputtering method deposition 10nm amorphous oxides SiSnO film (SiO is used
2: SnO
2=5%:95wt%)) as active layer 04, sputtering power is 300w, operating pressure is respectively 2mTorr, 5mTorr, 10mTorr (sample C1, C2, C3), and the ratio of sputter gas is respectively Ar: O
2=20: 2sccm, 60:6sccm, 90:9sccm.After deposition, with 300 DEG C of after annealing process 0.5 hour.The results are shown in Table 3.
The performance parameter of table 3 sample C1, C2, C3
| Sample | Mobility (cm 2/Vs) | Carrier concentration (cm -3) |
| C1 | 7.08 | 2.97E+19 |
| C2 | 2.58 | 8.44E+19 |
| C3 | 1.24 | 4.38E+19 |
Embodiment 4
A preparation method for thin-film transistor, with reference to embodiment 1.Difference is active layer.
As shown in Figure 3, radio frequency sputtering method deposition 10nm amorphous oxides SiSnO film (SiO is used
2: SnO
2=5%:95wt%)) as active layer 04, sputtering power is 300w, operating pressure is 2mTorr, and the ratio of sputter gas is Ar: O
2=60: 0sccm.After deposition, respectively with 150 DEG C, 250 DEG C, 350 DEG C, 450 DEG C (sample D1, D2, D3, D4) after annealing process 0.5 hour.The results are shown in Table 4.
The performance parameter of table 4 sample D1, D2, D3, D4
| Sample | Active layer Film roughness RMS (nm) | Active layer film relative density ρ (%) |
| D1 | 0.18 | 92.6 |
| D2 | 0.19 | 99.9 |
| D3 | 0.09 | 103.2 |
| D4 | 0.09 | 104.7 |
Embodiment 5
A preparation method for thin-film transistor, with reference to embodiment 1.
Depositing metal layers on described active layer, use PVD (PhysicalVaporDeposition) method to deposit Mo/Al/Mo three-layer metal film successively, thickness is respectively 25nm/100nm/25nm, forms the metal level 05 of source-drain electrode, as shown in Figure 4.And use the H of 30%
2o
2with 1% KOH as wet etching liquid, Mo and Al respectively in etching stack metal.Use the method to have and Mo/Al/Mo is graphically formed source-drain electrode 06, as shown in Figure 5.
Described source-drain electrode uses the SiO that PECVD deposit thickness is 300nm
2as passivation layer 07, as shown in Figure 6.Complete the making of thin-film transistor.
The thin-film transistor that this technique makes, may be used for liquid crystal display LCD (LiquidCrystalDisplay) and active-matrix organic light emitting diode (AMOLED) panel AMOLED (ActiveMatrix/OrganicLightEmittingDiode) field.
In sum, preparation technology of the present invention, has preparation technology simple, the features such as prepared thin-film transistor good stability, can realize thin-film transistor and drive the high-precision refinement of backboard, low-cost production.
It should be noted that, the size related in the present embodiment, ratio do not limit the preparation technology of thin-film transistor of the present invention, and in actual fabrication process, user can adjust according to specific needs flexibly.
Above-described embodiment is the present invention's preferably execution mode; but embodiments of the present invention are not restricted to the described embodiments; change, the modification done under other any does not deviate from Spirit Essence of the present invention and principle, substitute, combine, simplify; all should be the substitute mode of equivalence, be included within protection scope of the present invention.
Claims (10)
1. based on a thin-film transistor for amorphous oxide semiconductor material, it is characterized in that: comprise substrate, grid, gate insulator, active layer, source-drain electrode and passivation layer successively from the bottom to top;
Described active layer is using amorphous oxides SiSnO film as active layer.
2. the thin-film transistor based on amorphous oxide semiconductor material according to claim 1, is characterized in that: the semi-conducting material of described active layer is amorphous tin Si oxide (SiO
2)
x(SnO
2)
y, SiO
2and SnO
2weight ratio be (5 ~ 15): (85 ~ 95) wt%;
The thickness of described active layer is 5nm ~ 30nm.
3. the thin-film transistor based on amorphous oxide semiconductor material according to claim 1, is characterized in that: described substrate comprises: the glass substrate with resilient coating, or the flexible substrate with water oxygen barrier layer;
Described flexible substrate comprises: PEN, PET, PI or metal forming.
4. the thin-film transistor based on amorphous oxide semiconductor material according to claim 1, is characterized in that: described grid is metal conducting layer, and the metal that described metal conducting layer uses comprises: Al, Cu, Mo, Ti, Ag, Au, Ta, W, Cr simple substance or aluminium alloy;
Described metal conducting layer is single layer metal firms, or by individual layer Al, the plural layers of any two-layer above composition in Cu, Mo, Ti, Ag, Au, Ta, W, Cr or aluminium alloy;
The thickness of described grid is 100nm ~ 2000nm.
5. the thin-film transistor based on amorphous oxide semiconductor material according to claim 1, is characterized in that: described gate insulator is based on SiO
2, Si
3n
4, Al
2o
3, Ta
2o
5or Y
2o
3the single thin film of insulation film, or the plural layers of above insulating material composition;
The thickness of described gate insulator is 50nm ~ 500nm.
6. the thin-film transistor based on amorphous oxide semiconductor material according to claim 1, is characterized in that: the metal that described source-drain electrode uses comprises: Al, Cu, Mo, Ti simple substance, or more state the alloy material of metal simple-substance as main body;
Described source-drain electrode is single layer metal firms, or by individual layer Al, Cu, Mo, Ti simple substance, or more state the plural layers of metal simple-substance as any two-layer above composition of alloy material of main body;
The thickness of described source-drain electrode is 100nm ~ 2000nm.
7. the thin-film transistor based on amorphous oxide semiconductor material according to claim 1, is characterized in that: the material of described passivation layer is SiO
2, Si
3n
4, Al
2o
3, Y
2o
3, polyimides, photoresist, phenylpropyl alcohol cyclobutane or polymethyl methacrylate, or the plural layers of above insulating material composition;
Described passivation layer thickness is 50nm ~ 2000nm.
8. the preparation method of the thin-film transistor based on amorphous oxide semiconductor material described in any one of claim 1 ~ 7, is characterized in that comprising the steps:
(1) on substrate preparation and patterned metal conductive layer as grid;
(2) on described metal conducting layer, insulation film is deposited as gate insulator;
(3) on described gate insulator, deposited amorphous oxide S iSnO film is also graphical, as active layer;
(4) depositing metal layers on described active layer, is then patterned into as source-drain electrode figure;
(5) on described source-drain electrode, insulation film is deposited as passivation layer; Obtain the thin-film transistor based on amorphous oxide semiconductor material.
9. the preparation method of the thin-film transistor based on amorphous oxide semiconductor material according to claim 8, is characterized in that:
Described active layer passes through radio frequency sputtering; Sputtering power is 140 ~ 300W, and operating pressure is 2mTorr ~ 10mTorr, and sputter gas is argon gas, or argon gas and oxygen mix.
10. the preparation method of the thin-film transistor based on amorphous oxide semiconductor material according to claim 8, is characterized in that:
Carry out front annealing in process after described active layer deposition, front annealing temperature is 150 DEG C ~ 450 DEG C, and front annealing time is 5 ~ 60min;
Carry out after annealing process after described source-drain electrode is graphical, after annealing temperature is 150 DEG C ~ 450 DEG C, and the after annealing time is 5 ~ 60min.
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| CN107170833A (en) * | 2017-06-14 | 2017-09-15 | 华南理工大学 | A kind of amorphous oxide thin film transistor and preparation method thereof |
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