WO2019095408A1

WO2019095408A1 - Array substrate, manufacturing method thereof, and display panel

Info

Publication number: WO2019095408A1
Application number: PCT/CN2017/112188
Authority: WO
Inventors: 张鹏振
Original assignee: 武汉华星光电半导体显示技术有限公司
Priority date: 2017-11-14
Filing date: 2017-11-21
Publication date: 2019-05-23
Also published as: CN107833893A

Abstract

Provided is an array substrate, comprising a glass substrate (1), a buffer layer (2), a semiconductor layer (3), a gate insulation layer (4), a gate (5), an interlayer insulation layer (6), a source (7), a drain (8), a flat layer (9), a common electrode (10), a passivation layer (11), and a pixel electrode (12). Also provided are a manufacturing method of an array substrate, and a display panel. The invention adopts a top-gate self-aligned structure capable of reducing parasitic capacitance in order to reduce the size of an overlapping portion between the source and drain and the gate, thereby improving the aperture ratio and the capacity of a storage capacitor while reducing the area occupied by the storage capacitor. In addition, the invention reduces the parasitic capacitance of a thin film transistor device, leading to a lower RC delay and an improved response speed of the thin film transistor device.

Description

Array substrate and manufacturing method thereof, display panel

Technical field

The invention relates to a display panel technology, in particular to an array substrate, a manufacturing method thereof and a display panel.

Background technique

IGZO (In-Ga-Zn-O, indium gallium zinc oxide) has the advantages of high mobility and large-area production, and has become a strong competitor for next-generation display technology, and is mostly used for "in-plane conversion" (IPS). )technology. In the IPS technology, the passivation layer in the TFT (thin film transistor) structure not only bridges the drain electrode and the pixel electrode, but also the dielectric protection layer between the storage capacitor plates, but this affects the storage due to the presence of leakage current. Capacitance capacity and pixel stability, and in order to solve this problem, it is often used to reduce the area occupied by the storage capacitor, but this method will reduce the aperture ratio.

Summary of the invention

In order to overcome the deficiencies of the prior art, the present invention provides an array substrate, a manufacturing method thereof, and a display panel, thereby improving an aperture ratio and a storage capacitor size while reducing an area occupied by the storage capacitor.

The invention provides an array substrate comprising a glass substrate, a buffer layer, a semiconductor layer, a gate insulating layer, a gate, an interlayer insulating layer, a source, a drain, a flat layer, a common electrode, a passivation layer, and a pixel electrode. ;among them,

a buffer layer is formed on the substrate; a semiconductor layer is formed on the buffer layer; the semiconductor layer includes an active region and a source region and a drain region disposed on both sides of the active region, wherein the gate insulating layer and the gate are sequentially Formed on the active region; the interlayer insulating layer is formed on a buffer layer, a source region, and a drain region that are not blocked by the semiconductor layer; and the interlayer insulating layer is formed at a corresponding source region and a drain region a first via hole; the source and the drain are respectively in contact with the source region and the drain region via the first via hole; the flat layer is formed at the source and the drain, and is not blocked by the source and the drain On the interlayer insulating layer; the common electrode is formed on the flat layer, and the passivation layer is formed on the common electrode and the flat layer not blocked by the common electrode, and the passivation layer and the corresponding drain on the flat layer are formed on the same a second via hole, the third via hole; the pixel electrode is formed on the passivation layer and is in contact with the drain via the second via hole and the third via hole.

Further, the semiconductor layer is made of indium gallium zinc oxide.

Further, the passivation layer is made of yttrium oxide.

The invention also provides a display panel comprising the oxide array substrate.

The invention also provides a method for fabricating an array substrate, comprising the following steps:

Providing a substrate;

Forming a buffer layer on the substrate;

Forming a semiconductor layer on the buffer layer;

Forming a gate insulating layer and a gate electrode sequentially on the active region of the semiconductor layer;

Forming an interlayer insulating layer on the buffer layer not blocked by the semiconductor layer, the source region, the drain region, and the gate of the semiconductor layer;

Forming a first via hole on the corresponding interlayer region and the drain region on the interlayer insulating layer;

a source and a drain are respectively formed on the interlayer insulating layer, and the source and the drain are respectively in contact with the source region and the drain region via the first via hole;

Forming a flat layer on the interlayer insulating layer, the source and the drain, which are not blocked by the source and the drain;

Forming a common electrode on the flat layer;

Forming a passivation layer on the common electrode and on the flat layer not blocked by the common electrode;

Forming a second via hole and a third via hole respectively on the passivation layer and the corresponding drain on the flat layer;

A pixel electrode is formed on the passivation layer, and the pixel electrode is in contact with the drain via the second via hole and the third via hole.

Further, the forming a semiconductor layer on the buffer layer comprises depositing an amorphous indium gallium zinc oxide film on the buffer layer and patterning the amorphous indium gallium zinc oxide film to obtain a semiconductor layer.

Further, the material of the passivation layer is selected from the group consisting of cerium oxide.

Further, the material of the interlayer insulating layer is at least one selected from the group consisting of silicon oxide and silicon nitride.

Further, when the material of the interlayer insulating layer is selected from silicon oxide, the source region and the drain region of the semiconductor layer are plasma-treated after the gate is formed on the gate insulating layer.

Further, the plasma treatment employs an H ₂ plasma or an Ar plasma.

Compared with the prior art, the present invention adopts a top gate self-aligned structure capable of reducing parasitic capacitance, so that the overlapping portion between the source drain and the gate is reduced, thereby improving the area occupied by the storage capacitor. The aperture ratio and the size of the storage capacitor; and the parasitic capacitance of the thin film transistor device is reduced to reduce the RC (Resistance-Capacitance) delay, and the response speed of the thin film transistor device is improved.

DRAWINGS

Figure 1 is a schematic view of the structure of the present invention;

2 is a schematic view showing the fabrication of a semiconductor layer on a buffer layer of the present invention;

3 is a schematic view showing a gate insulating layer and a gate electrode formed by the present invention;

Figure 4 is a schematic view showing the formation of an interlayer insulating layer of the present invention;

Figure 5 is a schematic view showing the fabrication of the source and the drain of the present invention;

Figure 6 is a schematic view showing the formation of a flat layer and a common electrode of the present invention;

Figure 7 is a schematic illustration of the fabrication of a passivation layer in accordance with the present invention.

Detailed ways

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

As shown in FIG. 1, an oxide array substrate of the present invention includes a glass substrate 1 and a buffer layer 2, a semiconductor layer 3, a gate insulating layer 4, a gate electrode 5, an interlayer insulating layer 6, and a source which are sequentially disposed. 7. The drain 8, the flat layer 9, the common electrode 10, the passivation layer 11, and the pixel electrode 12;

The buffer layer 2 is formed on the substrate 1; the substrate may be a glass substrate;

a semiconductor layer 3 is formed on the buffer layer 2; the semiconductor layer 3 is made of indium gallium zinc oxide (IGZO);

The semiconductor layer 3 includes an active region 31 and a source region 32 and a drain region 33 disposed on both sides of the active region 31;

The gate insulating layer 4 and the gate 5 are sequentially formed on the active region 31; the material of the gate insulating layer is silicon oxide (SiOx);

The interlayer insulating layer 6 is formed on the buffer layer 2, the source region 32, and the drain region 33 that are not blocked by the semiconductor layer 3; the material of the interlayer insulating layer 6 is selected from silicon oxide (SiOx), nitrided At least one of silicon (SiNx); specifically, when the material of the interlayer insulating layer 6 is selected from silicon oxide, plasma treatment of the source region 32 and the drain region 33 is also required, and plasma treatment uses H ₂ (hydrogen gas) a plasma or an Ar (argon) plasma;

a first via 61 is formed on the interlayer insulating layer 6 corresponding to the source region 32 and the drain region 33;

The source 7 and the drain 8 are in contact with the source region 32 and the drain region 33 via the first via 61, respectively;

The flat layer 9 is formed on the source 7, the drain 8 and the interlayer insulating layer 6 not blocked by the source 7 and the drain 8;

The common electrode 10 is formed on the flat layer 9;

The passivation layer 11 is formed on the common electrode 10 and the flat layer 9 not blocked by the common electrode 10. The passivation layer 11 and the corresponding drain 8 on the flat layer 9 are formed with a second via 111 and a third via. 91; the passivation layer 11 is made of yttria (Y ₂ O ₃ ) having high dielectric constant and high transmittance, thereby further increasing the storage capacitor size and reducing the storage capacitor area. Improve pixel stability and aperture ratio of thin film transistor devices;

The pixel electrode 12 is formed on the passivation layer 11 and is in contact with the drain 8 via the second via 111 and the third via 91.

The present invention fabricates an array substrate for in-plane switching (IPS) mode by using the above-described top gate self-aligned structure and using a high dielectric constant and high transmittance passivation layer 11 to reduce the occupation of the storage capacitor The area is increased to increase the aperture ratio while increasing the size of the storage capacitor.

The invention also discloses a method for fabricating an array substrate, comprising the following steps:

Step 1: providing a substrate 1; the substrate 1 may be a glass substrate;

Step 2, forming a buffer layer 2 on the substrate 1; specifically, forming a buffer layer by chemical vapor deposition (CVD);

Step 3, forming a semiconductor layer 3 on the buffer layer 2 (as shown in FIG. 3); specifically, depositing an amorphous indium gallium zinc oxide (a-IGZO) film 34 (shown in FIG. 2) by deposition, and then The amorphous indium gallium zinc oxide film 34 is etched by a photolithography process to form a semiconductor layer 3; the semiconductor layer 3 includes an active region 31 and a source region 32 and a drain region 33 provided on both sides of the active region 31. The deposition may be performed by physical vapor deposition (PVD); the photolithography process may be performed using an existing standard photolithography process;

Step 4, sequentially forming a gate insulating layer 4 and a gate 5 on the active region 31 of the semiconductor layer 3 (as shown in FIG. 3); specifically, the gate insulating layer 4 is made of silicon oxide (SiOx) material. Forming a silicon oxide film on the semiconductor layer 3 and the buffer layer 2 not blocked by the semiconductor layer 3 by chemical vapor deposition (CVD); forming a gate electrode film layer on the silicon oxide film by physical vapor deposition (PVD); Applying the same photoresist as the gate pattern on the gate electrode film layer, etching the gate electrode film layer not protected by the photoresist and the silicon oxide film by an etching process, and forming a gate insulating layer on the active region 31 4 and the gate 5; the coating photoresist shown may be spin-coated; the etching process may be dry etching (Dry etch) or wet etching;

Step 5, forming an interlayer insulating layer 6 on the buffer layer 2 not blocked by the semiconductor layer 3, the source region 32 of the semiconductor layer 3, the drain region 33, and the gate electrode 5 (shown in FIG. 4); specifically, An interlayer insulating layer 6 is deposited on the buffer layer 2 not blocked by the semiconductor layer 3, the source region 32 of the oxide semiconductor 3, the drain region 33, and the gate electrode 5 by chemical vapor deposition (CVD). The material of the interlayer insulating layer 6 may be selected from at least one of silicon oxide and silicon nitride;

Step 6, forming a first via 61 on the corresponding source region 32 and the drain region 33 on the interlayer insulating layer 6; specifically, forming a first via 61 by a photolithography process;

Step 7: forming a source 7 and a drain 8 respectively on the interlayer insulating layer 6. The source 7 and the drain 8 are respectively in contact with the source region 32 and the drain region 33 via the first via 61 (FIG. 5). Shown); specifically, Forming an electrode metal film layer on the interlayer insulating layer 6 by physical vapor deposition (PVD), and patterning to form the source electrode 7 and the drain electrode 8 by a photolithography process; the photolithography process may adopt standard existing light The engraving process is carried out, and no specific limitation is made here;

Step 8. A flat layer 9 (shown in FIG. 6) is formed on the interlayer insulating layer 6 not blocked by the source 7 and the drain 8, and the source 7 and the drain 8; specifically, the specificity of the flat layer 9 The fabrication can be implemented by using the flat layer 9 in the thin film transistor array substrate in the prior art, and is not specifically limited herein;

Step 9: forming a common electrode 10 on the flat layer 9 (shown in FIG. 6); specifically, forming a transparent ITO film on the flat layer 9 by physical vapor deposition (PVD), and performing lithography on the ITO film Patterning to form a common electrode 10;

Step 10, forming a passivation layer 11 on the common electrode 10 and on the flat layer 9 not blocked by the common electrode 10 (shown in FIG. 7); specifically, the passivation layer 11 is made of yttria (Y ₂ O ₃ ) material. Specifically, a passivation layer 11 is formed on the common electrode 10 and on the flat layer 9 not blocked by the common electrode 10 by vapor deposition; the vapor deposition may be performed by atomic layer deposition (ALD) or physical vapor deposition. (PVD); the cerium oxide has high dielectric constant and high transmittance, thereby further increasing the storage capacitor size and reducing the storage capacitor area, improving pixel stability and the aperture ratio of the thin film transistor device;

Step 11 : forming a second via 111 and a third via 91 respectively on the passivation layer 11 and the corresponding drain 8 on the flat layer 9; specifically, the passivation layer 11 and the flat layer 9 by a photolithography process Forming a second via 111 and a third via 91 at the drain 8;

Step 12, forming a pixel electrode 12 on the passivation layer 11, the pixel electrode 12 being in contact with the drain 8 via the second via 111 and the third via 91; specifically, using physical vapor deposition (PVD) A transparent ITO film is formed on the passivation layer 11, and the ITO film is patterned by a photolithography process to form a pixel electrode 12, and the pixel electrode 12 passes through the second via 111, the third via 91 and the drain 8. contact.

In the manufacturing method of the present invention, when the material of the interlayer insulating layer 6 is selected from silicon oxide, plasma is also performed on the source region 32 and the drain region 33 of the semiconductor layer 3 after the gate electrode 5 is formed on the gate insulating layer 4. deal with. The plasma treatment uses a H ₂ (hydrogen) plasma or an Ar (argon) plasma.

In the present invention, the passivation layer uses yttrium oxide (Y ₂ O ₃ ) to have excellent heat resistance, corrosion resistance and high temperature stability, high dielectric constant, good transparency, and can be doped with rare earth elements such as Nd ³⁺ . Performance; using a high dielectric constant and a high transmittance Y ₂ O ₃ as a passivation layer, the storage capacitor capacity can be increased while reducing the area of the storage capacitor, thereby increasing the aperture ratio and the transmittance.

The present invention also discloses a display panel including the above array substrate, which will not be described herein.

The invention has the passivation layer material Y ₂ O ₃ with high dielectric constant and high transmittance in the IPS structure, increases the storage capacitor size, reduces the storage capacitor area, improves the pixel stability and the device aperture ratio; The gate self-aligned structure can reduce a mask, make the overlap between the source drain and the gate smaller, and also reduce the parasitic capacitance of the TFT, thereby reducing the RC (Resistance-Capacitance). Delay to improve its response speed.

While the invention has been shown and described with respect to the specific embodiments the embodiments of the invention Various changes in details.

Claims

An array substrate, comprising: a substrate, a buffer layer, a semiconductor layer, a gate insulating layer, a gate, an interlayer insulating layer, a source, a drain, a flat layer, a common electrode, a passivation layer, and a pixel electrode; wherein

a buffer layer is formed on the substrate; a semiconductor layer is formed on the buffer layer; the semiconductor layer includes an active region and a source region and a drain region disposed on both sides of the active region, wherein the gate insulating layer and the gate are sequentially Formed on the active region; the interlayer insulating layer is formed on a buffer layer, a source region, and a drain region that are not blocked by the semiconductor layer; and the interlayer insulating layer is formed at a corresponding source region and a drain region a first via hole; the source and the drain are respectively in contact with the source region and the drain region via the first via hole; the flat layer is formed at the source and the drain, and is not blocked by the source and the drain On the interlayer insulating layer; the common electrode is formed on the flat layer, and the passivation layer is formed on the common electrode and the flat layer not blocked by the common electrode, and the passivation layer and the corresponding drain on the flat layer are formed on the same a second via hole, the third via hole; the pixel electrode is formed on the passivation layer and is in contact with the drain via the second via hole and the third via hole.
The array substrate according to claim 1, wherein the semiconductor layer is made of indium gallium zinc oxide.
The array substrate according to claim 1, wherein the passivation layer is made of ruthenium oxide.
The array substrate according to claim 2, wherein the passivation layer is made of ruthenium oxide.
A display panel, comprising: an array substrate comprising a substrate, a buffer layer, a semiconductor layer, a gate insulating layer, a gate, an interlayer insulating layer, a source, a drain, a flat layer, a common electrode, and a blunt Layer, pixel electrode;

a buffer layer is formed on the substrate; a semiconductor layer is formed on the buffer layer; the semiconductor layer includes an active region and a source region and a drain region disposed on both sides of the active region, wherein the gate insulating layer and the gate are sequentially Formed on the active region; the interlayer insulating layer is formed on a buffer layer, a source region, and a drain region that are not blocked by the semiconductor layer; and the interlayer insulating layer is formed at a corresponding source region and a drain region a first via hole; the source and the drain are respectively in contact with the source region and the drain region via the first via hole; the flat layer is formed at the source and the drain, and is not blocked by the source and the drain On the interlayer insulating layer; the common electrode is formed on the flat layer, and the passivation layer is formed on the common electrode and the flat layer not blocked by the common electrode a second via hole and a third via hole are formed on the passivation layer and the corresponding drain on the flat layer; the pixel electrode is formed on the passivation layer and passes through the second via hole, the third via hole and the drain hole Extreme contact.
The display panel according to claim 5, wherein said semiconductor layer is made of indium gallium zinc oxide.
The display panel according to claim 5, wherein the passivation layer is made of ruthenium oxide.
The display panel according to claim 6, wherein the passivation layer is made of ruthenium oxide.
A method for fabricating an array substrate, comprising: the following steps:

Providing a substrate;

Forming a buffer layer on the substrate;

Forming a semiconductor layer on the buffer layer;

Forming a gate insulating layer and a gate electrode sequentially on the active region of the semiconductor layer;

Forming an interlayer insulating layer on the buffer layer not blocked by the semiconductor layer, the source region, the drain region, and the gate of the semiconductor layer;

Forming a first via hole on the corresponding interlayer region and the drain region on the interlayer insulating layer;

a source and a drain are respectively formed on the interlayer insulating layer, and the source and the drain are respectively in contact with the source region and the drain region via the first via hole;

Forming a flat layer on the interlayer insulating layer, the source and the drain, which are not blocked by the source and the drain;

Forming a common electrode on the flat layer;

Forming a passivation layer on the common electrode and on the flat layer not blocked by the common electrode;

Forming a second via hole and a third via hole respectively on the passivation layer and the corresponding drain on the flat layer;

A pixel electrode is formed on the passivation layer, and the pixel electrode is in contact with the drain via the second via hole and the third via hole.
The method of fabricating an array substrate according to claim 9, wherein: forming the semiconductor layer on the buffer layer comprises depositing an amorphous indium gallium zinc oxide film on the buffer layer and performing an amorphous indium gallium zinc oxide film on the buffer layer. Patterning results in a semiconductor layer.
The method of fabricating an array substrate according to claim 9, wherein the material of the passivation layer is selected from the group consisting of ruthenium oxide.
The method of fabricating an array substrate according to claim 10, wherein the material of the passivation layer is selected from the group consisting of ruthenium oxide.
The method of fabricating an array substrate according to claim 10, wherein the material of the interlayer insulating layer is at least one selected from the group consisting of silicon oxide and silicon nitride.
The method of fabricating an array substrate according to claim 11, wherein when the material of the interlayer insulating layer is selected from silicon oxide, a source region and a drain of the semiconductor layer are formed after the gate is formed on the gate insulating layer. The area is plasma treated.
The method of fabricating an array substrate according to claim 14, wherein the plasma treatment is performed by using an H2 plasma or an Ar plasma.