CN105206677A - Oxide semiconductor thin film transistor and manufacturing method thereof - Google Patents
Oxide semiconductor thin film transistor and manufacturing method thereof Download PDFInfo
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- CN105206677A CN105206677A CN201510580206.0A CN201510580206A CN105206677A CN 105206677 A CN105206677 A CN 105206677A CN 201510580206 A CN201510580206 A CN 201510580206A CN 105206677 A CN105206677 A CN 105206677A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 165
- 239000010409 thin film Substances 0.000 title claims abstract description 81
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000001257 hydrogen Substances 0.000 claims abstract description 231
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 231
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 171
- 150000002431 hydrogen Chemical class 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000000059 patterning Methods 0.000 claims description 65
- 238000000034 method Methods 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 229910044991 metal oxide Inorganic materials 0.000 claims description 11
- 150000004706 metal oxides Chemical class 0.000 claims description 11
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 10
- 229910003437 indium oxide Inorganic materials 0.000 claims description 10
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052733 gallium Inorganic materials 0.000 claims description 8
- 239000011787 zinc oxide Substances 0.000 claims description 5
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910052725 zinc Inorganic materials 0.000 claims description 4
- 239000011701 zinc Substances 0.000 claims description 4
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 4
- 239000000428 dust Substances 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 20
- 239000000463 material Substances 0.000 description 18
- 230000000694 effects Effects 0.000 description 13
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 12
- 238000012545 processing Methods 0.000 description 11
- 238000013461 design Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 229960005363 aluminium oxide Drugs 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 235000014692 zinc oxide Nutrition 0.000 description 4
- 229960001296 zinc oxide Drugs 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- 239000004925 Acrylic resin Substances 0.000 description 2
- 229920000178 Acrylic resin Polymers 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- BRPQOXSCLDDYGP-UHFFFAOYSA-N calcium oxide Chemical compound [O-2].[Ca+2] BRPQOXSCLDDYGP-UHFFFAOYSA-N 0.000 description 2
- 239000000292 calcium oxide Substances 0.000 description 2
- ODINCKMPIJJUCX-UHFFFAOYSA-N calcium oxide Inorganic materials [Ca]=O ODINCKMPIJJUCX-UHFFFAOYSA-N 0.000 description 2
- 235000012255 calcium oxide Nutrition 0.000 description 2
- 229940087373 calcium oxide Drugs 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910001195 gallium oxide Inorganic materials 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910000476 molybdenum oxide Inorganic materials 0.000 description 2
- PQQKPALAQIIWST-UHFFFAOYSA-N oxomolybdenum Chemical compound [Mo]=O PQQKPALAQIIWST-UHFFFAOYSA-N 0.000 description 2
- 230000001737 promoting effect Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229960005196 titanium dioxide Drugs 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-N Acrylic acid Chemical compound OC(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- -1 aluminium oxide) Chemical class 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 238000010023 transfer printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
An oxide semiconductor thin film transistor comprises a patterned oxide semiconductor layer, a patterned grid dielectric layer, a grid, a hydrogen diffusion control layer, a hydrogen source layer, a source electrode and a drain electrode. The patterned oxide semiconductor layer is arranged on a substrate. The patterned gate dielectric layer is disposed on the patterned oxide semiconductor layer. The gate is disposed on the patterned gate dielectric layer. The hydrogen diffusion control layer is arranged on the grid electrode and the patterned oxide semiconductor layer, and the hydrogen diffusion control layer covers the grid electrode and the patterned grid electrode dielectric layer. The hydrogen source layer is arranged on the hydrogen diffusion control layer and the patterned oxide semiconductor layer, the source electrode and the drain electrode are arranged on the hydrogen source layer, and the hydrogen content of the hydrogen source layer is greater than that of the hydrogen diffusion control layer.
Description
Technical field
The present invention is about a kind of oxide semiconductor thin-film transistor and preparation method thereof, and espespecially a kind of hydrogen trap key-course that utilizes enters oxide semiconductor thin-film transistor of the situation of oxide semiconductor layer and preparation method thereof to control hydrogen.
Background technology
In recent years, the application development of various display is rapid, and thin-film transistor (thinfilmtransistor, TFT) a kind of semiconductor element being widely used in display technology, such as be applied in liquid crystal display (liquidcrystaldisplay, LCD), in the display such as Organic Light Emitting Diode (organiclightemittingdiode, OLED) display and Electronic Paper (electronicpaper, E-paper).Thin-film transistor profit is used to provide the switching of voltage or electric current, can present display effect that is bright, dark and GTG to make the display pixel in various display.
The thin-film transistor that current display industry uses can distinguish according to the semiconductor layer material used, comprise amorphous silicon film transistor (amorphoussiliconTFT, a-SiTFT), polycrystalline SiTFT (polysiliconTFT) and oxide semiconductor thin-film transistor (oxidesemiconductorTFT).Wherein oxide semiconductor thin-film transistor applies the new oxide semiconductor material emerged in recent years, this type of material is generally amorphous phase (amorphous) structure, therefore be not more applied to the problem that on large size panel, uniformity is not good, and various ways film forming can be utilized, the modes such as such as sputter (sputter), spin coating (spin-on) and printing (inkjetprinting).Because the electron mobility of oxide semiconductor thin-film transistor generally compared with more than amorphous silicon film transistor high several times having above-mentioned processing procedure advantage, therefore can to have commercial prods listing of some application oxide semiconductor thin-film transistors in the market gradually.
In the structure of general oxide semiconductor thin-film transistor, the contact impedance of the storeroom of oxide semiconductor layer and source/drain obviously can affect the overall electrical performance of oxide semiconductor thin-film transistor.As shown in Figure 1, when the size stationary conduit width (W) of thin-film transistor, when passage length (L) is more and more less, can find that oxide semiconductor thin-film transistor electrical performance will produce skew when L narrows down to below 15 microns.Therefore, in order to promote the usefulness of oxide semiconductor thin-film transistor, need improve the contact impedance of oxide semiconductor layer and source/drain interpolar.Way general at present has use plasma treatment (plasmatreatment) or makes oxide semiconductor layer directly contact the high material of hydrogen content and produce hydrogen trap, estimates that the resistivity in the region of the oxide semiconductor layer contacted with source/drain reduces to make part.But, above-mentioned plasma treatment mode easily causes the resistance situation of the oxide semiconductor layer after being processed unstable, directly contact the high material of hydrogen content to produce mode then its range of scatter wayward of hydrogen trap, the oxide semiconductor layer originally will being used as conducting region is easily caused to be vulnerable to extend influence and seriously to have influence on the element characteristic of thin-film transistor, particularly under the design of the thin-film transistor of jitty.
Summary of the invention
One of main purpose of the present invention is to provide a kind of oxide semiconductor thin-film transistor and preparation method thereof, utilize hydrogen trap key-course to control the situation that hydrogen enters oxide semiconductor layer, avoid hydrogen to enter the element characteristic having influence on thin-film transistor in the conducting region of oxide semiconductor layer, the conducting region herein defined be oxide semiconductor thin-film transistor ideally electronics move beeline.
One embodiment of the invention provide a kind of oxide semiconductor thin-film transistor, comprise a substrate, a patterned oxide semiconductor layer, a patterning gate dielectric, a grid, a hydrogen trap key-course, a hydrogen source layer, one source pole and a drain electrode.Patterned oxide semiconductor layer is arranged on substrate.Patterning gate dielectric is arranged on patterned oxide semiconductor layer.Grid is arranged on patterning gate dielectric.Hydrogen trap key-course is arranged on grid and patterned oxide semiconductor layer, and the coated grid of hydrogen trap key-course and patterning gate dielectric.Hydrogen source layer is arranged on hydrogen trap key-course and patterned oxide semiconductor layer, and the hydrogen content of hydrogen source layer is greater than the hydrogen content of hydrogen trap key-course.Source electrode and drain electrode are arranged in hydrogen source layer, and source electrode and drain electrode contact with patterned oxide semiconductor layer and be electrically connected.
According to an embodiment of the present invention, wherein this hydrogen trap key-course directly contacts this patterned oxide semiconductor layer, and this hydrogen source layer directly contacts this hydrogen trap key-course.
According to another embodiment of the present invention, wherein this hydrogen source layer directly contacts this patterned oxide semiconductor layer.
According to another embodiment of the present invention, wherein this hydrogen trap key-course covers this patterning gate dielectric and this grid, this hydrogen trap key-course extends along a side of this grid to this patterned oxide semiconductor layer from an end face of this grid, and extends and do not exceed this hydrogen trap key-course and be positioned at this end face upright projection in the drop shadow spread of this substrate.
According to another embodiment of the present invention, wherein this hydrogen trap key-course also has an extension in a horizontal direction, and this extension covers this patterned oxide semiconductor layer in the two ends of this horizontal direction.
According to another embodiment of the present invention, described oxide semiconductor thin-film transistor also comprises multiple contact perforate, and wherein this source electrode and this drain electrode contact perforate through these and to contact with this patterned oxide semiconductor layer and to be electrically connected to run through this hydrogen source layer.
According to another embodiment of the present invention, wherein these contact perforates also run through this hydrogen trap key-course.
According to another embodiment of the present invention, wherein this hydrogen trap key-course comprises metal oxide, silicon nitride, silica or silicon oxynitride.
According to another embodiment of the present invention, wherein the thickness of this hydrogen trap key-course between 100 dusts (angstrom) to 500 dusts.
According to another embodiment of the present invention, wherein this hydrogen source layer comprises silicon nitride, silica or silicon oxynitride.
According to another embodiment of the present invention, wherein this patterned oxide semiconductor layer comprises indium oxide gallium zinc, zinc oxide, indium zinc oxide or indium oxide gallium.
According to another embodiment of the present invention, wherein this hydrogen content of this hydrogen source layer is between 15atoms/cm
3to 27atoms/cm
3between.
Another embodiment of the present invention provides a kind of manufacture method of oxide semiconductor thin-film transistor, comprises the following steps.A patterned oxide semiconductor layer is formed on a substrate; A patterning gate dielectric is formed on patterned oxide semiconductor layer; A grid is formed on patterning gate dielectric; A hydrogen trap key-course is formed, wherein the coated grid of hydrogen trap key-course and patterning gate dielectric on grid and patterned oxide semiconductor layer; On hydrogen trap key-course and patterned oxide semiconductor layer, form a hydrogen source layer, wherein the hydrogen content of hydrogen source layer is greater than the hydrogen content of hydrogen trap key-course; And in hydrogen source layer, form one source pole and a drain electrode, wherein source electrode and drain electrode contact with patterned oxide semiconductor layer and are electrically connected.
According to an embodiment of the present invention, this hydrogen trap key-course covers this patterning gate dielectric and this grid, this hydrogen trap key-course extends along a side of this grid to this patterned oxide semiconductor layer from an end face of this grid, and extends and do not exceed this hydrogen trap key-course and be positioned at this end face upright projection in the drop shadow spread of this substrate.
According to another embodiment of the present invention, wherein this hydrogen trap key-course, this patterning gate dielectric and this grid use same mask (mask) to define figure.
According to another embodiment of the present invention, wherein this hydrogen trap key-course comprises metal oxide, silicon nitride, silica or silicon oxynitride.
According to another embodiment of the present invention, wherein this hydrogen content of this hydrogen source layer is between 15atoms/cm
3to 27atoms/cm
3between.
Oxide semiconductor thin-film transistor of the present invention utilizes the hydrogen trap key-course of coated grid and patterning gate dielectric to control the situation of the hydrogen trap in hydrogen source layer to patterned oxide semiconductor layer, and the conducting region that the hydrogen in hydrogen source layer is diffused in patterning gate dielectric by patterning gate dielectric can be avoided, guarantee the electrical situation of conducting region while can forming doped region in patterned oxide semiconductor layer whereby, and then the oxide semiconductor thin-film transistor with jitty design can be realized.
Accompanying drawing explanation
Fig. 1 depicts the Drain current-Gate Voltage graph of a relation of the oxide semiconductor thin-film transistor of prior art.
Fig. 2 to Fig. 6 depicts the manufacture method schematic diagram of the oxide semiconductor thin-film transistor of first embodiment of the invention.
Fig. 7 depicts the Drain current-Gate Voltage graph of a relation of the oxide semiconductor thin-film transistor of first embodiment of the invention.
Fig. 8 depicts the schematic diagram of the oxide semiconductor thin-film transistor of a reference examples.
Fig. 9 depicts the Drain current-Gate Voltage graph of a relation of the oxide semiconductor thin-film transistor of reference examples.
Figure 10 depicts the schematic diagram of the oxide semiconductor thin-film transistor of second embodiment of the invention.
Figure 11 depicts the schematic diagram of the oxide semiconductor thin-film transistor of third embodiment of the invention.
Figure 12 and Figure 13 depicts the manufacture method schematic diagram of the oxide semiconductor thin-film transistor of fourth embodiment of the invention.
Figure 14 depicts the Drain current-Gate Voltage graph of a relation of the oxide semiconductor thin-film transistor of fourth embodiment of the invention.
[symbol description]
10 substrates
20 patterned oxide semiconductor layers
20A conducting region
20B doped region
30 patterning gate dielectrics
30F intersection
30S side
40 grids
50 hydrogen trap key-courses
50A extension
60 hydrogen source layer
70D drains
70S source electrode
101-104 oxide semiconductor thin-film transistor
200 oxide semiconductor thin-film transistors
H horizontal direction
S end face
V contacts perforate
W1 first width
W2 second width
W3 the 3rd width
Z vertical direction
Embodiment
For making the those skilled in the art haveing the knack of the technical field of the invention further can understand the present invention, hereafter spy enumerates preferred embodiment of the present invention, and coordinates appended accompanying drawing, describe in detail constitution content of the present invention and the effect for reaching.
Please refer to Fig. 2 to Fig. 6.Fig. 2 to Fig. 6 depicts the manufacture method schematic diagram of the oxide semiconductor thin-film transistor of first embodiment of the invention.The manufacture method of the oxide semiconductor thin-film transistor of the present embodiment comprises the following steps.First, as shown in Figure 2, on substrate 10, patterned oxide semiconductor layer 20 is formed.Substrate 10 can comprise the substrate that hard substrate such as glass substrate and ceramic substrate, flexible substrate (flexiblesubstrate) such as plastic substrate or other applicable materials are formed.The material of patterned oxide semiconductor layer 20 can comprise indium oxide gallium zinc, zinc oxide, indium zinc oxide, indium oxide gallium or other oxide semiconductor materials be applicable to, and patterned oxide semiconductor layer 20 reaches patterning effect by processing procedures such as such as micro-shadow, etchings or directly formed in transfer printing (rolltoroll) mode, but not as limit.Then, on patterned oxide semiconductor layer 20, form patterning gate dielectric 30 and grid 40.Patterning gate dielectric 30 and grid 40 define formation by same photoresistance pattern (not shown), so as to the effect making the figure of the figure of patterning gate dielectric 30 and grid 40 can reach autoregistration (self-aligned) on vertical direction Z, but not as limit.Patterning gate dielectric 30 can be the dielectric materials layer of single or multiple lift, and its material can comprise inorganic material such as silicon nitride (siliconnitride), silica (siliconoxide), silicon oxynitride (siliconoxynitride), with metal oxide (such as aluminium oxide), organic material such as acrylic resin (acrylicresin) or other be applicable to dielectric material.In addition, grid 40 can comprise the wherein at least one of metal material such as aluminium, copper, silver, chromium, titanium, molybdenum, the composite bed of above-mentioned material or the alloy of above-mentioned material, but other can not used to have the material of conduction property as limit.
Then, as shown in Figure 3, on patterning gate dielectric 30, hydrogen trap key-course 50 is formed.And as shown in Figure 4, patterning hydrogen trap key-course 50, in this step, hydrogen trap key-course 50, patterning gate dielectric 30 use same mask (mask) to define figure with grid 40, utilize exposure to decide the size of hydrogen trap key-course 50 coverage diagram patterning gate dielectric 30.Specifically, hydrogen trap key-course 50 is ㄇ font, complete coverage diagram patterning gate dielectric 30 and the side 30S of the grid 40 and intersection 30F of side 30S and patterned oxide semiconductor layer 20, hydrogen trap key-course 50 extends along side 30S to patterned oxide semiconductor layer 20 on vertical direction Z from the end face S of grid 40, and extends and do not exceed hydrogen trap key-course 50 and be positioned at end face S upright projection in the drop shadow spread of substrate 10.Horizontal direction H is preferably orthogonal with vertical direction Z, and vertical direction Z be preferably substantially with the surface normal of substrate 10, but not as limit.In the present embodiment, hydrogen trap key-course 50 is except coated grid 40 and patterning gate dielectric 30, only cover the side 30S of patterning the gate dielectric 30 and intersection 30F of patterned oxide semiconductor layer 20, therefore the two ends of hydrogen trap key-course 50 non-coverage diagram patterning oxide semiconductor layer 20 on horizontal direction H, but the present invention is not as limit.Also comprehensive coverage diagram patterning oxide semiconductor layer 20 or at least two ends of coverage diagram patterning oxide semiconductor layer 20 on horizontal direction H can optionally be made in other embodiments of the invention.Hydrogen trap key-course 50 can comprise the hydrogen content insulating material low compared with hydrogen source layer 60, comprise silicon nitride, silica, silicon oxynitride or metal oxide etc., metal oxide for example can be aluminium oxide (aluminiumoxide), calcium oxide (calciumoxide), molybdenum oxide (molybdenumoxide), zinc oxide (zincoxide), indium oxide (indiumoxide), gallium oxide (galliumoxide), indium oxide gallium (indiumgalliumoxide), indium oxide gallium zinc (indiumgalliumzincoxide), indium zinc oxide (indiumzincoxide), tin indium oxide (indiumtinoxide), titanium oxide (titaniumoxide), tin oxide (tinoxide), three-group metal oxide, 4th family metal oxide or the 5th family metal oxide, and other metal oxide materials be applicable to.Hydrogen content is herein the hydrogen content of hydrogen trap key-course 50 after fabrication process, and the hydrogen trap key-course 50 of the present embodiment is preferably the comparatively fine and close aluminium oxide of structure, reaches the better effect preventing hydrogen trap whereby, but not as limit.Hydrogen trap key-course 50 can utilize chemical vapour deposition (CVD) or physical vapour deposition (PVD) mode to be formed, and reduces hydrogen content by processing environment during processing procedure and parameter adjustment.In addition, the thickness of hydrogen trap key-course 50, between 100 dusts (angstrom) to 1000 dusts, be preferably between 100 dust to 500 dusts, but this is not limited.What deserves to be explained is, the hydrogen trap key-course 50 of the present embodiment is corresponding with grid 40 and patterning gate dielectric 30 to be arranged, therefore the same mask used can be used in the processing procedure of grid 40 patterning effect is formed to hydrogen trap key-course 50, same mask can be utilized and the adjustment of exposure of arranging in pairs or groups (exposuredose) forms the corresponding photoresistance pattern carrying out needed for patterning to hydrogen trap key-course 50, reach whereby and reduce mask requirements amount and the effect reducing production cost, but not as limit.
After, as shown in Figure 5, on substrate 10, patterned oxide semiconductor layer 20 and hydrogen trap key-course 50, form a hydrogen source layer 60.The hydrogen content of hydrogen source layer 60 is greater than the hydrogen content of hydrogen trap key-course 50.The material of hydrogen source layer 60 can comprise silicon nitride, silica, silicon oxynitride or other insulating material with high hydrogen content be applicable to, the silica that after the silicon nitride that after hydrogen source layer 60 can comprise processing procedure reaction, hydrogen content is higher or processing procedure react, hydrogen content is high compared with hydrogen trap key-course 50.Hydrogen source layer 60 also can utilize chemical vapour deposition (CVD) or physical vapour deposition (PVD) mode to be formed, and promotes hydrogen content by processing environment during processing procedure and parameter adjustment.For example, when using chemical vapour deposition (CVD) to form the hydrogen source layer 60 of silicon nitride, its process temperatures can be 280 DEG C, and the reacting gas passed into can comprise silicomethane (SiH
4) and ammonia (NH
3), and methane (SiH
4) and ammonia (NH
3) intake can be respectively 200sccm and 1200sccm, form the hydrogen content silicon nitride high compared with hydrogen trap key-course 50 whereby, but not as limit.The hydrogen content of the hydrogen source layer 60 of the present embodiment is preferably between 15atoms/cm
3to 27atoms/cm
3between, can diffuse in patterned oxide semiconductor layer 20 form doped region 20B in order to have enough hydrogen, but not as limit.Due to the two ends of hydrogen trap key-course 50 non-coverage diagram patterning oxide semiconductor layer 20 on horizontal direction H of the present embodiment, therefore the two ends of patterned oxide semiconductor layer 20 on horizontal direction H are exposed to outside hydrogen trap key-course 50 and directly contact with hydrogen source layer 60, the hydrogen composition can strengthened whereby in hydrogen source layer 60 diffuses to the effect of corresponding patterned oxide semiconductor layer 20, and then reduces the resistivity of doped region 20B.In the present embodiment, patterned oxide semiconductor layer 20 and hydrogen source layer 60 directly contact part and form two doped region 20B, and the region corresponding with hydrogen trap key-course 50, grid 40 and patterning gate dielectric 30 still maintains the conducting region 20A with characteristic of semiconductor.In other words, the patterned oxide semiconductor layer 20 of the present embodiment can comprise conducting region 20A and two doped region 20B after hydrogen source layer 60 is formed, grid 40 is overlapping with conducting region 20A on vertical direction Z, two doped region 20B lay respectively at the both sides of conducting region 20A on horizontal direction H, and the resistivity of doped region 20B is less than the resistivity of conducting region 20A.
What deserves to be explained is, the coated patterning gate dielectric 30 of the hydrogen trap key-course 50 due to the present embodiment, therefore the hydrogen in hydrogen source layer 60 can be avoided by the electrical situation having influence on conducting region 20A laterally through patterning gate dielectric 30.The hydrogen trap key-course 50 being covered in the side 30S of patterning gate dielectric 30 and the intersection 30F of patterned oxide semiconductor layer 20 also can, in order to the scope of controlled doping district 20B, be avoided making the scope of doped region 20B excessive and making whole patterned oxide semiconductor layer 20 present the state electrically conducted.In the present embodiment, to be arranged on grid 40 and coated grid 40 has the first width W 1 with the hydrogen trap key-course 50 of patterning gate dielectric 30 on horizontal direction H, grid 40 has the second width W 2 on horizontal direction H, conducting region 20A has the 3rd width W 3 on horizontal direction H, and the first width W 1 of hydrogen trap key-course 50 is more than or equal to the 3rd width W 3 of conducting region 20A.Can be controlled the width of conducting region 20A by the diffusion-condition of the hydrogen of adjustment hydrogen source layer 60, such as, when the diffusion-condition of the hydrogen of hydrogen source layer 60 is stronger, the 3rd width W 3 of conducting region 20A also may be less than the second width W 2 of grid 40.In addition, the manufacture method of the present embodiment optionally optionally can also comprise heat treated processing procedure, in order to the diffusion effect of the hydrogen of auxiliary hydrogen source layer 60, but not as limit.
Then, as shown in Figure 6, form multiple contact perforate V in hydrogen source layer 60, contact perforate V runs through hydrogen source layer 60 and exposes the doped region 20B of part.After, in hydrogen source layer 60, form one source pole 70S and drain electrode 70D, complete oxide semiconductor thin-film transistor 101 as shown in Figure 5 whereby.Source electrode 70S to contact with two doped region 20B with drain electrode 70D through contacting perforate V and to be electrically connected, source electrode 70S can comprise the wherein at least one of metal material such as aluminium, copper, silver, chromium, titanium, molybdenum, the composite bed of above-mentioned material or the alloy of above-mentioned material respectively with drain electrode 70D, but other can not used to have the material of conduction property as limit.
As shown in Figure 6, the oxide semiconductor thin-film transistor 101 of the present embodiment comprises patterned oxide semiconductor layer 20, patterning gate dielectric 30, grid 40, hydrogen trap key-course 50, hydrogen source layer 60, source electrode 70S and drain electrode 70D.Patterned oxide semiconductor layer 20 is arranged on substrate 10.Patterning gate dielectric 30 is arranged on patterned oxide semiconductor layer 20.Grid 40 is arranged on patterning gate dielectric 30.Hydrogen trap key-course 50 is arranged at grid 40 with on patterned oxide semiconductor layer 20, and the coated grid 40 of hydrogen trap key-course 50 and patterning gate dielectric 30.Hydrogen source layer 60 is arranged on hydrogen trap key-course 50 and patterned oxide semiconductor layer 20, and the hydrogen content of hydrogen source layer 60 is greater than the hydrogen content of hydrogen trap key-course 50.Source electrode 70S is arranged in hydrogen source layer 60 with drain electrode 70D, and source electrode 70S to contact with two doped region 20B with the 70D that drains through contacting perforate V and to be electrically connected.In oxide semiconductor thin-film transistor 101, the material behavior of each element illustrates in above-mentioned manufacture method, therefore repeats no more at this.It should be noted that the hydrogen trap key-course 50 of the present embodiment is preferably direct hookup patterning oxide semiconductor layer 20, hydrogen source layer 60 is preferably directly contact hydrogen trap key-course 50, and hydrogen source layer 60 directly contact doping district 20B, but not as limit.By the hydrogen trap in the controlled hydrogen manufacturing source layer 60 of the hydrogen trap key-course 50 of the present embodiment to the situation of patterned oxide semiconductor layer 20, and the conducting region 20A that simultaneously hydrogen in hydrogen source layer 60 can be avoided to be diffused in patterned oxide semiconductor layer 20 by patterning gate dielectric 30.Under this design, even if grid 40 and patterning gate dielectric 30 need reduce because of jitty design, still carry out the range size of controlled doping district 20B by hydrogen trap key-course 50 and avoid electrically being affected of conducting region 20A, promoting the element characteristic of oxide semiconductor thin-film transistor 101 whereby.
For example, please refer to Fig. 6 to Fig. 9.The channel width (W) that Fig. 7 depicts the oxide semiconductor thin-film transistor 101 of the first embodiment and passage length (L) are the graph of a relation of the Drain current-Gate Voltage under the design situation of 5 microns.Fig. 8 depicts the schematic diagram of the oxide semiconductor thin-film transistor 200 of a reference examples.The oxide semiconductor thin-film transistor 200 that Fig. 9 depicts reference examples is the Drain current-Gate Voltage graph of a relation under the design situation of 5 microns in channel width and passage length.The oxide semiconductor thin-film transistor 200 of this reference examples is not except comprising the hydrogen trap key-course 50 of the first embodiment, and remaining part is all similar to oxide semiconductor thin-film transistor 101.As shown in Figures 6 and 7, the oxide semiconductor thin-film transistor 101 of the first embodiment can still have good tft characteristics under the situation being provided with hydrogen trap key-course 50 under channel width and the relatively high situation of passage length ratio, and its carrier transport factor (mobility) can reach about 22cm
2/ VS.Comparatively speaking, as shown in Fig. 8 and Fig. 9, owing to not arranging hydrogen trap key-course, therefore the oxide semiconductor thin-film transistor of this reference examples can be partial to conducting and not have tft characteristics under channel width and the relatively high situation of passage length ratio.
Hereafter will be described for different embodiments of the invention, and be simplified illustration, and below illustrate and to describe in detail mainly for each embodiment difference, and no longer something in common is repeated.In addition, element identical in various embodiments of the present invention indicates with identical label, is beneficial to check one against another between each embodiment.
Please refer to Figure 10.Figure 10 depicts the schematic diagram of the oxide semiconductor thin-film transistor 102 of second embodiment of the invention.The place different from above-mentioned first embodiment is, 3rd width W 3 of the conducting region 20A of the present embodiment is less than the first width W 1 of hydrogen trap key-course 50, and the 3rd width W 3 of conducting region 20A is identical with the second width W 2 of grid 40 substantially, but not as limit.
Please refer to Figure 11.Figure 11 depicts the schematic diagram of the oxide semiconductor thin-film transistor 103 of third embodiment of the invention.The place different from above-mentioned first embodiment is, the present embodiment makes the 3rd width W 3 of conducting region 20A be less than the second width W 2 of grid 40 by the diffusion effect strengthening hydrogen in hydrogen source layer 60, reaches the object of the channel width further shortening oxide semiconductor thin-film transistor 103 whereby.In above-mentioned reinforcement hydrogen source layer 60 mode of hydrogen trap effect can comprise improve hydrogen in strong hydrogen source layer 60 concentration (such as additionally passing into hydrogen in time depositing hydrogen source layer 60), apply an aid in treatment such as heat treated or other be applicable to the mode that can be used to strengthen hydrogen trap effect.
Please refer to Figure 12 and Figure 13.Figure 12 and Figure 13 depicts the manufacture method schematic diagram of the oxide semiconductor thin-film transistor of fourth embodiment of the invention.The place different from above-mentioned first embodiment is, as shown in figure 12, the hydrogen trap key-course 50 of the present embodiment can coverage diagram patterning oxide semiconductor layer 20, patterning gate dielectric 30 and grid 40 completely, therefore the two ends of hydrogen trap key-course 50 coverage diagram patterning oxide semiconductor layer 20 on horizontal direction H, the doped region 20B of hydrogen source layer 60 then directly hookup patterning oxide semiconductor layer 20 and follow-up formation.Mode can be avoided crossing strong when the hydrogen trap effect in hydrogen source layer 60 and making the scope of the corresponding doped region 20B formed excessive whereby, and therefore has influence on the electrical situation of conducting region 20A.As shown in figure 13, when forming the oxide semiconductor thin-film transistor 104 of the present embodiment, due to doped region 20B by hydrogen trap key-course 50 and hydrogen source layer 60 cover, therefore contact perforate V need run through hydrogen source layer 60 exposes two doped region 20B with hydrogen trap key-course 50 with part, and source electrode 70S and the 70D that drains are formed by contacting perforate V and contacting with doped region 20B be electrically connected.In addition, the hydrogen trap key-course 50 of the present embodiment also has an extension 50A, and extension 50A coverage diagram patterning oxide semiconductor layer 20 is in the two ends of horizontal direction H.
Please refer to Figure 14, and please also refer to Figure 13.The oxide semiconductor thin-film transistor 104 that Figure 14 depicts the present embodiment is the graph of a relation of the Drain current-Gate Voltage under the design situation of 5 microns in channel width and passage length.As shown in Figure 14 and Figure 13, the oxide semiconductor thin-film transistor 104 of the present embodiment can still have good tft characteristics under the situation being provided with hydrogen trap key-course 50 under channel width and the relatively high situation of passage length ratio, and its carrier transport factor (mobility) can reach about 13cm
2/ VS.Although more above-mentioned first embodiment of the carrier transport factor of the oxide semiconductor thin-film transistor 104 of the present embodiment is low, but make hydrogen source layer 60 direct hookup patterning oxide semiconductor layer 20 due to the hydrogen trap key-course 50 coverage diagram patterning oxide semiconductor layer 20 of the present embodiment, therefore to control on precision for the hydrogen concentration of hydrogen source layer 60 can be comparatively loose and be conducive to the carrying out of processing procedure.Comparatively speaking, as shown in Fig. 8 and Fig. 9, owing to not arranging hydrogen trap key-course, therefore the oxide semiconductor thin-film transistor of this reference examples can be partial to conducting and not have tft characteristics under channel width and the relatively high situation of passage length ratio.
In sum, oxide semiconductor thin-film transistor of the present invention utilizes hydrogen trap key-course to control the situation of the hydrogen trap in hydrogen source layer to patterned oxide semiconductor layer, and avoids the hydrogen in hydrogen source layer to diffuse to the conducting region in patterning gate dielectric by patterning gate dielectric simultaneously and have influence on the electrical situation of conducting region.Therefore, even if the grid in oxide semiconductor thin-film transistor and patterning gate dielectric need reduce to meet jitty design, still carry out the forming range in controlled doping district by hydrogen trap key-course and avoid electrically being affected of conducting region, therefore the object of the element characteristic promoting oxide semiconductor thin-film transistor can be reached.In addition, the manufacture method of oxide semiconductor thin-film transistor of the present invention can utilize the figure of same mask definition hydrogen trap key-course, patterning gate dielectric and grid, reaches the object reducing cost of manufacture whereby.
The foregoing is only preferred embodiment of the present invention, all equalizations done according to the present patent application the scope of the claims change and modify, and all should belong to covering scope of the present invention.
Claims (17)
1. an oxide semiconductor thin-film transistor, comprising:
One substrate;
One patterned oxide semiconductor layer, is arranged on this substrate;
One patterning gate dielectric, is arranged on this patterned oxide semiconductor layer;
One grid, is arranged on this patterning gate dielectric;
One hydrogen trap key-course, is arranged on this grid and this patterned oxide semiconductor layer, wherein this hydrogen trap key-course this grid coated and this patterning gate dielectric;
One hydrogen source layer, be arranged on this hydrogen trap key-course and this patterned oxide semiconductor layer, wherein the hydrogen content of this hydrogen source layer is greater than the hydrogen content of this hydrogen trap key-course; And
One source pole and one drains, and is arranged in this hydrogen source layer, and wherein this source electrode and this drain electrode contact with this patterned oxide semiconductor layer and be electrically connected.
2. oxide semiconductor thin-film transistor as claimed in claim 1, wherein this hydrogen trap key-course directly contacts this patterned oxide semiconductor layer, and this hydrogen source layer directly contacts this hydrogen trap key-course.
3. oxide semiconductor thin-film transistor as claimed in claim 1, wherein this hydrogen source layer directly contacts this patterned oxide semiconductor layer.
4. oxide semiconductor thin-film transistor as claimed in claim 1, wherein this hydrogen trap key-course covers this patterning gate dielectric and this grid, this hydrogen trap key-course extends along a side of this grid to this patterned oxide semiconductor layer from an end face of this grid, and extends and do not exceed this hydrogen trap key-course and be positioned at this end face upright projection in the drop shadow spread of this substrate.
5. oxide semiconductor thin-film transistor as claimed in claim 4, wherein this hydrogen trap key-course also has an extension in a horizontal direction, and this extension covers this patterned oxide semiconductor layer in the two ends of this horizontal direction.
6. oxide semiconductor thin-film transistor as claimed in claim 1, also comprises multiple contact perforate, runs through this hydrogen source layer, and wherein this source electrode and this drain electrode contact perforate through these and to contact with this patterned oxide semiconductor layer and to be electrically connected.
7. oxide semiconductor thin-film transistor as claimed in claim 6, wherein these contact perforates also run through this hydrogen trap key-course.
8. oxide semiconductor thin-film transistor as claimed in claim 1, wherein this hydrogen trap key-course comprises metal oxide, silicon nitride, silica or silicon oxynitride.
9. oxide semiconductor thin-film transistor as claimed in claim 1, wherein the thickness of this hydrogen trap key-course is between 100 dust to 500 dusts.
10. oxide semiconductor thin-film transistor as claimed in claim 1, wherein this hydrogen source layer comprises silicon nitride, silica or silicon oxynitride.
11. oxide semiconductor thin-film transistors as claimed in claim 1, wherein this patterned oxide semiconductor layer comprises indium oxide gallium zinc, zinc oxide, indium zinc oxide or indium oxide gallium.
12. oxide semiconductor thin-film transistors as claimed in claim 1, wherein this hydrogen content of this hydrogen source layer is between 15atoms/cm
3to 27atoms/cm
3between.
The manufacture method of 13. 1 kinds of oxide semiconductor thin-film transistors, comprising:
A patterned oxide semiconductor layer is formed on a substrate;
A patterning gate dielectric is formed on this patterned oxide semiconductor layer;
A grid is formed on this patterning gate dielectric;
A hydrogen trap key-course is formed, wherein this hydrogen trap key-course this grid coated and this patterning gate dielectric on this grid and this patterned oxide semiconductor layer;
On this hydrogen trap key-course and this patterned oxide semiconductor layer, form a hydrogen source layer, wherein the hydrogen content of this hydrogen source layer is greater than the hydrogen content of this hydrogen trap key-course; And
In this hydrogen source layer, form one source pole and a drain electrode, wherein this source electrode and this drain electrode contact with this patterned oxide semiconductor layer and are electrically connected.
The manufacture method of 14. oxide semiconductor thin-film transistors as claimed in claim 13, this hydrogen trap key-course covers this patterning gate dielectric and this grid, this hydrogen trap key-course extends along a side of this grid to this patterned oxide semiconductor layer from an end face of this grid, and extends and do not exceed this hydrogen trap key-course and be positioned at this end face upright projection in the drop shadow spread of this substrate.
The manufacture method of 15. oxide semiconductor thin-film transistors as claimed in claim 14, wherein this hydrogen trap key-course, this patterning gate dielectric and this grid use same mask to define figure.
The manufacture method of 16. oxide semiconductor thin-film transistors as claimed in claim 13, wherein this hydrogen trap key-course comprises metal oxide, silicon nitride, silica or silicon oxynitride.
The manufacture method of 17. oxide semiconductor thin-film transistors as claimed in claim 13, wherein this hydrogen content of this hydrogen source layer is between 15atoms/cm
3to 27atoms/cm
3between.
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| CN104183650A (en) * | 2014-09-10 | 2014-12-03 | 六安市华海电子器材科技有限公司 | Oxide semiconductor thin film transistor |
| CN105977306A (en) * | 2016-06-21 | 2016-09-28 | 北京大学深圳研究生院 | Self-aligned thin-film transistor and preparation method thereof |
| WO2017124686A1 (en) * | 2016-01-21 | 2017-07-27 | 武汉华星光电技术有限公司 | Tft array substrate structure and manufacturing method thereof |
| US10861733B2 (en) | 2016-08-09 | 2020-12-08 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
| CN113497155A (en) * | 2020-06-23 | 2021-10-12 | 台湾积体电路制造股份有限公司 | Transistor and forming method thereof |
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| CN111937161A (en) * | 2018-04-04 | 2020-11-13 | 株式会社半导体能源研究所 | Semiconductor device and method for manufacturing semiconductor device |
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| TW201703120A (en) | 2017-01-16 |
| CN105206677B (en) | 2018-10-12 |
| TWI613706B (en) | 2018-02-01 |
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