TW201703120A - Oxide semiconductor thin film transistor and manufacturing method thereof - Google Patents

Abstract

An oxide semiconductor thin film transistor includes a patterned oxide semiconductor layer, a patterned gate insulation layer, a gate, a hydrogen diffusion control layer, a hydrogen source layer, a source, and a drain. The patterned oxide semiconductor layer is disposed on a substrate. The patterned gate insulation layer is disposed on the patterned oxide semiconductor layer. The gate is disposed on the patterned gate insulation layer. The hydrogen diffusion control layer is disposed on the gate and the patterned oxide semiconductor layer. The hydrogen diffusion control layer wraps the gate and the patterned gate insulation layer. The hydrogen source layer is disposed on the hydrogen diffusion control layer and the patterned oxide semiconductor layer. The source and the drain are disposed on the hydrogen source layer. A hydrogen concentration of the hydrogen source layer is higher than a hydrogen concentration of the hydrogen diffusion control layer.

Description

Oxide semiconductor thin film transistor and manufacturing method thereof

The present invention relates to an oxide semiconductor thin film transistor and a method of fabricating the same, and more particularly to an oxide semiconductor thin film transistor using a hydrogen diffusion control layer to control the state of hydrogen entering an oxide semiconductor layer and a method of fabricating the same.

In recent years, the application of various displays has been rapidly developed, and thin film transistors (TFTs) are a semiconductor component widely used in display technology, such as liquid crystal display (LCD), organic light-emitting diodes. (organic light emitting diode, OLED) display and electronic paper (E-paper) and other displays. Thin film electro-crystal systems are utilized to provide switching of voltage or current such that display pixels in various displays can exhibit bright, dark, and grayscale display effects.

At present, thin film transistors used in the display industry can be distinguished according to the semiconductor layer materials used, including amorphous silicon TFTs (a-Si TFTs), polysilicon TFTs, and oxide semiconductors. Thin film transistor (oxide semiconductor TFT). Among them, the oxide semiconductor thin film transistor is a newly emerging oxide semiconductor material in recent years, and such a material is generally an amorphous structure, so it is less suitable for the problem of poor uniformity on a large-sized panel, and Film formation is performed in a variety of ways, such as sputtering, spin-on, and inkjet printing. Since the electron mobility of the oxide semiconductor thin film transistor is generally several times higher than that of the amorphous germanium thin film transistor and has the above-mentioned process advantages, there are some commercial products for the application of the oxide semiconductor thin film transistor on the market. Listing.

In the structure of a general oxide semiconductor thin film transistor, the contact resistance between the oxide semiconductor layer and the source/drain material can significantly affect the overall electrical performance of the oxide semiconductor thin film transistor. As shown in Fig. 1, in the case where the size of the thin film transistor is fixed by the channel width (W), the channel length (L) becomes smaller and smaller, and it can be found that when L is reduced to 15 μm or less, the oxide semiconductor thin film transistor is obtained. Electrical performance will shift. Therefore, in order to improve the performance of the oxide semiconductor thin film transistor, it is necessary to improve the contact resistance between the oxide semiconductor layer and the source/drain. At present, it is common practice to use plasma treatment or to directly contact an oxide semiconductor layer with a material having a high hydrogen content to generate hydrogen diffusion so that a portion of the oxide semiconductor layer which is expected to be in contact with the source/drain is partially formed. The resistivity is reduced. However, the above-mentioned plasma treatment method tends to cause unstable resistance of the treated oxide semiconductor layer, and direct contact with a material having a high hydrogen content to generate hydrogen diffusion is difficult to control the diffusion range, which is likely to cause the original The oxide semiconductor layer to be used as a conduction region is susceptible to diffusion and seriously affects the element characteristics of the thin film transistor, particularly in the design of a short-channel thin film transistor.

One of the main objects of the present invention is to provide an oxide semiconductor thin film transistor and a method of fabricating the same, which utilizes a hydrogen diffusion control layer to control the state of hydrogen entering the oxide semiconductor layer, thereby preventing hydrogen from entering the conduction region of the oxide semiconductor layer and affecting it. To the element characteristics of the thin film transistor, the conduction region defined herein is the shortest distance that the oxide semiconductor thin film transistor ideally moves electrons.

An embodiment of the present invention provides an oxide semiconductor thin film transistor including a substrate, a patterned oxide semiconductor layer, a patterned gate dielectric layer, a gate, a hydrogen diffusion control layer, and a hydrogen source layer. , a source and a bungee. The patterned oxide semiconductor layer is disposed on the substrate. A patterned gate dielectric layer is disposed on the patterned oxide semiconductor layer. The gate is disposed on the patterned gate dielectric layer. The hydrogen diffusion control layer is disposed on the gate and the patterned oxide semiconductor layer, and the hydrogen diffusion control layer covers the gate and the patterned gate dielectric layer. The hydrogen source layer is disposed on the hydrogen diffusion control layer and the patterned oxide semiconductor layer, and the hydrogen source layer has a hydrogen content greater than a hydrogen content of the hydrogen diffusion control layer. The source and the drain are disposed on the hydrogen source layer, and the source and the drain are in contact with and electrically connected to the patterned oxide semiconductor layer.

Another embodiment of the present invention provides a method of fabricating an oxide semiconductor thin film transistor, comprising the following steps. Forming a patterned oxide semiconductor layer on a substrate; forming a patterned gate dielectric layer on the patterned oxide semiconductor layer; forming a gate on the patterned gate dielectric layer; and forming a gate and a pattern Forming a hydrogen diffusion control layer on the oxide semiconductor layer, wherein the hydrogen diffusion control layer covers the gate and the patterned gate dielectric layer; forming a hydrogen source layer on the hydrogen diffusion control layer and the patterned oxide semiconductor layer Wherein the hydrogen source layer has a hydrogen content greater than the hydrogen diffusion control layer; and a source and a drain are formed on the hydrogen source layer, wherein the source and the drain are in contact with the patterned oxide semiconductor layer Electrical connection.

The oxide semiconductor thin film electro-crystal system of the present invention utilizes a hydrogen diffusion control layer covering the gate and the patterned gate dielectric layer to control the diffusion of hydrogen in the hydrogen source layer to the patterned oxide semiconductor layer, and can be avoided Hydrogen in the hydrogen source layer diffuses through the patterned gate dielectric layer to the conduction region in the patterned gate dielectric layer, whereby a doped region can be formed in the patterned oxide semiconductor layer while ensuring the conduction region The electrical condition, in turn, enables an oxide semiconductor thin film transistor having a short channel design.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

Please refer to Figures 2 to 6. 2 to 6 are schematic views showing a method of fabricating an oxide semiconductor thin film transistor according to a first embodiment of the present invention. The manufacturing method of the oxide semiconductor thin film transistor of this embodiment includes the following steps. First, as shown in FIG. 2, the patterned oxide semiconductor layer 20 is formed on the substrate 10. The substrate 10 may include a rigid substrate such as a glass substrate and a ceramic substrate, a flexible substrate such as a plastic substrate or other suitable material. The material of the patterned oxide semiconductor layer 20 may include indium gallium zinc oxide, zinc oxide, indium zinc oxide, indium gallium oxide or other suitable oxide semiconductor material, and the patterned oxide semiconductor layer 20 may be formed by, for example, lithography. The etching process or the like achieves a patterning effect or is formed directly by a roll to roll method, but is not limited thereto. Next, the patterned gate dielectric layer 30 and the gate 40 are formed on the patterned oxide semiconductor layer 20. The patterned gate dielectric layer 30 and the gate 40 can be defined by the same photoresist pattern (not shown), so that the pattern of the patterned gate dielectric layer 30 and the pattern of the gate 40 are perpendicular. Self-aligned effects can be achieved on Z, but are not limited to this. The patterned gate dielectric layer 30 can be a single layer or multiple layers of dielectric material, and the material thereof can include inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride. And with a metal oxide (such as alumina), an organic material such as an acrylic resin or other suitable dielectric material. In addition, the gate 40 may include at least one of a metal material such as aluminum, copper, silver, chromium, titanium, molybdenum, a composite layer of the above materials, or an alloy of the above materials, but not limited thereto. A material of conductive nature.

Next, as shown in FIG. 3, a hydrogen diffusion control layer 50 is formed on the patterned gate dielectric layer 30. And as shown in FIG. 4, the hydrogen diffusion control layer 50 is patterned. In this step, the hydrogen diffusion control layer 50, the patterned gate dielectric layer 30 and the gate 40 are defined by the same mask. The pattern determines the size of the hydrogen diffusion control layer 50 covering the patterned gate dielectric layer 30 using the amount of exposure. In detail, the hydrogen diffusion control layer 50 has a U-shape, completely covering the side edge 30S of the patterned gate dielectric layer 30 and the gate 40, and the junction 30F of the side edge 30S and the patterned oxide semiconductor layer 20, and hydrogen diffusion. The control layer 50 extends from the top surface S of the gate 40 in the vertical direction Z along the side 30S toward the patterned oxide semiconductor layer 20, and extends no more than the hydrogen diffusion control layer 50 is vertically projected on the substrate 10 at the top surface S. Projection range. The horizontal direction H is preferably orthogonal to the vertical direction Z, and the vertical direction Z is preferably substantially orthogonal to the surface of the substrate 10, but is not limited thereto. In the present embodiment, the hydrogen diffusion control layer 50 covers only the side 30S of the patterned gate dielectric layer 30 and the patterned oxide semiconductor except for the gate electrode 40 and the patterned gate dielectric layer 30. At the junction 30F of the layer 20, the hydrogen diffusion control layer 50 does not cover both ends of the patterned oxide semiconductor layer 20 in the horizontal direction H, but the invention is not limited thereto. In other embodiments of the present invention, it is also possible to cover the patterned oxide semiconductor layer 20 or at least both ends of the patterned oxide semiconductor layer 20 in the horizontal direction H as needed. The hydrogen diffusion control layer 50 may include an insulating material having a lower hydrogen content than the hydrogen source layer 60, including tantalum nitride, hafnium oxide, hafnium oxynitride or a metal oxide, and the metal oxide may be, for example, aluminum oxide. ), calcium oxide, molybdenum oxide, zinc oxide, indium oxide, gallium oxide, indium gallium oxide, indium gallium zinc oxide (indium gallium zinc oxide), indium zinc oxide, indium tin oxide, titanium oxide, tin oxide, group III metal oxide, group IV metal An oxide or a Group 5 metal oxide, as well as other suitable metal oxide materials. The hydrogen content here is the hydrogen content of the hydrogen diffusion control layer 50 after the process, and the hydrogen diffusion control layer 50 of the present embodiment is preferably a densely structured alumina, thereby achieving better prevention of hydrogen diffusion. Effect, but not limited to this. The hydrogen diffusion control layer 50 can be formed by chemical vapor deposition or physical vapor deposition, and the hydrogen content can be reduced by the process environment during the process and parameter adjustment. Further, the thickness of the hydrogen diffusion control layer 50 is between 100 angstroms and 1000 angstroms, preferably between 100 angstroms and 500 angstroms, but is not limited thereto. It should be noted that the hydrogen diffusion control layer 50 of the present embodiment is disposed corresponding to the gate 40 and the patterned gate dielectric layer 30, so that the same mask used in the process of the gate 40 can be used for hydrogen. The diffusion control layer 50 forms a patterning effect, that is, the same mask can be used with the adjustment of the exposure dose to form a corresponding photoresist pattern required for patterning the hydrogen diffusion control layer 50, thereby reducing the mask. Demand and reduce production costs, but not limited to this.

Thereafter, as shown in FIG. 5, a hydrogen source layer 60 is formed on the substrate 10, the patterned oxide semiconductor layer 20, and the hydrogen diffusion control layer 50. The hydrogen content of the hydrogen source layer 60 is greater than the hydrogen content of the hydrogen diffusion control layer 50. The material of the hydrogen source layer 60 may include tantalum nitride, tantalum oxide, niobium oxynitride or other suitable insulating material having a high hydrogen content, and the hydrogen source layer 60 may include tantalum nitride or the like having a higher hydrogen content after the process reaction. After the process, the amount of hydrogen is higher than that of the hydrogen diffusion control layer 50. The hydrogen source layer 60 can also be formed by chemical vapor deposition or physical vapor deposition, and the hydrogen content can be increased by the process environment and parameter adjustment during the process. For example, when chemical vapor deposition is used to form the hydrogen nitride source layer 60 of tantalum nitride, the process temperature may be 280 ° C, and the introduced reaction gas may include germanium methane (SiH ₄ ) and ammonia gas (NH _{3 ).} And the amount of methane (SiH ₄ ) and ammonia (NH ₃ ) can be 200 sccm and 1200 sccm, respectively, thereby forming a tantalum nitride having a higher hydrogen content than the hydrogen diffusion control layer 50, but not limit. The hydrogen source layer 60 of the present embodiment preferably has a hydrogen content of between 15 atoms/cm ³ and 27 atoms/cm ^{3 for} having sufficient hydrogen to diffuse into the patterned oxide semiconductor layer 20 to form Doped region 20B, but not limited thereto. Since the hydrogen diffusion control layer 50 of the present embodiment does not cover both ends of the patterned oxide semiconductor layer 20 in the horizontal direction H, both ends of the patterned oxide semiconductor layer 20 in the horizontal direction H are exposed to the hydrogen diffusion control layer. In addition to 50, it is directly in contact with the hydrogen source layer 60, whereby the effect of diffusing the hydrogen component in the hydrogen source layer 60 to the corresponding patterned oxide semiconductor layer 20 can be enhanced, thereby reducing the resistivity of the doped region 20B. In the present embodiment, the patterned oxide semiconductor layer 20 is in direct contact with the hydrogen source layer 60 to form two doped regions 20B, and the hydrogen diffusion control layer 50, the gate 40, and the patterned gate dielectric layer. The region corresponding to 30 still maintains the conductive region 20A having semiconductor characteristics. In other words, the patterned oxide semiconductor layer 20 of the present embodiment may include a conductive region 20A and two doped regions 20B after the hydrogen source layer 60 is formed, and the gate 40 overlaps the conductive region 20A in the vertical direction Z. The two doped regions 20B are respectively located on both sides of the conductive region 20A in the horizontal direction H, and the resistivity of the doped region 20B is smaller than the resistivity of the conductive region 20A.

It should be noted that since the hydrogen diffusion control layer 50 of the present embodiment encapsulates the patterned gate dielectric layer 30, hydrogen in the hydrogen source layer 60 can be prevented from laterally passing through the patterned gate dielectric layer 30. It affects the electrical condition of the conductive region 20A. The hydrogen diffusion control layer 50 covering the interface 30F of the patterned gate dielectric layer 30 and the patterned oxide semiconductor layer 20 can also be used to control the range of the doped region 20B to avoid the doping region 20B. The range is too large to cause the entire patterned oxide semiconductor layer 20 to be electrically conductive. In the present embodiment, the hydrogen diffusion control layer 50 disposed on the gate 40 and covering the gate 40 and the patterned gate dielectric layer 30 has a first width W1 in the horizontal direction H and the gate 40 in the horizontal direction. H has a second width W2, the conductive region 20A has a third width W3 in the horizontal direction H, and the first width W1 of the hydrogen diffusion control layer 50 is greater than or equal to the third width W3 of the conductive region 20A. The width of the conductive region 20A can be controlled by adjusting the diffusion state of the hydrogen of the hydrogen source layer 60. For example, when the hydrogen diffusion state of the hydrogen source layer 60 is strong, the third width W3 of the conductive region 20A may be smaller than the gate. The second width of 40 is W2. In addition, the manufacturing method of the embodiment may optionally further include a heat treatment process to assist the diffusion effect of hydrogen of the hydrogen source layer 60, but is not limited thereto.

Then, as shown in FIG. 6, a plurality of contact openings V are formed in the hydrogen source layer 60, and the contact openings V extend through the hydrogen source layer 60 to expose portions of the doped regions 20B. Thereafter, a source 70S and a drain 70D are formed on the hydrogen source layer 60, whereby the oxide semiconductor thin film transistor 101 as shown in Fig. 5 is completed. The source 70S and the drain 70D are in contact with and electrically connected to the two doped regions 20B through the contact opening V. The source 70S and the drain 70D may respectively comprise a metal material such as aluminum, copper, silver, chromium, titanium, molybdenum. At least one of them, a composite layer of the above materials or an alloy of the above materials, but not limited thereto, other materials having conductive properties may be used.

As shown in FIG. 6, the oxide semiconductor thin film transistor 101 of the present embodiment includes a patterned oxide semiconductor layer 20, a patterned gate dielectric layer 30, a gate 40, a hydrogen diffusion control layer 50, and a hydrogen source layer 60. , source 70S and bungee 70D. The patterned oxide semiconductor layer 20 is disposed on the substrate 10. The patterned gate dielectric layer 30 is disposed on the patterned oxide semiconductor layer 20. The gate 40 is disposed on the patterned gate dielectric layer 30. The hydrogen diffusion control layer 50 is disposed on the gate 40 and the patterned oxide semiconductor layer 20, and the hydrogen diffusion control layer 50 covers the gate 40 and the patterned gate dielectric layer 30. The hydrogen source layer 60 is provided on the hydrogen diffusion control layer 50 and the patterned oxide semiconductor layer 20, and the hydrogen source layer 60 has a hydrogen content greater than that of the hydrogen diffusion control layer 50. The source 70S and the drain 70D are disposed on the hydrogen source layer 60, and the source 70S and the drain 70D are in contact with and electrically connected to the two doped regions 20B through the contact opening V. The material properties of the respective elements in the oxide semiconductor thin film transistor 101 have been described in the above-described manufacturing method, and thus will not be described herein. It should be noted that the hydrogen diffusion control layer 50 of the present embodiment preferably directly contacts the patterned oxide semiconductor layer 20, and the hydrogen source layer 60 preferably directly contacts the hydrogen diffusion control layer 50, and the hydrogen source layer 60 is in direct contact. Doped region 20B, but not limited thereto. The hydrogen diffusion control layer 50 of the present embodiment can control the diffusion of hydrogen in the hydrogen source layer 60 to the patterned oxide semiconductor layer 20 while avoiding hydrogen in the hydrogen source layer 60 passing through the patterned gate dielectric layer. 30 is diffused into the conductive region 20A in the patterned oxide semiconductor layer 20. Under this design, even if the gate 40 and the patterned gate dielectric layer 30 need to be reduced due to the short channel design, the range of the doped region 20B can be controlled by the hydrogen diffusion control layer 50 and the conduction region 20A can be avoided. The electrical properties are affected, thereby enhancing the element characteristics of the oxide semiconductor thin film transistor 101.

For example, please refer to Figures 6 to 9. Fig. 7 is a graph showing the relationship between the gate current (W) and the gate current (gate voltage) of the oxide semiconductor thin film transistor 101 of the first embodiment in a design condition in which the channel width (W) and the channel length (L) are both 5 μm. Fig. 8 is a schematic view showing an oxide semiconductor thin film transistor 200 of a comparative example. Fig. 9 is a graph showing the relationship between the gate current and the gate voltage of the oxide semiconductor thin film transistor 200 of the comparative example under the design conditions of a channel width and a channel length of 5 μm. The oxide semiconductor thin film transistor 200 of this comparative example is similar to the oxide semiconductor thin film transistor 101 except that the hydrogen diffusion controlling layer 50 of the first embodiment is not included. As shown in FIGS. 6 and 7, the oxide semiconductor thin film transistor 101 of the first embodiment can still have a relatively high ratio of the channel width to the channel length in the case where the hydrogen diffusion control layer 50 is provided. Good film crystal properties with a carrier mobility of up to about 22 cm ² /VS. In contrast, as shown in FIGS. 8 and 9, since the hydrogen diffusion control layer is not provided, the oxide semiconductor thin film transistor of the comparative example is biased in a relatively high ratio of the channel width to the channel length. Without thin film transistor properties.

The different embodiments of the present invention are described below, and the following description is mainly for the sake of simplification of the description of the embodiments, and the details are not repeated. In addition, the same elements in the embodiments of the present invention are denoted by the same reference numerals to facilitate the comparison between the embodiments.

Please refer to Figure 10. Fig. 10 is a view showing the oxide semiconductor thin film transistor 102 of the second embodiment of the present invention. The difference from the first embodiment described above is that the third width W3 of the conductive region 20A of the present embodiment is smaller than the first width W1 of the hydrogen diffusion control layer 50, and the third width W3 of the conductive region 20A is substantially related to the gate. The second width W2 of the pole 40 is the same, but is not limited thereto.

Please refer to Figure 11. Fig. 11 is a view showing the oxide semiconductor thin film transistor 103 of the third embodiment of the present invention. The difference from the first embodiment described above is that the third width W3 of the conductive region 20A can be made smaller than the second width W2 of the gate 40 by enhancing the diffusion effect of hydrogen in the hydrogen source layer 60. The purpose of further shortening the channel width of the oxide semiconductor thin film transistor 103 is further achieved. The manner of enhancing the hydrogen diffusion effect in the hydrogen source layer 60 may include increasing the concentration of hydrogen in the strong hydrogen source layer 60 (for example, introducing hydrogen into the hydrogen source layer 60), applying an auxiliary treatment such as heat treatment or other suitable. A way to enhance the hydrogen diffusion effect.

Please refer to Figure 12 and Figure 13. 12 and 13 are schematic views showing a method of fabricating an oxide semiconductor thin film transistor according to a fourth embodiment of the present invention. The difference from the first embodiment described above is that, as shown in FIG. 12, the hydrogen diffusion control layer 50 of the present embodiment can completely cover the patterned oxide semiconductor layer 20, the patterned gate dielectric layer 30, and the gate 40. Therefore, the hydrogen diffusion control layer 50 covers both ends of the patterned oxide semiconductor layer 20 in the horizontal direction H, and the hydrogen source layer 60 does not directly contact the patterned oxide semiconductor layer 20 and the subsequently formed doped region 20B. In this way, it is possible to avoid that the hydrogen diffusion effect in the hydrogen source layer 60 is too strong, so that the range of the correspondingly formed doping region 20B is too large, and thus affects the electrical condition of the conduction region 20A. As shown in FIG. 13, when the oxide semiconductor thin film transistor 104 of the present embodiment is formed, since the doping region 20B is covered by the hydrogen diffusion controlling layer 50 and the hydrogen source layer 60, the contact opening V needs to penetrate the hydrogen. The source layer 60 and the hydrogen diffusion control layer 50 partially expose the two doped regions 20B, and the source 70S and the drain 70D can be electrically connected to the doped region 20B through the contact opening V. Further, the hydrogen diffusion control layer 50 of the present embodiment further has an extension portion 50A covering the both ends of the patterned oxide semiconductor layer 20 in the horizontal direction H.

Please refer to Figure 14, and please refer to Figure 13 together. Fig. 14 is a view showing the relationship between the gate current and the gate voltage of the oxide semiconductor thin film transistor 104 of the present embodiment in a design condition in which the channel width and the channel length are both 5 μm. As shown in FIGS. 14 and 13, the oxide semiconductor thin film transistor 104 of the present embodiment can be excellent in a condition in which the ratio of the channel width to the channel length is relatively high in the case where the hydrogen diffusion control layer 50 is provided. The properties of the thin film transistor, and its carrier mobility can reach about 13 cm ² /VS. Although the carrier mobility of the oxide semiconductor thin film transistor 104 of the present embodiment is lower than that of the first embodiment described above, since the hydrogen diffusion control layer 50 of the present embodiment covers the patterned oxide semiconductor layer 20, the hydrogen source layer 60 is provided. Since the patterned oxide semiconductor layer 20 is not directly contacted, the hydrogen concentration control of the hydrogen source layer 60 can be relatively loosely controlled to facilitate the process. In contrast, as shown in FIGS. 8 and 9, since the hydrogen diffusion control layer is not provided, the oxide semiconductor thin film transistor of the comparative example is biased in a relatively high ratio of the channel width to the channel length. Without thin film transistor properties.

In summary, the oxide semiconductor thin film electromorphic system of the present invention utilizes a hydrogen diffusion control layer to control the diffusion of hydrogen in the hydrogen source layer to the patterned oxide semiconductor layer while avoiding hydrogen passing through the pattern in the hydrogen source layer. The gate dielectric layer is diffused into the conductive region in the patterned gate dielectric layer to affect the electrical condition of the conductive region. Therefore, even if the gate electrode and the patterned gate dielectric layer in the oxide semiconductor thin film transistor need to be reduced in order to conform to the short channel design, the formation range of the doped region can be controlled by the hydrogen diffusion control layer and the conduction region can be avoided. The electrical properties are affected, so that the purpose of improving the component characteristics of the oxide semiconductor thin film transistor can be achieved. In addition, the method for fabricating the oxide semiconductor thin film transistor of the present invention can define the hydrogen diffusion control layer, the patterned gate dielectric layer and the gate pattern by using the same mask, thereby achieving the purpose of reducing the manufacturing cost. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Substrate
20‧‧‧ patterned oxide semiconductor layer
20A‧‧‧Transduction zone
20B‧‧‧Doped area
30‧‧‧ patterned gate dielectric layer
30F‧‧‧ Junction
30S‧‧‧ side
40‧‧‧ gate
50‧‧‧ Hydrogen diffusion control layer
50A‧‧‧Extension
60‧‧‧ Hydrogen source layer
70D‧‧‧Bungee
70S‧‧‧ source
101-104‧‧‧Oxide semiconductor thin film transistor
200‧‧‧Oxide semiconductor thin film transistor
H‧‧‧ horizontal direction
S‧‧‧ top surface
V‧‧‧Contact opening
W1‧‧‧ first width
W2‧‧‧ second width
W3‧‧‧ third width
Z‧‧‧Vertical direction

FIG. 1 is a diagram showing the relationship between the gate current and the gate voltage of an oxide semiconductor thin film transistor of the prior art. 2 to 6 are schematic views showing a method of fabricating an oxide semiconductor thin film transistor according to a first embodiment of the present invention. Fig. 7 is a view showing the relationship between the gate current and the gate voltage of the oxide semiconductor thin film transistor of the first embodiment of the present invention. Fig. 8 is a schematic view showing an oxide semiconductor thin film transistor of a comparative example. Fig. 9 is a graph showing the relationship between the gate current and the gate voltage of the oxide semiconductor thin film transistor of the comparative example. Fig. 10 is a view showing the oxide semiconductor thin film transistor of the second embodiment of the present invention. Fig. 11 is a view showing the oxide semiconductor thin film transistor of the third embodiment of the present invention. 12 and 13 are schematic views showing a method of fabricating an oxide semiconductor thin film transistor according to a fourth embodiment of the present invention. Fig. 14 is a view showing the relationship between the gate current and the gate voltage of the oxide semiconductor thin film transistor of the fourth embodiment of the present invention.

10‧‧‧Substrate

20‧‧‧ patterned oxide semiconductor layer

20A‧‧‧Transduction zone

20B‧‧‧Doped area

30‧‧‧ patterned gate dielectric layer

30F‧‧‧ Junction

30S‧‧‧ side

40‧‧‧ gate

50‧‧‧ Hydrogen diffusion control layer

60‧‧‧ Hydrogen source layer

70D‧‧‧Bungee

70S‧‧‧ source

101‧‧‧Oxide semiconductor thin film transistor

H‧‧‧ horizontal direction

S‧‧‧ top surface

V‧‧‧Contact opening

W1‧‧‧ first width

W2‧‧‧ second width

W3‧‧‧ third width

Z‧‧‧Vertical direction

Claims (17)

An oxide semiconductor thin film transistor comprising: a substrate; a patterned oxide semiconductor layer disposed on the substrate; a patterned gate dielectric layer disposed on the patterned oxide semiconductor layer; a gate Provided on the patterned gate dielectric layer; a hydrogen diffusion control layer disposed on the gate and the patterned oxide semiconductor layer, wherein the hydrogen diffusion control layer encapsulates the gate and the patterning a gate dielectric layer; a hydrogen source layer disposed on the hydrogen diffusion control layer and the patterned oxide semiconductor layer, wherein the hydrogen source layer has a hydrogen content greater than a hydrogen content of the hydrogen diffusion control layer; A source and a drain are disposed on the hydrogen source layer, wherein the source and the drain are in contact with and electrically connected to the patterned oxide semiconductor layer. The oxide semiconductor thin film transistor according to claim 1, wherein the hydrogen diffusion control layer directly contacts the patterned oxide semiconductor layer, and the hydrogen source layer directly contacts the hydrogen diffusion control layer. The oxide semiconductor thin film transistor according to claim 1, wherein the hydrogen source layer directly contacts the patterned oxide semiconductor layer. The oxide semiconductor thin film transistor according to claim 1, wherein the hydrogen diffusion control layer covers the patterned gate dielectric layer and the gate, and the hydrogen diffusion control layer is from a top surface of the gate One side of the gate extends toward the patterned oxide semiconductor layer and extends beyond a projection range in which the hydrogen diffusion control layer is vertically projected on the substrate. The oxide semiconductor thin film transistor according to claim 4, wherein the hydrogen diffusion control layer further has an extension portion in a horizontal direction, the extension portion covering the patterned oxide semiconductor layer at both ends in the horizontal direction. The oxide semiconductor thin film transistor of claim 1, further comprising a plurality of contact openings extending through the hydrogen source layer, wherein the source and the drain pass through the contact openings and the patterned oxide semiconductor The layers are in contact and electrically connected. The oxide semiconductor thin film transistor of claim 6, wherein the contact openings further extend through the hydrogen diffusion control layer. The oxide semiconductor thin film transistor according to claim 1, wherein the hydrogen diffusion controlling layer comprises a metal oxide, tantalum nitride, hafnium oxide or hafnium oxynitride. The oxide semiconductor thin film transistor according to claim 1, wherein the hydrogen diffusion control layer has a thickness of from 100 angstroms to 500 angstroms. The oxide semiconductor thin film transistor according to claim 1, wherein the hydrogen source layer comprises tantalum nitride, hafnium oxide or hafnium oxynitride. The oxide semiconductor thin film transistor according to claim 1, wherein the patterned oxide semiconductor layer comprises indium gallium zinc oxide, zinc oxide, indium zinc oxide or indium gallium oxide. The oxide semiconductor thin film transistor according to claim 1, wherein the hydrogen source layer has a hydrogen content of between 15 atoms/cm ³ and 27 atoms/cm ³ . A method for fabricating an oxide semiconductor thin film transistor, comprising: forming a patterned oxide semiconductor layer on a substrate; forming a patterned gate dielectric layer on the patterned oxide semiconductor layer; Forming a gate on the gate layer; forming a hydrogen diffusion control layer on the gate and the patterned oxide semiconductor layer, wherein the hydrogen diffusion control layer encapsulates the gate and the patterned gate dielectric Forming a hydrogen source layer on the hydrogen diffusion control layer and the patterned oxide semiconductor layer, wherein the hydrogen source layer has a hydrogen content greater than a hydrogen content of the hydrogen diffusion control layer; and on the hydrogen source layer A source and a drain are formed, wherein the source and the drain are in contact with and electrically connected to the patterned oxide semiconductor layer. The method of fabricating an oxide semiconductor thin film transistor according to claim 13, wherein the hydrogen diffusion control layer covers the patterned gate dielectric layer and the gate, and the hydrogen diffusion control layer is from a top surface of the gate The patterned oxide semiconductor layer extends along a side of the gate and extends beyond a projection range in which the hydrogen diffusion control layer is perpendicularly projected onto the substrate. The method of fabricating an oxide semiconductor thin film transistor according to claim 14, wherein the hydrogen diffusion control layer, the patterned gate dielectric layer and the gate system define a pattern using a same mask. The method of fabricating an oxide semiconductor thin film transistor according to claim 13, wherein the hydrogen diffusion controlling layer comprises a metal oxide, tantalum nitride, hafnium oxide or hafnium oxynitride. The method for fabricating an oxide semiconductor thin film transistor according to claim 13, wherein the hydrogen source layer has a hydrogen content of between 15 atoms/cm ³ and 27 atoms/cm ³ .