TWI613706B - Oxide semiconductor thin film transistor and manufacturing method thereof - Google Patents

Abstract

An oxide semiconductor thin film transistor includes a patterned oxide semiconductor layer, a patterned gate dielectric layer, a gate electrode, a hydrogen diffusion control layer, a hydrogen source layer, a source electrode, and a drain electrode. The patterned oxide semiconductor layer is disposed on a substrate. The patterned gate dielectric layer is disposed on the patterned oxide semiconductor layer. The gate is disposed on the patterned gate dielectric layer. The hydrogen diffusion control layer is disposed on the gate and the patterned oxide semiconductor layer, and the hydrogen diffusion control layer covers the gate and the patterned gate dielectric layer. The hydrogen source layer is disposed on the hydrogen diffusion control layer and the patterned oxide semiconductor layer, the source drain is disposed on the hydrogen source layer, and the hydrogen content of the hydrogen source layer is greater than the hydrogen content of the hydrogen diffusion control layer.

Description

Oxide semiconductor thin film transistor and manufacturing method thereof

The invention relates to an oxide semiconductor thin film transistor and a manufacturing method thereof, and more particularly to an oxide semiconductor thin film transistor using a hydrogen diffusion control layer to control the state of hydrogen entering the oxide semiconductor layer and a manufacturing method thereof.

In recent years, the application of various displays has developed rapidly, and thin film transistor (TFT) is a kind of semiconductor element widely used in display technology, such as liquid crystal display (LCD), organic light emitting diode (organic light emitting diode (OLED)) displays and electronic paper (electronic paper, E-paper) displays. The thin film transistor system is used to provide voltage or current switching, so that the display pixels in various displays can display bright, dark and grayscale display effects.

The thin film transistors currently used in the display industry can be differentiated according to the semiconductor layer materials used, including amorphous silicon TFTs (a-Si TFTs), poly silicon TFTs (poly silicon TFTs), and oxide semiconductors. Thin film transistor (oxide semiconductor TFT). Among them, the oxide semiconductor thin film transistor is an oxide semiconductor material that has been newly emerging in recent years. Such materials generally have an amorphous structure, so they are less applicable to the problem of poor uniformity on large-size panels, and can be Films are formed by a variety of methods, such as sputtering, spin-on, and inkjet printing. Because the electron mobility of oxide semiconductor thin film transistors can generally be several times higher than that of amorphous silicon thin film transistors and has the above-mentioned process advantages, there are already some commercialized products using oxide semiconductor thin film transistors on the market. Go public.

In the structure of a general oxide semiconductor thin film transistor, the contact resistance between the oxide semiconductor layer and the source / drain material will significantly affect the overall electrical performance of the oxide semiconductor thin film transistor. As shown in Figure 1, when the size of the thin film transistor is fixed with the channel width (W), the channel length (L) is getting smaller and smaller. It can be found that when L is reduced below 15 microns, the oxide semiconductor thin film transistor Electrical performance will shift. Therefore, in order to improve the efficiency of the oxide semiconductor thin film transistor, it is necessary to improve the contact resistance between the oxide semiconductor layer and the source / drain. At present, the general practice is to use plasma treatment or directly contact the oxide semiconductor layer with a material containing high hydrogen content to generate hydrogen diffusion, so that part of the area of the oxide semiconductor layer which is expected to be in contact with the source / drain electrode. The resistivity decreases. However, the above-mentioned plasma treatment method is likely to cause the resistance state of the oxide semiconductor layer after the treatment to be unstable, and the direct contact with a material with a high hydrogen content to generate hydrogen diffusion is difficult to control the diffusion range, which may easily cause the original The oxide semiconductor layer that is to be used as a conductive region is susceptible to diffusion and severely affects the characteristics of thin film transistors, especially in the design of short channel thin film transistors.

One of the main objects of the present invention is to provide an oxide semiconductor thin film transistor and a method for manufacturing the same. A hydrogen diffusion control layer is used to control the state of hydrogen entering the oxide semiconductor layer and avoid the influence of hydrogen entering the conductive region of the oxide semiconductor layer. To the element characteristics of the thin film transistor, the conduction region defined here is the shortest distance that the electrons of the oxide semiconductor thin film transistor ideally move.

An embodiment of the present invention provides an oxide semiconductor thin film transistor including a substrate, a patterned oxide semiconductor layer, a patterned gate dielectric layer, a gate electrode, a hydrogen diffusion control layer, and a hydrogen source layer. , A source, and a drain. The patterned oxide semiconductor layer is disposed on a substrate. The patterned gate dielectric layer is disposed on the patterned oxide semiconductor layer. The gate is disposed on the patterned gate dielectric layer. The hydrogen diffusion control layer is disposed on the gate and the patterned oxide semiconductor layer, and the hydrogen diffusion control layer covers the gate and the patterned gate dielectric layer. The hydrogen source layer is disposed on the hydrogen diffusion control layer and the patterned oxide semiconductor layer, and the hydrogen content of the hydrogen source layer is greater than the hydrogen content of the hydrogen diffusion control layer. The source and the drain are disposed on the hydrogen source layer, and the source and the drain are in contact with and electrically connected to the patterned oxide semiconductor layer.

Another embodiment of the present invention provides a method for manufacturing an oxide semiconductor thin film transistor, including the following steps. Forming a patterned oxide semiconductor layer on a substrate; forming a patterned gate dielectric layer on the patterned oxide semiconductor layer; forming a gate on the patterned gate dielectric layer; forming a gate and a pattern A hydrogen diffusion control layer is formed on the oxide semiconductor layer, wherein the hydrogen diffusion control layer covers the gate and the patterned gate dielectric layer; a hydrogen source layer is formed on the hydrogen diffusion control layer and the patterned oxide semiconductor layer Wherein the hydrogen content of the hydrogen source layer is greater than that of the hydrogen diffusion control layer; and a source and a drain are formed on the hydrogen source layer, wherein the source and the drain are in contact with the patterned oxide semiconductor layer and Electrical connection.

The oxide semiconductor thin film transistor system of the present invention uses a hydrogen diffusion control layer covering the gate and the patterned gate dielectric layer to control the diffusion of hydrogen from the hydrogen source layer to the patterned oxide semiconductor layer, and can avoid The hydrogen in the hydrogen source layer is diffused to the conductive region in the patterned gate dielectric layer through the patterned gate dielectric layer, thereby forming a doped region in the patterned oxide semiconductor layer while ensuring the conduction region. The electrical condition can further realize an oxide semiconductor thin film transistor with a short channel design.

In order to make a person skilled in the art who is familiar with the technical field of the present invention further understand the present invention, the preferred embodiments of the present invention are enumerated below, and in conjunction with the accompanying drawings, the constitutional content of the present invention and the desired effects are described in detail. .

Please refer to Figure 2 to Figure 6. FIG. 2 to FIG. 6 are schematic diagrams illustrating a method for manufacturing an oxide semiconductor thin film transistor according to a first embodiment of the present invention. The method for manufacturing an oxide semiconductor thin film transistor in this embodiment includes the following steps. First, as shown in FIG. 2, a patterned oxide semiconductor layer 20 is formed on a substrate 10. The substrate 10 may include a rigid substrate such as a glass substrate and a ceramic substrate, a flexible substrate such as a plastic substrate, or a substrate formed of other suitable materials. The material of the patterned oxide semiconductor layer 20 may include indium gallium zinc oxide, zinc oxide, indium zinc oxide, indium gallium oxide, or other suitable oxide semiconductor materials, and the patterned oxide semiconductor layer 20 may be formed by, for example, lithography, A process such as etching achieves a patterning effect or is formed directly by a roll to roll method, but is not limited thereto. Next, a patterned gate dielectric layer 30 and a gate electrode 40 are formed on the patterned oxide semiconductor layer 20. The patterned gate dielectric layer 30 and the gate 40 can be defined by the same photoresist pattern (not shown), so that the pattern of the patterned gate dielectric layer 30 and the pattern of the gate 40 are perpendicular to each other. The self-aligned effect can be achieved on Z, but it is not limited to this. The patterned gate dielectric layer 30 may be a single-layer or multi-layer dielectric material layer, and its material may include inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride. And metal oxides (such as alumina), organic materials such as acrylic resin, or other suitable dielectric materials. In addition, the gate electrode 40 may include a metal material such as at least one of aluminum, copper, silver, chromium, titanium, and molybdenum, a composite layer of the foregoing materials, or an alloy of the foregoing materials, but is not limited thereto, and other materials Materials with conductive properties.

Next, as shown in FIG. 3, a hydrogen diffusion control layer 50 is formed on the patterned gate dielectric layer 30. And as shown in FIG. 4, the patterned hydrogen diffusion control layer 50 is used. In this step, the hydrogen diffusion control layer 50, the patterned gate dielectric layer 30 and the gate 40 are defined using the same mask. In the pattern, the exposure amount is used to determine the size of the hydrogen diffusion control layer 50 covering the patterned gate dielectric layer 30. In detail, the hydrogen diffusion control layer 50 has a zigzag shape, and completely covers the side 30S of the patterned gate dielectric layer 30 and the gate 40 and the boundary 30F between the side 30S and the patterned oxide semiconductor layer 20. The hydrogen diffusion The control layer 50 extends from the top surface S of the gate 40 to the patterned oxide semiconductor layer 20 along the side 30S in the vertical direction Z, and does not extend beyond the top surface S of the hydrogen diffusion control layer 50 which is vertically projected on the substrate 10 Projection range. The horizontal direction H is preferably orthogonal to the vertical direction Z, and the vertical direction Z is preferably substantially orthogonal to the surface of the substrate 10, but is not limited thereto. In this embodiment, in addition to covering the gate 40 and the patterned gate dielectric layer 30, the hydrogen diffusion control layer 50 only covers the side 30S and the patterned oxide semiconductor of the patterned gate dielectric layer 30. At the boundary 30F of the layer 20, the hydrogen diffusion control layer 50 does not cover both ends of the patterned oxide semiconductor layer 20 in the horizontal direction H, but the invention is not limited thereto. In other embodiments of the present invention, if necessary, the patterned oxide semiconductor layer 20 may be completely covered or at least two ends of the patterned oxide semiconductor layer 20 in the horizontal direction H may be covered. The hydrogen diffusion control layer 50 may include an insulating material having a lower hydrogen content than the hydrogen source layer 60, including silicon nitride, silicon oxide, silicon oxynitride, or a metal oxide. The metal oxide may be aluminum oxide, for example. ), Calcium oxide, molybdenum oxide, zinc oxide, indium oxide, gallium oxide, indium gallium oxide, indium gallium zinc oxide (indium gallium zinc oxide), indium zinc oxide, indium tin oxide, titanium oxide, tin oxide, Group III metal oxide, Group IV metal Oxides or Group 5 metal oxides, and other suitable metal oxide materials. The hydrogen content here is the hydrogen content of the hydrogen diffusion control layer 50 after the processing process, and the hydrogen diffusion control layer 50 in this embodiment is preferably alumina with a denser structure, thereby achieving better prevention of hydrogen diffusion. Effect, but not limited to this. The hydrogen diffusion control layer 50 can be formed by chemical vapor deposition or physical vapor deposition, and can reduce the hydrogen content by the process environment and parameter adjustment during the process. In addition, the thickness of the hydrogen diffusion control layer 50 is between 100 angstroms and 1000 angstroms, preferably between 100 angstroms and 500 angstroms, but it is not limited thereto. It is worth noting that the hydrogen diffusion control layer 50 in this embodiment is provided corresponding to the gate 40 and the patterned gate dielectric layer 30, so the same photomask used in the process of manufacturing the gate 40 can be used for hydrogen The diffusion control layer 50 forms a patterning effect, which can use the same photomask and adjust the exposure dose to form the corresponding photoresist pattern required to pattern the hydrogen diffusion control layer 50, thereby reducing the photomask. The effect of demand and reduce production costs, but not limited to this.

Thereafter, as shown in FIG. 5, a hydrogen source layer 60 is formed on the substrate 10, the patterned oxide semiconductor layer 20, and the hydrogen diffusion control layer 50. The hydrogen content of the hydrogen source layer 60 is greater than the hydrogen content of the hydrogen diffusion control layer 50. The material of the hydrogen source layer 60 may include silicon nitride, silicon oxide, silicon oxynitride, or other suitable insulating materials with high hydrogen content. The hydrogen source layer 60 may include silicon nitride or silicon nitride with a higher hydrogen content after a process reaction. After the process reaction, silicon oxide having a higher hydrogen content than that of the hydrogen diffusion control layer 50 is used. The hydrogen source layer 60 can also be formed by chemical vapor deposition or physical vapor deposition, and the hydrogen content can be increased by the process environment and parameter adjustment during the process. For example, when chemical vapor deposition is used to form the silicon nitride hydrogen source layer 60, the process temperature may be 280 ° C, and the reaction gas passed in may include silicon methane (SiH ₄ ) and ammonia gas (NH ₃ ), And the fluxes of methane (SiH ₄ ) and ammonia (NH ₃ ) can be 200 sccm and 1200 sccm, respectively, thereby forming silicon nitride with a hydrogen content higher than that of the hydrogen diffusion control layer 50, but this is not the case. limit. The hydrogen content of the hydrogen source layer 60 in this embodiment is preferably between 15 x 10 ²⁰ atoms / cm ³ and 27 x 10 ²² atoms / cm ^{3 for} sufficient hydrogen to diffuse into the patterned oxide semiconductor layer. The doped region 20B is formed in 20, but is not limited thereto. Since the hydrogen diffusion control layer 50 of this embodiment does not cover both ends of the patterned oxide semiconductor layer 20 in the horizontal direction H, both ends of the patterned oxide semiconductor layer 20 in the horizontal direction H are exposed to the hydrogen diffusion control layer. It is in direct contact with the hydrogen source layer 60 beyond 50, thereby enhancing the effect of diffusing the hydrogen component in the hydrogen source layer 60 to the corresponding patterned oxide semiconductor layer 20, thereby reducing the resistivity of the doped region 20B. In this embodiment, where the patterned oxide semiconductor layer 20 and the hydrogen source layer 60 are in direct contact, two doped regions 20B are formed, and they are in contact with the hydrogen diffusion control layer 50, the gate 40, and the patterned gate dielectric layer. The region corresponding to 30 still maintains the conductive region 20A having semiconductor characteristics. In other words, the patterned oxide semiconductor layer 20 of this embodiment may include a conductive region 20A and two doped regions 20B after the hydrogen source layer 60 is formed. The gate electrode 40 overlaps the conductive region 20A in the vertical direction Z. The two doped regions 20B are respectively located on two sides of the conductive region 20A in the horizontal direction H, and the resistivity of the doped region 20B is smaller than that of the conductive region 20A.

It is worth noting that, since the hydrogen diffusion control layer 50 of this embodiment covers the patterned gate dielectric layer 30, the hydrogen in the hydrogen source layer 60 can be prevented from passing through the patterned gate dielectric layer 30 from the side. Affects the electrical condition of the conductive region 20A. The hydrogen diffusion control layer 50 covering the side 30S of the patterned gate dielectric layer 30 and the interface 30F of the patterned oxide semiconductor layer 20 can also be used to control the range of the doped region 20B and avoid the doped region 20B. The range is too large, so that the entire patterned oxide semiconductor layer 20 is in an electrically conductive state. In this embodiment, the hydrogen diffusion control layer 50 disposed on the gate 40 and covering the gate 40 and the patterned gate dielectric layer 30 has a first width W1 in the horizontal direction H, and the gate 40 is in the horizontal direction. H has a second width W2, the conductive region 20A has a third width W3 in the horizontal direction H, and the first width W1 of the hydrogen diffusion control layer 50 is greater than or equal to the third width W3 of the conductive region 20A. The width of the conductive region 20A can be controlled by adjusting the hydrogen diffusion state of the hydrogen source layer 60. For example, when the hydrogen diffusion state of the hydrogen source layer 60 is strong, the third width W3 of the conductive region 20A may also be smaller than the gate The second width W2 of 40. In addition, the manufacturing method of this embodiment may optionally further include a heat treatment process to assist the hydrogen diffusion effect of the hydrogen source layer 60, but it is not limited thereto.

Then, as shown in FIG. 6, a plurality of contact openings V are formed in the hydrogen source layer 60. The contact openings V penetrate through the hydrogen source layer 60 to expose a part of the doped region 20B. After that, a source electrode 70S and a drain electrode 70D are formed on the hydrogen source layer 60, thereby completing the oxide semiconductor thin film transistor 101 as shown in FIG. 5. The source 70S and the drain 70D are in contact with and electrically connected to the two doped regions 20B through the contact opening V. The source 70S and the drain 70D may include metal materials such as aluminum, copper, silver, chromium, titanium, and molybdenum, respectively. At least one of them, a composite layer of the above materials, or an alloy of the above materials, but is not limited to this, and other materials having conductive properties may be used.

As shown in FIG. 6, the oxide semiconductor thin film transistor 101 of this embodiment includes a patterned oxide semiconductor layer 20, a patterned gate dielectric layer 30, a gate 40, a hydrogen diffusion control layer 50, and a hydrogen source layer 60. , Source 70S and drain 70D. The patterned oxide semiconductor layer 20 is disposed on the substrate 10. The patterned gate dielectric layer 30 is disposed on the patterned oxide semiconductor layer 20. The gate electrode 40 is disposed on the patterned gate dielectric layer 30. The hydrogen diffusion control layer 50 is disposed on the gate 40 and the patterned oxide semiconductor layer 20, and the hydrogen diffusion control layer 50 covers the gate 40 and the patterned gate dielectric layer 30. The hydrogen source layer 60 is disposed on the hydrogen diffusion control layer 50 and the patterned oxide semiconductor layer 20, and the hydrogen content of the hydrogen source layer 60 is greater than the hydrogen content of the hydrogen diffusion control layer 50. The source electrode 70S and the drain electrode 70D are disposed on the hydrogen source layer 60. The source electrode 70S and the drain electrode 70D are in contact with and electrically connected to the two doped regions 20B through the contact opening V. The material characteristics of each element in the oxide semiconductor thin film transistor 101 have been described in the above manufacturing method, so it will not be repeated here. It is worth noting that the hydrogen diffusion control layer 50 of this embodiment is preferably in direct contact with the patterned oxide semiconductor layer 20, the hydrogen source layer 60 is preferably in direct contact with the hydrogen diffusion control layer 50, and the hydrogen source layer 60 is in direct contact The doped region 20B is not limited thereto. The hydrogen diffusion control layer 50 of this embodiment can control the diffusion of hydrogen in the hydrogen source layer 60 to the patterned oxide semiconductor layer 20, and at the same time can prevent hydrogen in the hydrogen source layer 60 from passing through the patterned gate dielectric layer. 30 and diffused to the conductive region 20A in the patterned oxide semiconductor layer 20. Under this design, even if the gate 40 and the patterned gate dielectric layer 30 need to be reduced due to the short channel design, the size of the doped region 20B can be controlled by the hydrogen diffusion control layer 50 and the conduction region 20A can be avoided. The electrical properties are affected, thereby improving the device characteristics of the oxide semiconductor thin film transistor 101.

For example, please refer to Figures 6 to 9. FIG. 7 illustrates the relationship between the drain current and the gate voltage of the oxide semiconductor thin film transistor 101 according to the first embodiment in a design condition in which the channel width (W) and the channel length (L) are both 5 μm. FIG. 8 is a schematic diagram of an oxide semiconductor thin film transistor 200 of a comparative example. FIG. 9 is a graph showing the relationship between the drain current and the gate voltage of the oxide semiconductor thin film transistor 200 of the comparative example under the design condition that the channel width and the channel length are both 5 μm. The oxide semiconductor thin film transistor 200 of this comparative example is similar to the oxide semiconductor thin film transistor 101 except that it does not include the hydrogen diffusion control layer 50 of the first embodiment. As shown in FIG. 6 and FIG. 7, the oxide semiconductor thin film transistor 101 of the first embodiment can still have the condition that the ratio of the channel width to the channel length is relatively high when the hydrogen diffusion control layer 50 is provided. Good thin film transistor characteristics, and its carrier mobility can reach about 22 cm ² / VS. In contrast, as shown in FIGS. 8 and 9, since the hydrogen diffusion control layer is not provided, the oxide semiconductor thin film transistor of this comparative example will be biased to conduct under the condition that the channel width to channel length ratio is relatively high. Does not have thin film transistor characteristics.

The following will describe different embodiments of the present invention, and to simplify the description, the following description mainly details the differences between the embodiments, and will not repeat the same points repeatedly. In addition, the same elements in the embodiments of the present invention are marked with the same reference numerals, so as to facilitate comparison between the embodiments.

Please refer to Figure 10. FIG. 10 is a schematic diagram of an oxide semiconductor thin film transistor 102 according to a second embodiment of the present invention. The difference from the first embodiment is that the third width W3 of the conductive region 20A in this embodiment is smaller than the first width W1 of the hydrogen diffusion control layer 50, and the third width W3 of the conductive region 20A is substantially the same as that of the gate. The second width W2 of the electrode 40 is the same, but it is not limited thereto.

Please refer to Figure 11. FIG. 11 is a schematic diagram showing an oxide semiconductor thin film transistor 103 according to a third embodiment of the present invention. The difference from the first embodiment is that the third width W3 of the conductive region 20A is smaller than the second width W2 of the gate 40 by enhancing the hydrogen diffusion effect in the hydrogen source layer 60. The purpose of shortening the channel width of the oxide semiconductor thin film transistor 103 is further. The above-mentioned ways to enhance the hydrogen diffusion effect in the hydrogen source layer 60 may include increasing the hydrogen concentration in the strong hydrogen source layer 60 (for example, additional hydrogen is introduced when the hydrogen source layer 60 is deposited), applying an auxiliary treatment such as heat treatment or other suitable A way to enhance the hydrogen diffusion effect.

Please refer to Figure 12 and Figure 13. FIG. 12 and FIG. 13 are schematic diagrams showing a method for manufacturing an oxide semiconductor thin film transistor according to a fourth embodiment of the present invention. The difference from the first embodiment is that, as shown in FIG. 12, the hydrogen diffusion control layer 50 of this embodiment can completely cover the patterned oxide semiconductor layer 20, the patterned gate dielectric layer 30, and the gate 40. Therefore, the hydrogen diffusion control layer 50 covers both ends of the patterned oxide semiconductor layer 20 in the horizontal direction H, and the hydrogen source layer 60 does not directly contact the patterned oxide semiconductor layer 20 and the subsequent doped region 20B. In this way, it can be avoided that when the hydrogen diffusion effect in the hydrogen source layer 60 is too strong, the range of the corresponding doped region 20B is too large, and thus the electrical condition of the conductive region 20A is affected. As shown in FIG. 13, when the oxide semiconductor thin film transistor 104 of this embodiment is formed, since the doped region 20B is covered by the hydrogen diffusion control layer 50 and the hydrogen source layer 60, the contact opening V needs to penetrate hydrogen. The source layer 60 and the hydrogen diffusion control layer 50 partially expose the two doped regions 20B, and the source 70S and the drain 70D can be electrically connected through the contact opening V and the doped region 20B. In addition, the hydrogen diffusion control layer 50 of this embodiment further has an extension portion 50A, and the extension portion 50A covers both ends of the patterned oxide semiconductor layer 20 in the horizontal direction H.

Please refer to Figure 14 and please also refer to Figure 13. FIG. 14 is a graph showing the relationship between the drain current and the gate voltage of the oxide semiconductor thin film transistor 104 in this embodiment under the design condition that the channel width and the channel length are both 5 μm. As shown in FIG. 14 and FIG. 13, the oxide semiconductor thin film transistor 104 of this embodiment can perform well under the condition that the ratio of the channel width to the channel length is relatively high when the hydrogen diffusion control layer 50 is provided. The characteristics of the thin film transistor, and its carrier mobility (mobility) can reach about 13 cm ² / VS. Although the carrier mobility of the oxide semiconductor thin film transistor 104 of this embodiment is lower than that of the first embodiment described above, the hydrogen source layer 60 is caused by the hydrogen diffusion control layer 50 of this embodiment covering the patterned oxide semiconductor layer 20 The patterned oxide semiconductor layer 20 is not directly contacted, so the accuracy of controlling the hydrogen concentration of the hydrogen source layer 60 can be relatively loose, which is beneficial to the process. In contrast, as shown in FIGS. 8 and 9, since the hydrogen diffusion control layer is not provided, the oxide semiconductor thin film transistor of this comparative example will be biased to conduct under the condition that the channel width to channel length ratio is relatively high. Does not have thin film transistor characteristics.

In summary, the oxide semiconductor thin film transistor system of the present invention uses a hydrogen diffusion control layer to control the diffusion of hydrogen in the hydrogen source layer to the patterned oxide semiconductor layer, and at the same time to prevent hydrogen in the hydrogen source layer from passing through the pattern The gate dielectric layer is diffused and diffused into the conductive region in the patterned gate dielectric layer to affect the electrical condition of the conductive region. Therefore, even if the gate and patterned gate dielectric in the oxide semiconductor thin film transistor need to be reduced in order to meet the short channel design, the formation range of the doped region can be controlled by the hydrogen diffusion control layer and the conductive region can be avoided. The electrical properties of the semiconductor are affected, so the purpose of improving the device characteristics of the oxide semiconductor thin film transistor can be achieved. In addition, in the method for manufacturing an oxide semiconductor thin film transistor of the present invention, the same mask can be used to define the hydrogen diffusion control layer, the pattern of the gate dielectric layer and the gate pattern, thereby achieving the purpose of reducing the manufacturing cost. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the present invention.

10‧‧‧ substrate
20‧‧‧ patterned oxide semiconductor layer
20A‧‧‧ Conduction area
20B‧‧‧ doped region
30‧‧‧ patterned gate dielectric
30F‧‧‧ Junction
30S‧‧‧side
40‧‧‧Gate
50‧‧‧ Hydrogen diffusion control layer
50A‧‧‧ Extension
60‧‧‧ Hydrogen source layer
70D‧‧‧ Drain
70S‧‧‧Source
101-104‧‧‧‧oxide semiconductor thin film transistor
200‧‧‧ oxide semiconductor thin film transistor
H‧‧‧Horizontal
S‧‧‧Top
V‧‧‧ contact opening
W1‧‧‧first width
W2‧‧‧Second width
W3‧‧‧ Third width
Z‧‧‧ vertical

FIG. 1 is a diagram showing a relationship between a drain current and a gate voltage of an oxide semiconductor thin film transistor of the conventional technology. FIG. 2 to FIG. 6 are schematic diagrams illustrating a method for manufacturing an oxide semiconductor thin film transistor according to a first embodiment of the present invention. FIG. 7 is a diagram showing the relationship between the drain current and the gate voltage of the oxide semiconductor thin film transistor according to the first embodiment of the present invention. FIG. 8 is a schematic diagram of an oxide semiconductor thin film transistor of a comparative example. FIG. 9 shows the relationship between the drain current and the gate voltage of the oxide semiconductor thin film transistor of the comparative example. FIG. 10 is a schematic diagram showing an oxide semiconductor thin film transistor according to a second embodiment of the present invention. FIG. 11 is a schematic diagram of an oxide semiconductor thin film transistor according to a third embodiment of the present invention. FIG. 12 and FIG. 13 are schematic diagrams showing a method for manufacturing an oxide semiconductor thin film transistor according to a fourth embodiment of the present invention. FIG. 14 is a diagram showing a relationship between a drain current and a gate voltage of an oxide semiconductor thin film transistor according to a fourth embodiment of the present invention.

10‧‧‧ substrate

20‧‧‧ patterned oxide semiconductor layer

20A‧‧‧ Conduction area

20B‧‧‧ doped region

30‧‧‧ patterned gate dielectric

30F‧‧‧ Junction

30S‧‧‧side

40‧‧‧Gate

50‧‧‧ Hydrogen diffusion control layer

60‧‧‧ Hydrogen source layer

70D‧‧‧ Drain

70S‧‧‧Source

101‧‧‧oxide semiconductor thin film transistor

H‧‧‧Horizontal

S‧‧‧Top

V‧‧‧ contact opening

W1‧‧‧first width

W2‧‧‧Second width

W3‧‧‧ Third width

Z‧‧‧ vertical

Claims (17)

An oxide semiconductor thin film transistor includes: a substrate; a patterned oxide semiconductor layer disposed on the substrate; a patterned gate dielectric layer disposed on the patterned oxide semiconductor layer; a gate Is disposed on the patterned gate dielectric layer; a hydrogen diffusion control layer is disposed on the gate and the patterned oxide semiconductor layer, wherein the hydrogen diffusion control layer covers the gate and the patterning A gate dielectric layer; a hydrogen source layer disposed on the hydrogen diffusion control layer and the patterned oxide semiconductor layer, wherein a hydrogen content of the hydrogen source layer is greater than a hydrogen content of the hydrogen diffusion control layer; and A source and a drain are disposed on the hydrogen source layer, wherein the source and the drain are in contact with and electrically connected to the patterned oxide semiconductor layer. The oxide semiconductor thin film transistor according to claim 1, wherein the hydrogen diffusion control layer directly contacts the patterned oxide semiconductor layer, and the hydrogen source layer directly contacts the hydrogen diffusion control layer. The oxide semiconductor thin film transistor according to claim 1, wherein the hydrogen source layer directly contacts the patterned oxide semiconductor layer. The oxide semiconductor thin film transistor according to claim 1, wherein the hydrogen diffusion control layer covers the patterned gate dielectric layer and the gate, and the hydrogen diffusion control layer is along a top surface of one of the gates. One side of the gate extends toward the patterned oxide semiconductor layer and does not extend beyond a projection range where the hydrogen diffusion control layer is located on the top surface and is perpendicularly projected onto the substrate. The oxide semiconductor thin film transistor according to claim 4, wherein the hydrogen diffusion control layer further has an extension in a horizontal direction, and the extension covers both ends of the patterned oxide semiconductor layer in the horizontal direction. The oxide semiconductor thin film transistor according to claim 1, further comprising a plurality of contact openings penetrating the hydrogen source layer, wherein the source and the drain are connected to the patterned oxide semiconductor through the contact openings. The layers are in contact and electrically connected. The oxide semiconductor thin film transistor according to claim 6, wherein the contact openings further penetrate the hydrogen diffusion control layer. The oxide semiconductor thin film transistor according to claim 1, wherein the hydrogen diffusion control layer includes a metal oxide, silicon nitride, silicon oxide, or silicon oxynitride. The oxide semiconductor thin film transistor according to claim 1, wherein a thickness of the hydrogen diffusion control layer is between 100 angstrom and 500 angstrom. The oxide semiconductor thin film transistor according to claim 1, wherein the hydrogen source layer includes silicon nitride, silicon oxide, or silicon oxynitride. The oxide semiconductor thin film transistor according to claim 1, wherein the patterned oxide semiconductor layer includes indium gallium zinc oxide, zinc oxide, indium zinc oxide, or indium gallium oxide. The oxide semiconductor thin film transistor according to claim 1, wherein the hydrogen content of the hydrogen source layer is between 15 x 10 ²⁰ atoms / cm ³ and 27 x 10 ²² atoms / cm ³ . A method for manufacturing an oxide semiconductor thin film transistor includes: forming a patterned oxide semiconductor layer on a substrate; forming a patterned gate dielectric layer on the patterned oxide semiconductor layer; and forming a patterned gate on the patterned oxide semiconductor layer A gate is formed on the gate dielectric layer; a hydrogen diffusion control layer is formed on the gate and the patterned oxide semiconductor layer, wherein the hydrogen diffusion control layer covers the gate and the patterned gate dielectric Forming a hydrogen source layer on the hydrogen diffusion control layer and the patterned oxide semiconductor layer, wherein the hydrogen content of the hydrogen source layer is greater than the hydrogen content of the hydrogen diffusion control layer; and on the hydrogen source layer A source and a drain are formed, wherein the source and the drain are in contact with and electrically connected to the patterned oxide semiconductor layer. According to the manufacturing method of the oxide semiconductor thin film transistor according to claim 13, the hydrogen diffusion control layer covers the patterned gate dielectric layer and the gate, and the hydrogen diffusion control layer is from a top surface of the gate. Extending along one side of the gate toward the patterned oxide semiconductor layer, the extension does not exceed the projection range where the hydrogen diffusion control layer is located on the top surface and is perpendicularly projected onto the substrate. The method for manufacturing an oxide semiconductor thin film transistor according to claim 14, wherein the hydrogen diffusion control layer, the patterned gate dielectric layer, and the gate system use a same mask to define a pattern. The method for manufacturing an oxide semiconductor thin film transistor according to claim 13, wherein the hydrogen The diffusion control layer includes a metal oxide, silicon nitride, silicon oxide, or silicon oxynitride. The method for manufacturing an oxide semiconductor thin film transistor according to claim 13, wherein the hydrogen content of the hydrogen source layer is between 15 x 10 ²⁰ atoms / cm ³ and 27 x 10 ²² atoms / cm ³ .