TW201508841A - Method for improving the electrical conductivity of metal oxide semiconductor layers - Google Patents

Abstract

The present disclosure provides a method for improving the electrical conductivity of a metal oxide semiconductor layer at predetermined locations. The method comprises: providing on a substrate a metal oxide semiconductor layer; providing by means of Atomic Layer Deposition a metal oxide layer on top of the metal oxide semiconductor layer, wherein the metal oxide layer is in physical contact with the metal oxide semiconductor layer at the predetermined locations. It was surprisingly found that this method results in an increased electrical conductivity of the metal oxide semiconductor layer at the predetermined locations. The method of the present disclosure can advantageously be used in a fabrication process for self-aligned top-gate metal oxide semiconductor thin film transistors, for improving the electrical conductivity in the source and drain regions.

Description

Method for improving the conductivity of a MOS layer

The present disclosure is directed to a method of locally improving the conductivity of a MOS layer.

The present disclosure further relates to a method of fabricating a metal oxide based thin film transistor.

Amorphous GaN thin film transistor (TFT) (for example, Amorphous Indium-Gallium-Zinc Oxide (a-IGZO) thin film transistor) has been studied as a flat panel. Potential replacements for germanium-based TFTs in display applications because of their higher mobility and greater area uniformity.

A conventional amorphous germanium TFT which is regarded as a switching device in an active matrix liquid crystal display has an advantage of having a large area uniformity. However, their field effect mobility coefficients (<1 cm ² /Vs) are too low to drive an Organic Light-Emitting Diode (OLED).

Conversely, a high mobility factor is currently used as the switching device in an AMOLED display (> 50cm ² / Vs) of the crystalline p-Si TFT have the threshold voltage of the field effect movement of non-uniformity coefficient AMOLED display a large size Disadvantages.

Known bottom gate TFT structures and top gate TFT structures are not suitable for use in high resolution displays because of their high parasitic capacitance and poor shrinkability. (scalability) (large coverage). The high parasitic capacitance in such TFT structures is related to the presence of overlap between the source and the gate and/or between the drain and the gate. This overlap is due to the use of a transistor gate length greater than the channel length to avoid or limit the negative consequences of alignment misalignment between the gate and the source and drain.

Therefore, a method for fabricating a self-aligned top gate oxide TFT is currently being developed in which a source and a drain are aligned with a gate, and wherein the TFTs have good electrical efficiency and high stability. Several self-aligned top gate structures having an active layer of an oxide semiconductor have been described in which the conductivity of the MOS is locally increased in the source and drain regions.

Several methods have been proposed to (locally) increase the conductivity of oxy-semiconductor materials. One of these methods consists of doping by ion implantation of impurities such as boron, phosphorus, or arsenic. However, ion implantation on a flexible substrate can be difficult because an annealing step is required to perform dopant activation, which is typically performed at temperatures above 450 °C.

Another method consists of performing argon plasma treatment, hydrogen plasma treatment, or NH ₃ plasma treatment. However, it has been observed that the stability of the source and drain regions of such plasma treatment is poor, and the effects of plasma treatment may disappear as a result of further processing steps required to integrate the OLED.

A method for fabricating a self-aligned MOS film transistor is described in US 2012/0001167, wherein an alternative method is used to locally increase the conductivity of the MOS layer. After depositing a MOS layer, a gate insulator and a gate electrode, a metal film made of a metal (for example, Ti, Al, or In) having a thickness of 10 nm or less is provided. . Then, heat treatment is carried out in an oxygen-containing environment, for example, at a temperature of 300 ° C. At the office. Due to the thermal shutdown, the metal film is oxidized. In the oxidation reaction of the metal film, a portion of the oxygen contained in a source region and a drain region of the MOS layer is transferred to the metal film. Because of the decrease in oxygen concentration in the source region and the drain region, it results in the formation of a low resistance region in an upper portion of the MOS layer. The thickness of the metal film is preferably 10 nm or less, so that the metal film can be completely oxidized in the oxygen-containing environment during the heat treatment. In this manner, an etching step may not be required to remove the metal that is not oxidized.

The method described in US 2012/0001167 requires a temperature of at least 200 ° C, For example, the size of 300 ° C. Therefore, this method is not compatible with certain low cost flexible substrates such as, for example, PET (polyethylene terephthalate), PEN (polyethylene naphthalate), and PC (poly) Carbonate) and may require the use of higher quality plastic sheets with high thermal stability and/or chemical stability, for example, PI (polyimide), PES (polyether oxime), or PEEK (polyether) Ether ketone). The method also requires good and precise control of the thickness of the metal layer in order to avoid the need to perform an etching step to remove the unoxidized metal.

It is an object of the present disclosure to provide a method of locally improving the electrical conductivity of a MOS layer, wherein the high conductivity has good temperature stability, and wherein the method can be implemented at a temperature lower than 200 ° C .

A further object of the present disclosure is to provide a good source contact and drain contact, good field effect shift coefficient (for example, above 10 cm ² /Vs), good thermal stability, and good bias stability. A method of self-aligning a top gate MOS thin film transistor, wherein the transistors can be fabricated at temperatures below 200 °C.

The present disclosure relates to a guide for improving a MOS layer at a predetermined position Electrical method. The method includes: providing a MOS layer on a substrate; and providing a gold oxide layer on top of the MOS layer by Atomic Layer Deposition (ALD), wherein the MOS layer is The MOS layer is physically contacted (ie, by a direct physical interface).

It has been surprisingly discovered that depositing the gold oxide layer by ALD results in the gold oxide semiconductor layer having high conductivity at a location where the gold oxide layer is in direct physical contact with the gold oxide semiconductor layer.

In an embodiment of the present disclosure, for example, the thickness of the MOS layer may be in a range between 10 nm and 100 nm, or in a range between 11 nm and 99 nm, the disclosure is not limited this.

In an embodiment of the present disclosure, providing (for example, depositing) a gold oxide layer by atomic layer deposition may be performed at a temperature in a range between 150 ° C and 200 ° C.

In an embodiment of the present disclosure, the method may further include: providing an alkali metal (for example, Li, Na, K, Rb, Cs, or a reduction layer of any one or any combination of Fr or alkaline earth metals (for example, any one or any combination of Be, Mg, Ca, Sr, Ba, or Ra) Setting a physical contact with the MOS layer; inducing a chemical reduction reaction between the reducing layer and the MOS layer, for example, by a temperature in a range between 20 ° C and 200 ° C An annealing step is performed; and the reducing layer and the reaction by-products in the reduction reaction are removed, for example, by rinsing in water or alcohol.

In an embodiment of the present disclosure, for example, the MOS layer may include gallium indium zinc oxide (GIZO or IGZO); and, for example, the gold oxide layer may include Al ₂ O ₃ . However, the disclosure is not limited thereto. Other MOS semiconductors can also be used, such as, for example, ZnO, ZnSnO, InO, InZnSnO, LaInZnO, GaInO, HfInZnO, MgZnO, LaInZnO, TiO, TiInSnO, ScInZnO, and SiInZnO and ZrInZnO, or ZrZnSnO. Other gold oxide layers can also be used, such as, for example, HfO ₂ , Ta ₂ O ₅ , ZrO ₂ , or Ga ₂ O ₃ .

In an embodiment of the present disclosure in which the gold oxide layer is an Al ₂ O ₃ layer, the gold oxide layer may be deposited as a precursor of trimethylaluminum and water (H ₂ O), or, for example, Triethylaluminum and water are used as precursors or are deposited with triisobutylaluminum and water as precursors.

In embodiments of the present disclosure, when forming the gold oxide layer, different precursors may be mixed or different precursors may be used alternately.

The present disclosure is further directed to a fabrication of a self-aligned (meaning that the source and drain will self-align the gate) a top gate (the gate is provided at the top of the MOS layer) of a MOS film transistor method. The method includes: providing a MOS layer on a substrate; depositing a gate dielectric layer on top of the MOS layer; depositing a gate electrode layer on the gate dielectric layer; patterning the gate a pole electrode layer and the gate insulating layer for forming a gate electrode and a gate insulator, thereby defining a channel region in the MOS layer; patterning the MOS layer to thereby form the gold oxide Defining a source region and a drain region in the semiconductor layer; and depositing a gold oxide layer by atomic layer deposition, for example, at least in the source region and the drain region, thereby at the source The direct contact of the gold oxide layer in the polar region with the gold oxide layer (that is, the interface through a direct physical interface) increases the conductivity of the gold oxide semiconductor layer. .

The method may further include: providing a dielectric layer to the top of the gold oxide layer; forming a via hole penetrating the dielectric layer and the gold oxide layer; and filling the via holes with a metal to form a source The contact is connected to a bungee.

In an embodiment of the present disclosure, the method may be in the MOS layer Further providing the gold oxide layer before the top portion further comprises: providing an alkali metal (for example, any one or any combination of Li, Na, K, Rb, Cs, or Fr) or an alkaline earth metal (for example, a reducing layer of any one or any combination of Be, Mg, Ca, Sr, Ba, or Ra) physically contacting the oxynitride layer at the predetermined positions; at the reducing layer and the gold Inducing a chemical reduction reaction between the oxygen semiconductor layers, for example, by performing an annealing step at a temperature in a range between 20 ° C and 200 ° C; and removing the reduced layer and the reaction pair in the reduction reaction The product, for example, is rinsed in water or alcohol.

An advantage of the method of the present disclosure is that it can be below 200 ° C or below A temperature of 199 ° C, or less than 190 ° C, or less than 180 ° C, or less than 170 ° C, or less than 160 ° C is carried out. Therefore, the methods are compatible with low cost flexible substrates such as, for example, PET (polyethylene terephthalate), PEN (polyethylene naphthalate), and PC (polycarbonate). ).

An advantage of the method of the present disclosure is that it is relatively unnecessary or not necessary to precisely control the layer thickness as is the case with certain prior art approaches.

An advantage of the method of the present disclosure is that depositing the gold oxide layer not only results in improved conductivity of the underlying gold oxide semiconductor layer; in addition, depositing the gold oxide layer results in passivation and encapsulation of the underlying gold oxide semiconductor layer ( For example, the MOS layer will be completely covered or encapsulated, that is, no longer exposed to the environment).

An advantage of the methods of the present disclosure is that they result in good stability of the high electrical conductivity of the MOS layer; this high conductivity does not change over time.

An advantage of the method of the present disclosure is that they allow for good bias stability Self-aligned top gate MOS thin film transistor that is qualitative and has good thermal stability.

The specific objects and advantages of various innovative aspects of the present invention have been described hereinabove. It should be understood, of course, that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the present disclosure. Thus, for example, those skilled in the art will appreciate that the present disclosure may achieve or optimize one of the advantages or a group of advantages as taught herein, but does not necessarily achieve other possibilities that may be as taught or suggested herein. The purpose or advantage of the way to achieve or achieve. Further, it should be understood that the summary is merely exemplary and not intended to limit the scope of the disclosure. With reference to the detailed description below, it is best to understand the disclosure (organization and its method of operation) and its features and advantages when reading with the accompanying drawings.

10‧‧‧Substrate

11‧‧‧Active layer

12‧‧‧Gold-oxide semiconductor layer

13‧‧‧ gate dielectric layer

14‧‧‧ gate electrode layer

15‧‧‧Gold oxygen layer

16‧‧‧Dielectric layer

21‧‧‧Source electrode

22‧‧‧汲electrode

101‧‧‧矽 substrate

102‧‧‧ dielectric layer

110‧‧‧Channel area

111‧‧‧ source area

112‧‧‧Bungee Area

131‧‧‧gate insulator

141‧‧‧gate electrode

1(a) to 1(f) show a method of fabricating a gold oxide semiconductor thin film transistor according to a method of the present disclosure.

2 is a conversion characteristic curve (I _DS -V _GS ) of an a-IGZO thin film transistor fabricated according to a method of the present disclosure.

Figure 3 shows an output characteristic curve (I _DS - V _DS ) of an a-IGZO thin film transistor fabricated according to a method of the present disclosure.

4 is a conversion characteristic curve (I _DS ) of a-IGZO TFT (W/L=30/10 μm/μm) produced according to a method of the present disclosure at different bias stress times. -V _GS ): Figure 4(a) is the negative bias stress of -1 MV/cm (V _GS = -12 V and V _DS =0 V); Figure 4 (b) is +1 MV/cm (V _GS = +12 V and Positive bias stress of V _DS = +12 V).

Figure 5 is a graph of the _VTH shift of an a-IGZO TFT fabricated in accordance with a method of the present disclosure as a function of stress time in the forward and negative directions.

Figure 6 shows the initial conversion characteristic curve (open circles) of an a-IGZO TFT (W/L = 30/10 μm/μm) and the conversion characteristic curve after a 2 hour annealing at 150 ° C in nitrogen (solid square) ).

Any component symbols in the scope of the patent application are not considered to be limited to the scope of the present disclosure.

In the different figures, the same element symbols indicate the same or similar elements.

In the following detailed description, numerous specific details are set forth However, it should be understood that the present disclosure may be practiced without such specific details. The methods, procedures, and techniques that are well known will not be described in detail in other examples, so as not to obscure the present disclosure.

The disclosure is described with respect to particular embodiments and with reference to specific drawings; however, the disclosure is not limited thereto. The drawings contained and illustrated herein are illustrative and not limiting of the scope of the disclosure. It should also be noted that in the drawings, the size of some of the elements may be exaggerated for the purpose of explanation and are not drawn to scale.

Furthermore, the first, second, third, and similar words in the description are used to distinguish the same elements and do not necessarily indicate the order of time or space according to the level or any other manner. It will be appreciated that the terms used may be used interchangeably, where appropriate, and that the embodiments of the disclosure described herein can operate in other sequences than those described or illustrated herein.

Further, the top, bottom, over, under, and similar words in the description are for illustrative purposes and do not necessarily indicate relative positions. It will be appreciated that the terms used may be used interchangeably where appropriate and that embodiments of the disclosure described herein can be used herein. Operates in other orientations than those described or illustrated.

The present disclosure provides a method of improving (improving) the conductivity of a MOS layer, for example, locally improving the layers at a source contact and a drain contact of a MOS film transistor Electrical conductivity. The increase in conductivity can be significant, for example, by at least one size rating, for example, up to three size classes.

According to an aspect of the present disclosure, there is provided a method of improving conductivity of a MOS layer at a predetermined position, wherein the method comprises: depositing a gold oxide layer at the predetermined locations by atomic layer deposition At the top end of the MOS layer and physically contacting (and thus interposing) the MOS layer.

It has been surprisingly discovered that depositing the gold oxide layer by ALD results in the gold oxide semiconductor layer having high conductivity at a location where the gold oxide layer is in direct physical contact with the gold oxide semiconductor layer.

For example, the gold oxide layer may include Al ₂ O ₃ , HfO ₂ , Ta ₂ O ₅ , ZrO ₂ , or Ga ₂ O ₃ , but the invention is not limited thereto.

In an embodiment of the present disclosure, for example, the gold oxide layer may be an Al ₂ O ₃ layer. For example, it can be deposited as a precursor of trimethylaluminum (TMA, Al(CH ₃ ) ₃ ) and water (H ₂ O). However, other precursors may also be used, such as, for example, triethylaluminum and water as precursors or triisobutylaluminum and water as precursors to form an Al ₂ O ₃ layer.

In an embodiment of the present disclosure, for example, the gold oxide layer may be a Ga ₂ O ₃ layer. For example, precursors useful in this layer include triethylgallium and water, trimethylgallium and water, triisopropylgallium and water, or tri-tertiary butylgallium and water, but the present invention Not limited to this.

In embodiments of the present disclosure, when forming the gold oxide layer, different precursors may be mixed or different precursors may be used alternately.

For example, the thickness of the gold oxide layer may be in the range between 10 nm and 100 nm, and for example, it may be deposited at a temperature in the range between 150 ° C and 200 ° C, for example , between 150 ° C and 170 ° C, but the invention is not limited thereto.

The method of the present disclosure can be advantageously used in the fabrication of a thin film transistor having a MOS active layer to locally increase the conductivity at a predetermined position corresponding to the source region and the drain region, thereby The charge emission from the source contacts and the drain contacts is improved. This method can be advantageously used in the fabrication of self-aligned top gate thin film transistors.

The method can also be used in the fabrication of other MOS-based devices (for example, diodes or transistor-diodes) to improve charge emission from the contacts.

For example, the MOS layer can include gallium indium zinc oxide (GIZO or IGZO), or a semiconductor based on other metal oxides, for example, the following composition (which is not ideal) Ratio indication): ZnO, ZnSnO, InO, InZnSnO, LaInZnO, GaInO, HfInZnO, MgZnO, LaInZnO, TiO, TiInSnO, ScInZnO, SiInZnO, and ZrInZnO, ZrZnSnO. However, the present disclosure is not limited thereto, and the method can be applied to other suitable gold oxide semiconductors known to those skilled in the art. A semiconductor layer having a typical thickness between 5 nm and 50 nm, or between 6 nm and 49 nm, can be provided by a number of methods such as, for example, sputtering, thermal evaporation, pulsed laser deposition. And spin casting, inkjet printing, or drop casting of the precursor solution.

Further described herein is a method for fabricating a self-aligned top gate MOS thin film transistor, wherein the method of the present disclosure is used to locally improve the conductivity of the MOS layer in the source and drain regions. . In the structure of the device, the ALD metal oxide layer The conductivity of the lower source region and the drain region is changed, and it also has a function of passivation and encapsulation layer.

An exemplary process flow for fabricating a MOS thin film transistor in accordance with the present disclosure is schematically illustrated in FIGS. 1(a) through 1(f).

In the first step shown in Fig. 1(a), a oxynitride layer 12 (e.g., a GIZO layer) is provided on a substrate 10, for example, by sputtering from a precursor solution. Plating, laser ablation, or spin coating. In the example shown in FIG. 1(a), the substrate 10 includes a germanium substrate 101 and a dielectric layer 102 (for example, a hafnium oxide layer); however, other suitable substrates may be used. For example, the thickness of the GIZO layer 12 is about 10 nm or about 15 nm to 20 nm, for example, between 10 nm and 20 nm, or between 11 nm and 19 nm; however, other suitable thicknesses can also be used. .

Next, as shown in FIG. 1(b), a gate dielectric layer 13 (for example, a hafnium oxide layer) is deposited on top of the MOS layer 12, for example, by electricity. Slurry enhanced chemical vapor deposition. Thereafter, a gate electrode layer 14 (for example, a Mo layer) is deposited on the top end of the gate dielectric layer 13 (Fig. 1(b)).

The gate electrode layer 14 and the gate insulating layer 13 are then patterned, for example, by dry etching to form a gate electrode 141 and a gate insulator 131, as shown in FIG. 1(c). .

Next, the MOS layer 12 is patterned to define the active layer 11 of the thin film transistor (Fig. 1 (d)). For example, the MOS layer can be patterned by wet etching, for example, using buffered HF or oxalic acid. The advantage of using oxalic acid in active layer patterning is that it has good selectivity for the underlying layer. The patterned gate electrode 141 defines a channel region 110, a source region 111, and a drain region 112 among the active layers 11, as shown in FIG. 1(d). The outline is shown. The source and drain regions are directly adjacent to the channel region and self-aligned.

In the example shown in FIG. 1, the MOS layer is patterned after the gate electrode layer and the gate dielectric layer are patterned; however, the disclosure is not limited thereto. For example, the MOS layer can also be patterned prior to the gate fabrication process or patterned at a later stage after the gate fabrication process.

Next, a gold oxide layer 15 (for example, an Al ₂ O ₃ layer) will be formed by ALD (for example, using trimethylaluminum (TMA, Al(CH ₃ ) ₃ )) and water (H ₂ O). ) is deposited as a precursor (as shown in Figure 1(e)). A surprising finding is that depositing this layer results in a high conductivity of the MOS layer at the location where the Al ₂ O ₃ layer 15 is in direct physical contact with the MOS layer 11. Therefore, enhanced conductivity is achieved in the source region 111 and the drain region 112 of the MOS layer 11, at least in an upper portion of the MOS layer. It is believed that there is a doping effect or a reduction reaction due to the interaction between the ALD precursors and the surface of the oxynitride layer. For example, TMA and H ₂ O, which are ALD precursors in Al ₂ O ₃ , can react with the IGZO surface. For example, if H ₂ O, O ₂ , O ₃ are present in the reaction, a doping effect will occur. The upper portion preferably has a depth/thickness of from several nanometers up to 10 or about 10 nm. If the ALD gold oxide is combined with additional doping (for example, using Ca, see above), then the enhanced conductivity is expected to extend deeper into the MOS layer, for example, Up to tens of nm, for example, up to 20 nm or up to 30 nm.

Next, a dielectric layer 16 (for example, a tantalum nitride layer) is provided on the top end of the gold oxide layer 15 and then formed at a position where the source contact and the drain contact are to be formed. A hole penetrates through the dielectric layer 16 and the underlying gold oxide layer 15. The vias are then filled with a suitable metal (e.g., Mo) for forming a source electrode 21 and a drain electrode 22. The resulting structure is schematically shown in Figure 1 (f).

2 is a conversion characteristic curve (I _DS -V _GS ) of an a-IGZO thin film transistor fabricated according to a method of the present disclosure as described above, having an ALD Al ₂ O ₃ gold oxide layer 15. Figure 3 shows the output characteristic curve (I _DS - V _DS ) of this transistor.

The a-IGZO TFT exhibits high thermal stability and good electrical performance. From the figure, a field effect shift coefficient of 14.82 cm ² /VS, a threshold voltage of 3.6 V, a subcritical swing of 0.42 V/dec, and a turn-on/non-conduction current ratio of about 10 ⁸ are observed.

The effect of bias stress on the electrical performance of a TFT has been studied in the present invention. Corresponding to a positive and negative / cm gate electric field is applied for up to ¹⁰⁴ seconds of stress at the time in a dark room temperature to +/- 1.0MV. In the case of a positive gate bias stress, which corresponds to a full turn-on condition (V _DS = 12 V and V _GS = 12 V), a threshold voltage shift of 0.8 V is observed. If it is a negative bias stress (V _DS =0V and V _GS = -12V), a critical voltage offset of 1.0V is observed. Figure 4(a) and Figure 4(b) show that both the negative gate bias stress (Figure 4(a)) and the positive gate bias stress (Figure 4(b)) are in different bias stress times below. Conversion characteristic curve: 0s (that is, no bias stress), 100s, 300s, 1000s, 3000s, and 10000s. Figure 5 shows the _VTH offset as a function of stress time in the positive and negative directions. The conclusions obtained from these results are that the stability under various stress conditions is very good.

Figure 6 shows the initial conversion characteristic curve (open circles) of an a-IGZO TFT (W/L = 30/10 μm/μm) and the conversion characteristic curve after a 2 hour annealing at 150 ° C in nitrogen (solid square) ). It can be concluded from these results that the effect of the annealing step on the characteristic curve of the device is negligible, which indicates good thermal stability.

The foregoing description details specific embodiments of the present disclosure; however, it should be understood that the present disclosure may be in many ways, no matter how detailed the preceding text is. Implemented. It should be noted that the use of specific terms when describing specific features and aspects of the present disclosure should not be considered as a metaphor. The term is redefined herein to include only the features associated with the term in this disclosure or Specific characteristics of the point of view.

Although the above detailed description has shown, illustrated, and pointed out the novel features of the aspects of the present invention in various embodiments, it should be understood that those skilled in the art can The form and details are subject to various omissions, substitutions, and changes,

10‧‧‧Substrate

11‧‧‧Active layer

15‧‧‧Gold oxygen layer

16‧‧‧Dielectric layer

21‧‧‧Source electrode

22‧‧‧汲electrode

101‧‧‧矽 substrate

102‧‧‧ dielectric layer

131‧‧‧gate insulator

141‧‧‧gate electrode

Claims (12)

A method of improving conductivity of a MOS layer at a predetermined position, comprising: providing a MOS layer (12) on a substrate (10); and depositing an OX layer on the MOS layer by an atomic layer The top end provides a gold oxide layer (15), wherein the gold oxide layer physically contacts the gold oxide semiconductor layer at the predetermined positions. The method of claim 1, wherein the thickness of the gold oxide layer (15) is in a range between 10 nm and 100 nm. The method of claim 1, wherein the gold oxide layer (15) is provided at a temperature in a range between 150 ° C and 200 ° C. The method of claim 1, wherein the oxynitride layer (12) is a gallium indium zinc oxide layer. The method of claim 1, wherein the gold oxide layer (15) is an Al ₂ O ₃ layer. The method of claim 5, wherein the Al ₂ O ₃ layer is deposited using trimethylaluminum and water (H ₂ O) as a reagent. The method of claim 1, further comprising: providing a gold oxide layer at the top end of the oxynitride layer further comprising: providing a reducing layer comprising an alkali metal or an alkaline earth metal at the presets Physically contacting the gold-oxygen semiconductor layer at a position; inducing a chemical reduction reaction between the reduced layer and the gold-oxygen semiconductor layer; and removing the reduction layer and reaction by-products in the reduction reaction. A method for fabricating a self-aligned top gate MOS thin film transistor according to the method of claim 1 of the patent application, the method comprising: Providing a MOS layer (12) on a substrate (10); depositing a gate dielectric layer (13) on top of the MOS layer (12); depositing a gate electrode layer (14) thereon a gate dielectric layer (13); the gate electrode layer (14) and the gate insulating layer (13) are patterned to form a gate electrode (141) and a gate insulator (131); The MOS layer (12) is defined to define a source region (111), a channel region (110), and a drain region (112) of the thin film transistor; and depositing a layer by atomic layer deposition a gold oxide layer (15), thereby enhancing the MOS layer in the source region (111) and where the gold oxide layer directly contacts the MOS layer in the drain region (112) Electrical conductivity. The method of claim 8 further comprising: providing a dielectric layer (16) to the top end of the gold oxide layer (15); forming a via hole through the dielectric layer (16) and the gold oxide layer ( 15); and filling the via holes with a metal to form a source electrode (21) and a drain electrode (22). The method of claim 8 wherein the method is carried out at a temperature below 200 °C. The method of claim 8 wherein the substrate is a low cost flexible substrate. The method of claim 8, wherein the substrate comprises PET (polyethylene terephthalate), PEN (polyethylene naphthalate), or PC (polycarbonate).