JP2014072408A - Field effect transistor, semiconductor device equipped with the same and field effect transistor manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field effect transistor which can inhibit heat generation even when used as a driver circuit and the like which places a high burden on a semiconductor layer.SOLUTION: In a field effect transistor which has at least a semiconductor layer, a source electrode, a drain electrode, a gate insulation film and a gate electrode on a substrate in which the source electrode and the drain electrode are connected via the semiconductor layer and which has a gate insulation film between the gate electrode and the semiconductor layer, an oxidation reduction potential at 25°C of the source electrode and the drain electrode at parts which contact at least the semiconductor layer is not less than -1.7 V and not more than 0.4 V with respect to a normal electrode potential, and the source electrode and the drain electrode have offset regions each of which is within a region of not less then 0.1 μm and not more than 5 μm.

Description

  The present invention relates to a field effect transistor, a semiconductor device including the same, and a method for manufacturing the field effect transistor.

  In recent years, a technique for driving a liquid crystal or an organic EL using an oxide semiconductor has been widespread. In addition, oxide semiconductors use high mobility to control not only panel display but also video signals (gate drivers, demultiplexers, signal drivers), as with low-temperature polysilicon (LTPS), Alternatively, it can be applied to a driver such as a touch sensor to reduce the weight of the panel and simplify the production process.

By the way, when an oxide semiconductor is used for the driver as described above, it is operated at a faster frequency and drive voltage, so that a portion where the electric field is concentrated may generate heat and cause deterioration. Heat generation causes a decrease in On current, leakage due to an increase in Off current, and the like. In particular, oxide semiconductors are often used on lightweight resin substrates and flexible substrates by utilizing low-temperature processes, and such a problem of heat generation appears more conspicuously than on a glass substrate.
Also, when used for driving organic EL elements, the phenomenon of heat generation causes uneven brightness.

As a method of preventing such a phenomenon, conventionally, a lightly doped drain (LDD) structure (Patent Document 1) by ion implantation and a channel length are designed to be long, and the concentration of the drain electric field is reduced. (Non-Patent Document 1) and the like.
However, in the case of an oxide semiconductor, it has been difficult to apply an ion implantation technique. In addition, the method of designing a longer channel length has a disadvantage in that the high mobility characteristics inherent in the material are impaired.

JP 05-029338 A

Renesas Rev. 1.00 2006.06.12 4-11 Failure mechanism of semiconductor device

  The present invention has been made in view of the above problems, and the present invention provides a field effect transistor capable of suppressing heat generation even when used in such a manner that a high load is applied to a semiconductor layer, such as a driver circuit. Objective. Another object of the present invention is to provide a method for manufacturing such a field effect transistor.

  In the field effect transistor, the present inventors formed a source electrode and a drain electrode using a metal having a redox potential at 25 ° C. of −1.7 V to 0.4 V with respect to the standard electrode potential, and The inventors have found that the object can be achieved by setting the offset region of the gate electrode within the range of 0.1 μm or more and 5 μm or less, and completed the present invention.

According to the present invention, the following field effect transistor, a semiconductor device including the same, and a method for manufacturing the field effect transistor are provided.
1. A substrate includes at least a semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode, and the source electrode and the drain electrode are connected to each other through the semiconductor layer. A field effect transistor having a gate insulating film between semiconductor layers,
An oxidation-reduction potential at 25 ° C. of at least a portion of the source electrode and the drain electrode in contact with the semiconductor layer is −1.7 V or more and 0.4 V or less with respect to a standard electrode potential, and
A field-effect transistor having an offset region within a range of 0.1 μm to 5 μm.
2. 2. The field effect transistor according to 1, wherein a thickness of a portion of the source electrode and drain electrode in contact with the semiconductor layer is 5 nm or more and 50 nm or less.
3. 3. The field effect transistor according to 1 or 2, wherein at least portions of the source electrode and the drain electrode that are in contact with the semiconductor layer are made of a metal or alloy containing at least one selected from Ti and Mo. .
4). 4. The field effect transistor according to any one of 1 to 3, wherein the semiconductor layer contains one or more elements selected from In, Ga, Sn, and Zn.
A semiconductor device provided with the field effect transistor in any one of 5.1-4.
6). A substrate includes at least a semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode, and the source electrode and the drain electrode are connected to each other through the semiconductor layer. A method of manufacturing a field effect transistor having a gate insulating film between semiconductor layers,
Forming at least a portion of the source and drain electrodes in contact with the semiconductor layer by using a metal having a redox potential at 25 ° C. of −1.7 V to 0.4 V with respect to a standard electrode potential;
A field effect transistor manufacturing method comprising: forming an offset region within a range of 0.1 μm to 5 μm; and an annealing step performed after the semiconductor layer, the source electrode, and the drain electrode are stacked. Method.

According to the present invention, it is possible to provide a field effect transistor and a semiconductor device that can suppress heat generation even when the semiconductor layer such as a driver circuit is subjected to a high load.
According to the present invention, a method of manufacturing a field effect transistor having the above characteristics can be provided.

It is a figure which shows the result of having measured the magnitude | size of the drain current (Id) accompanying the change of the gate voltage (Vg) of the thin-film transistor produced in Example 1. FIG. It is a schematic diagram which shows the position of the offset region of a top gate / bottom contact type transistor. It is a schematic diagram which shows the position of the offset area | region of a bottom gate top contact type transistor.

The field effect transistor of the present invention has at least a semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a substrate, and the source electrode and the drain electrode are interposed through the semiconductor layer. A field effect transistor having a gate insulating film between the gate electrode and the semiconductor layer,
An oxidation-reduction potential at 25 ° C. of at least a portion of the source electrode and the drain electrode in contact with the semiconductor layer is −1.7 V or more and 0.4 V or less with respect to a standard electrode potential, and
It has an offset region within a range of 0.1 μm to 5 μm.

  The reason why a metal having a voltage of −1.7 V or more and 0.4 V with respect to the standard electrode potential is used for the source electrode and the drain electrode is that the interface with the semiconductor layer is appropriately oxidized by annealing described later, and is expressed by a silicon semiconductor. This is because an n-layer is realized. Usually, when the interface between the electrode and the semiconductor layer is oxidized, a parasitic transistor often called a hump is easily generated. In the case where the source electrode and the drain electrode are formed of a metal (for example, Mg) whose oxidation-reduction potential is less than −1.7 V with respect to the standard electrode potential, the source electrode and the drain electrode are easily oxidized by contact with the oxide semiconductor layer. Incurs an increase. When they are formed of a metal whose oxidation-reduction potential exceeds 0.4 V (eg, Ag, Au, Pt, etc.), no oxidation reaction occurs even by oxidation annealing treatment or the like. For this reason, the offset region remains as an insulating layer as it is and becomes a parasitic resistance, so that the On current does not flow sufficiently.

  In the present invention, a metal having an oxidation-reduction potential of −1.7 V or more and 0.4 V or less with respect to the standard electrode potential is actively used, and an offset from the gate electrode region is provided at a predetermined distance. A field effect transistor having an excellent On-Off ratio can be obtained.

  Since a transistor having an offset region generally causes a significant decrease in on-current, it is usually designed so that the offset region is not formed. Here, the “offset region” refers to a distance between a region where the gate bias is effective and the source electrode and the drain electrode, that is, a region where the gate effect is not effective (the gate voltage is not applied). When viewed from the top surface of the transistor stack, it is a region where a semiconductor layer (channel layer) exists and does not overlap any of the source electrode, the drain electrode, and the gate electrode. A schematic diagram showing the position of the offset region seen from the cross section of the top gate / bottom contact transistor is shown in FIG. 1, and a schematic diagram showing the position of the offset region seen from the cross section of the bottom gate / top contact transistor is shown in FIG. Show.

  In general, it is considered that the positional relationship between the gate electrode, the source electrode, and the drain electrode should be neither overlapping nor offset. Since the accuracy of alignment and lithography in the photolithography process affects the formation of overlap and offset regions, a highly accurate resist is used, or a self-aligned process using a gate electrode or the like as a mask is used.

  On the other hand, the present invention can appropriately oxidize the interface between the source and drain electrodes and the semiconductor layer by using the source and drain electrodes having a redox potential within a predetermined range even if there is a slight offset region. In this case, the fact that conduction with the channel layer (semiconductor layer) is maintained is positively utilized. As a result, an n-layer is realized like a silicon semiconductor, and a transistor having an excellent On-Off ratio can be obtained.

  As a phenomenon, when a metal such as Ti or Mo is used for the source electrode and the drain electrode, a thin TiOx layer or MoOx layer is generated between the source and drain electrodes and the semiconductor layer. Since these layers have moderate conductivity, the electric field strength at the interface can be relaxed, and generation of hot carriers that cause heat generation can be suppressed. It is conventionally known that an interfacial oxide film is formed by laminating Ti or Mo with an oxide thin film, but by controlling the film thickness of Ti or Mo, a film of a suboxide layer such as TiOx or MoOx It was not known that the thickness could be controlled.

Moreover, the electrical resistance of the suboxide layer can be continuously changed in the depth direction by appropriately setting the annealing conditions.
Furthermore, in the present invention, by providing an offset region of 0.1 μm or more and 5 μm or less, humps caused by parasitic transistors and off current floating can be prevented, and heat generation is suppressed, so that stable operation can be achieved even for a long time. It becomes possible to show TFT characteristics.

Hereinafter, preferred embodiments of the field effect transistor of the present invention will be described for each component of the field effect transistor.
(1) Semiconductor layer (channel layer)
The semiconductor layer is preferably made of an amorphous oxide semiconductor such as IGZO, ITZO, IZO, GZO, ZTO, or SnO, or a crystalline semiconductor such as IZO, IGO, In ₂ O ₃ , or ZnO. The present invention suppresses hot carriers in the vicinity of the drain electrode, and the effect is greater as the semiconductor layer is formed of a material having higher mobility.
The semiconductor layer preferably contains one or more elements selected from In, Ga, Sn, and Zn.

  The film thickness of the semiconductor layer is usually 0.5 to 500 nm, preferably 1 to 150 nm, more preferably 3 to 80 nm, and particularly preferably 10 to 60 nm. If the thickness is 0.5 nm or more, the film can be uniformly formed industrially, and if it is less than 500 nm, the film formation time does not become too long and can be industrially employed. Moreover, when it exists in the range of 3-80 nm, TFT characteristics, such as a mobility and an on / off ratio, are especially favorable.

(2) Source electrode and drain electrode In the present invention, at least a portion of the source electrode and drain electrode that contacts the semiconductor layer has an oxidation-reduction potential at 25 ° C. of −1.7 V or more with respect to the standard electrode potential. It must be 0.4V or less. If the oxidation-reduction potential at the portion in contact with the semiconductor layer is −1.7 V or more, the electrode itself is stable, the oxygen is moderately extracted and the interface is not insulated, and if it is 0.4 V or less. The oxidation reaction at the interface with the oxide semiconductor layer is sufficiently advanced, and a low carrier concentration range can be positively created.

  In addition, the part which contacts the semiconductor layer of a source electrode and a drain electrode should just consist of the material which has the said oxidation-reduction potential, and the part which does not contact a semiconductor layer may consist of the material which does not have the said oxidation-reduction potential. .

Specific materials having the oxidation-reduction potential include Cr, Ti, In, V, Mo, Sn, Pb, Cu, and the like, but considering workability, mass productivity, conductivity, etc., Ti, Mo, and Cu is preferred.
The source electrode and the drain electrode may have a laminated structure such as Ti / Al or Mo / Ag / Mo.
In addition, the metal in the portion in contact with the semiconductor layer may contain a trace amount of other elements in a range where the oxidation-reduction potential satisfies −1.7 V to 0.4 V with respect to the standard electrode potential. An alloy may be used. Specific examples of the alloy include AlNd, MoW, CuMn, MoTa, and MoTi.
More preferably, at least portions of the source electrode and the drain electrode that are in contact with the semiconductor layer are made of a metal or alloy containing at least one selected from Ti and Mo.

The redox potential of a metal or alloy with respect to a standard potential electrode can be measured as follows.
(1) Electrolytic Solution A water-soluble supporting electrolyte 0.1 mol / L such as LiF or LiClO ₄ is dissolved in pure water to obtain an electrolytic solution. The electrolytic solution is kept at 25 ° C. using a thermostatic bath or the like, and an inert gas such as nitrogen is bubbled for about 30 minutes to remove dissolved oxygen in the electrolytic solution.

(2) Measurement A potentiostat (BAS R600, Hokuto Denko HA-151, etc.) is prepared, platinum is connected to the counter electrode, a hydrogen electrode is connected to the reference electrode, and a small piece of the same quality as the metal material used in the present invention is connected to the working electrode. Then, it is immersed in the electrolytic solution. When each electrode is electrically connected via a potentiostat, the potential of the working electrode relative to the reference electrode is displayed. The potential of the working electrode is the oxidation-reduction potential of the metal material with respect to the standard electrode potential at 25 ° C.
A silver / silver chloride electrode or a saturated calomel electrode may be used instead of the hydrogen electrode. In this case, at 25 ° C., the values are displayed lower by 0.199 V and 0.244 V than the hydrogen electrode, respectively, so that these values are added to provide an electrode potential based on the hydrogen electrode.

  Moreover, the oxidation-reduction potential with respect to a standard electrode potential at 25 ° C. of a metal or an alloy is described in, for example, an electrochemical manual (edited by Electrochemical Association, Maruzen).

Moreover, it is preferable that the film thickness of the part which has a predetermined oxidation-reduction potential in contact with a semiconductor layer in a source electrode and a drain electrode is 5 nm or more and 50 nm or less. If the thickness of the portion of the source and drain electrodes in contact with the semiconductor layer is 5 nm or more, oxygen can be sufficiently extracted from the oxide, and a low carrier concentration region can be appropriately formed. In addition, since oxygen is moderately extracted, channel leakage does not occur. A more preferable film thickness of the portion in contact with the semiconductor is 7 nm or more and 30 nm or less.
In addition, what is necessary is just to select the film thickness of the whole of a source electrode and a drain electrode suitably, For example, the range of 5-300 nm is preferable, The range of 7-200 nm is more preferable, The range of 20-150 nm is further more preferable.

(3) Offset region In the present invention, it is essential that the offset region is in the range of 0.1 μm to 5 μm. Since there is an effect of reducing the Off current in the offset region, there is an appropriate range (offset interval). If the offset region is 0.1 μm or more, the off current does not increase and parasitic transistors such as humps are not generated. On the other hand, if the offset region is 5 μm or less, the source resistance and the drain resistance do not become excessively large, and the On current is unlikely to decrease. The offset region is more preferably 0.5 μm or more and 3 μm or less.

If the field effect transistor of this invention has the structure of said (1)-(3), other element structure will not be specifically limited, Well-known various element structure is employable.
The field effect transistor of the present invention can employ a known configuration such as a bottom gate, a bottom contact, and a top contact without limitation.

  There is no restriction | limiting in particular as a board | substrate, a gate electrode, and a gate insulating film which comprise the field effect transistor of this invention, A well-known material can be used and thickness, a shape, etc. should just be selected suitably.

Examples of the material for forming the gate insulating film include SiO ₂ , SiN _x , Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , MgO, ZrO ₂ , CeO ₂ , K ₂ O, Li ₂ O, and Na ₂ O. , Rb ₂ O, Sc ₂ O ₃ , Y ₂ O ₃ , HfO ₂ , CaHfO ₃ , PbTi ₃ , BaTa ₂ O ₆ , SrTiO ₃ , Sm ₂ O ₃ , AlN, and the like can be used. Among them, preferred are _{SiO 2, SiN x, Al 2} O 3, Y 2 O 3, HfO 2, CaHfO 3, more preferably _{SiO 2, SiN x, HfO 2} , Al 2 O 3.

The gate insulating film can be formed by, for example, a plasma CVD (Chemical Vapor Deposition) method.
Note that the number of oxygen in the oxide does not necessarily match the stoichiometric ratio, and may be, for example, SiO ₂ or SiO _x .
The gate insulating film may have a structure in which two or more insulating films made of different materials are stacked. The gate insulating film may be crystalline, polycrystalline, or amorphous, but is preferably polycrystalline or amorphous that can be easily manufactured industrially.

As a material for forming the gate electrode, for example, a transparent electrode such as ITO, IZO, ZnO, and SnO ₂ , a metal electrode such as Al, Ag, Cu, Cr, Ni, Mo, Au, Ti, and Ta, or these can be used. An alloy metal electrode can be used.

  The field effect transistor of the present invention may have elements other than the above-described components, and examples thereof include a semiconductor layer protective layer and an etch stopper layer. These film thicknesses, sizes, and the like may be selected as appropriate.

The field effect transistor of the present invention preferably includes a protective layer on the semiconductor layer. The protective layer of the semiconductor layer preferably contains at least SiN _x . Since SiN _x can form a dense film as compared with SiO ₂ , it has an advantage of a high TFT deterioration suppressing effect.

In addition to SiN _x , the protective layer may be, for example, SiO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , MgO, ZrO ₂ , CeO ₂ , K ₂ O, Li ₂ O, Na ₂ O, Rb ₂ O, Sc ₂ O ₃ , Y ₂ O ₃ , HfO ₂ , CaHfO ₃ , PbTi ₃ , BaTa ₂ O ₆ , Sm ₂ O ₃ , SrTiO _3, or an oxide such as AlN can be included.

Since the semiconductor device of the present invention includes the field effect transistor of the present invention, heat generation is suppressed even when the oxide semiconductor layer such as a driver circuit is subjected to a high load, and the durability is high.
The semiconductor device of the present invention only needs to include the field effect transistor of the present invention, and other device configurations are not particularly limited, and various known device configurations can be employed.

The method for producing a field effect transistor of the present invention (hereinafter referred to as the method of the present invention) has at least a semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a substrate. The source electrode and the drain electrode are connected through a semiconductor layer, and a method of manufacturing a field effect transistor having a gate insulating film between a gate electrode and a semiconductor layer,
Forming at least a portion of the source and drain electrodes in contact with the semiconductor layer by using a metal having a redox potential at 25 ° C. of −1.7 V to 0.4 V with respect to a standard electrode potential;
The method includes a step of forming an offset region within a range of 0.1 μm to 5 μm, and an annealing step performed after the semiconductor layer, the source electrode, and the drain electrode are stacked.

  In the method of the present invention, a method for manufacturing the semiconductor layer, the source electrode, the drain electrode, the gate insulating film, the gate electrode, and the like is not particularly limited, and a known method can be used.

(A) Formation of offset region In order to form the offset region within a range of 0.1 μm or more and 5 μm or less, a method using a photomask reflecting the offset region, a gate electrode, a source electrode, and a drain electrode itself are used. There is a method in which a mask (self-alignment) is used and an offset region within a predetermined range is obtained by adjusting the exposure amount or over-etching.

(B) Annealing treatment An annealing process performed after the semiconductor layer, the source electrode, and the drain electrode are stacked is performed to form an oxide film in the low carrier concentration region, that is, the interface between the semiconductor layer, the source electrode, and the drain electrode. . The annealing temperature is preferably 250 ° C. or higher and 400 ° C. or lower. If the annealing temperature is 250 ° C. or higher, oxygen is sufficiently extracted from the semiconductor, and a low carrier concentration region can be appropriately formed. If the annealing temperature is 400 ° C. or lower, the electrode material itself is deteriorated. There is no invitation. A more preferable range of the annealing temperature is 250 ° C. or higher and 350 ° C. or lower.
The annealing atmosphere may be an atmosphere of an inert gas such as nitrogen or argon in addition to air, or may be performed under oxidizing conditions such as an atmosphere containing water vapor or 20% or more oxygen.

Example 1
[Production of Thin Film Transistor]
A thin film transistor was fabricated with the following materials and conditions.
The channel mask and the source / drain mask used here were each designed to have a gap of 2 μm.

(1) Formation of gate electrode Eagle 2000 was used as non-alkali glass (substrate), and Cr was formed by sputtering. Next, a photoresist was applied, exposed, developed, and etched, and finally the resist was peeled to form a gate electrode.

(2) Formation of gate insulating film The substrate on which the gate electrode was formed was set in a CVD apparatus, and SiO ₂ was formed. SiO ₂ was formed by plasma chemical vapor deposition (PCVD) using SiH ₄ + N ₂ O + N ₂ gas to form a gate insulating film having a thickness of 50 nm.

(3) Formation of channel layer (semiconductor layer) The substrate with a gate insulating film was set in a sputtering apparatus, and a channel layer (semiconductor layer) was formed on the substrate with an insulating film under the following conditions.
Target: ITZO (In: Zn: Sn atomic ratio = 0.365: 0.15: 0.485)
Target-to-board distance: 88mm
Substrate temperature: 150 ° C
Gas flow rate: Ar / O ² = 15/15 sccm
Deposition pressure: 1Pa
Sputtering power: DC 100 W / cm ²
Film thickness: 45nm

(4) Patterning of channel layer Photoresist was applied on the formed channel layer, exposure, development, and dry etching were performed, and finally the resist was peeled off to obtain a patterned channel layer (semiconductor layer). .

(5) Formation of etch stopper film A substrate on which the patterned channel layer is formed is set in a CVD apparatus, and SiO ₂ is formed under the same conditions as the gate insulating film production except that the film thickness is set to 200 nm. A stopper film was obtained.

(6) Patterning of etch stopper film Photoresist was coated on the etch stopper film, exposed, developed, and dry etched, and finally the resist was peeled off to obtain a patterned etch stopper film.

(7) Formation of source and drain electrodes Ti / Al / Ti is formed on the patterned substrate by sputtering in the order of 20 nm, 50 nm, and 20 nm, respectively, and then a photoresist is applied, followed by exposure, development, and etching. Finally, the resist was stripped to form a source electrode and a drain electrode.
Table 1 shows the oxidation-reduction potential (V vs. NHE) with respect to the standard electrode potential at 25 ° C. of the portion of the source electrode and drain electrode that are in contact with the channel layer.

(8) Formation of protective layer and production of contact hole Further, the substrate on which the source electrode and the drain electrode are formed is set in a CVD apparatus, and a SiO ₂ film is formed under the same conditions as the film formation of the etch stopper. It was set as the protective layer of the layer (semiconductor layer). Next, a photoresist was applied on the protective layer, and exposure, development, and dry etching were performed. Finally, the resist was peeled off, and contact holes for a source electrode, a drain electrode, and a gate electrode were produced.

(9) Annealing Step The thin film transistor thus obtained was put in an oven and annealed in nitrogen at 350 ° C. for 1 hour.

[Characteristic evaluation of thin film transistor]
Using the thin film transistor thus obtained, the magnitude of the drain current (Id) accompanying the change in the gate voltage (Vg) was measured to evaluate the transfer characteristics. The drain voltage was set to 20V, and the gate voltage was changed from -15V to 20V. The results are shown in FIG.
Further, the field effect mobility and the off-current (Ioff) of the obtained thin film transistor were measured by the following method, and reliability evaluation was performed. The results are shown in Table 1.

-Field effect mobility (cm ² / Vs)
The saturation region mobility was derived according to the following formula, and the maximum value in the range of −15V to 20V of the gate voltage was selected to be the field effect mobility.

・ Ioff (off current) (A @ Vgs = -5V)
The drain current (Id) when the gate voltage (Vg) = − 5 V was defined as the off current (Ioff).

[Reliability evaluation]
The gate voltage (Vg) = 20 V and the drain voltage (Vd) = 20 V were set, and the transistor continued to operate for 10,000 seconds under the condition of 50 ° C. in the air, and the temperature of the drain region was evaluated with an infrared camera with a temperature measurement function. . Next, the transfer characteristics were evaluated again, and the gate voltage at which the drain current was turned on was compared before and after the reliability test, and the difference was defined as ΔVth (V). Table 1 shows the results of measuring the temperature (° C.) of the drain region and ΔVth.

As shown in Table 1, the field effect mobility (saturation region mobility) of this thin film transistor was 48 cm ² / Vs, and Ioff (off current) was a good value of 10 ⁻¹² or less. Furthermore, the temperature of the drain region when performing reliability was 53 ° C., and almost no increase in temperature was observed. Further, ΔVth was 0.1 V, which was found not to be deteriorated by the reliability test.

Example 2
As the sputtering conditions for the semiconductor layer, 2 × 10 ⁻³ Pa of water was introduced, and the film thicknesses of Ti / Al / Ti were set to 50 nm, 100 nm, and 50 nm, respectively, as source / drain electrodes. A thin film transistor was manufactured. The results are shown in Table 1.

Example 3
The composition of the semiconductor layer is In: Zn: Sn = 0.365: 0.3: 0.335 (atomic ratio), the sputtering condition of the semiconductor layer is the sputtering pressure of 0.2 Pa, and the source / drain electrodes are Ti / A thin film transistor was fabricated in the same manner as in Example 1 except that the thickness of Al / Ti was 5 nm, 50 nm, and 5 nm, respectively. The results are shown in Table 1.

Example 4
The composition of the semiconductor layer was set to In: Zn: Ga = 0.5: 0.1: 0.4 (atomic ratio), the offset region between the source / drain electrodes and the gate electrode was set to 4 μm, and the annealing condition was set to 400 ° C. A thin film transistor was manufactured in the same manner as in Example 1 except that. The results are shown in Table 1.

Example 5
The composition of the semiconductor layer was In: Zn: Ga = 0.55: 0.25: 0.2 (atomic ratio), and Al ₂ O ₃ was formed as a protective film to a thickness of 200 nm using an ALD (Atomic Layer Deposition) method. . Further, the material of the gate insulating film is Al ₂ O ₃ , the material of the source and drain electrodes is AlNd, the film thickness is 30 nm, the offset region between the source / drain electrodes and the gate electrode is set to 3 μm, and the annealing conditions are set. A thin film transistor was fabricated in the same manner as in Example 1 except that the temperature was 300 ° C. The results are shown in Table 1.

Examples 6-11
Hereinafter, TFT characteristics and reliability were evaluated by appropriately changing the composition of the semiconductor film, the sputtering conditions, the composition of the gate insulating film, the material and film thickness of the source / drain electrodes, the offset region setting, the annealing temperature, and the like. Each condition and evaluation result are shown in Table 1.

Comparative Example 1
A thin film transistor was fabricated in the same manner as in Example 1 except that the offset region was 0 μm. The results are shown in Table 1. In the case where there is no offset region, the oxygen extraction portion from the semiconductor region proceeds to the inside of the channel, and this portion has acted as a parasitic transistor. As a result, as a result of evaluating the transfer characteristics, it was observed as a hump in which Vth rises from Vg = −5V. Therefore, such a thin film transistor was not evaluated for reliability.

Comparative Example 2
A thin film transistor was fabricated in the same manner as in Example 1 except that the offset region was set to 10 μm. The results are shown in Table 1. When the offset region was made too large, the low carrier region did not reach the channel, so no drain current flowed even when a gate bias was applied.

Comparative Example 3
A thin film transistor was formed in the same manner as in Example 1 except that Au was used for the source / drain electrodes. The results are shown in Table 1. Since Au has a redox potential of +1.5 V, oxygen is not extracted from the semiconductor layer. For this reason, a low carrier concentration region was not formed, the offset became a high resistance layer, and the transistor did not operate.

Comparative Example 4
A thin film transistor was formed in the same manner as in Comparative Example 3 except that the offset region was set to 0 μm. As a result, it began to operate as a transistor, but since there was no low carrier concentration region, a high electric field region was generated in the vicinity of the drain in the reliability test, leading to deterioration of the transistor. When this situation was observed with an infrared microscope equipped with a temperature measurement function, it was found that the drain region reached 150 ° C.

  The field effect transistor of the present invention is particularly useful as a panel display, a circuit for controlling a video signal (gate driver, demultiplexer, signal driver), or a driver such as a touch sensor.

DESCRIPTION OF SYMBOLS 10 Substrate 12 Source electrode 14 Drain electrode 16 Semiconductor layer 18 Gate electrode

Claims (6)

A substrate includes at least a semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode, and the source electrode and the drain electrode are connected to each other through the semiconductor layer. A field effect transistor having a gate insulating film between semiconductor layers,
An oxidation-reduction potential at 25 ° C. of at least a portion of the source electrode and the drain electrode in contact with the semiconductor layer is −1.7 V or more and 0.4 V or less with respect to a standard electrode potential, and
A field-effect transistor having an offset region within a range of 0.1 μm to 5 μm.   2. The field effect transistor according to claim 1, wherein a film thickness of a portion of the source electrode and the drain electrode in contact with the semiconductor layer is 5 nm or more and 50 nm or less.   3. The field effect according to claim 1, wherein at least portions of the source electrode and the drain electrode that are in contact with the semiconductor layer are made of a metal or an alloy containing at least one selected from Ti and Mo. 4. Type transistor.   The field effect transistor according to claim 1, wherein the semiconductor layer contains one or more elements selected from In, Ga, Sn, and Zn.   A semiconductor device provided with the field effect transistor according to claim 1. A substrate includes at least a semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode, and the source electrode and the drain electrode are connected to each other through the semiconductor layer. A method of manufacturing a field effect transistor having a gate insulating film between semiconductor layers,
Forming at least a portion of the source and drain electrodes in contact with the semiconductor layer by using a metal having a redox potential at 25 ° C. of −1.7 V to 0.4 V with respect to a standard electrode potential;
A field effect transistor manufacturing method comprising: forming an offset region within a range of 0.1 μm to 5 μm; and an annealing step performed after the semiconductor layer, the source electrode, and the drain electrode are stacked. Method.

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