TWI660432B - Method for improving the electrical conductivity of metal oxide semiconductor layers - Google Patents

Abstract

The present disclosure provides a method for improving the conductivity of a metal-oxide semiconductor layer at a predetermined position. The method includes: providing a gold-oxide semiconductor layer on a substrate; providing a gold-oxide layer on top of the gold-oxide semiconductor layer by atomic layer deposition, wherein the gold-oxide layer is in physical contact at the predetermined positions. The metal oxide semiconductor layer. It is surprisingly found that this method causes the gold-oxygen semiconductor layer to have high conductivity at the predetermined positions. The method of the present disclosure can be advantageously used in the manufacturing process of self-aligned top gate metal-oxide semiconductor thin film transistors to improve the conductivity in the source region and the drain region.

Description

Method for improving conductivity of metal oxide semiconductor layer

The present disclosure relates to a method for locally improving the conductivity of a metal-oxide semiconductor layer.

The present disclosure further relates to a method for fabricating a thin film transistor based on a metal-oxide semiconductor.

Amorphous metal oxide thin film transistors (TFTs) (for example, Amorphous Indium-Gallium-Zinc Oxide (a-IGZO) thin film transistors) have been studied as flat plates Potential alternatives to silicon-based TFTs in display applications because of their higher coefficient of movement and larger area uniformity.

An advantage of the conventional amorphous silicon TFT, which is regarded as a switching device in an active matrix liquid crystal display, is that it has a large area uniformity. However, their field-effect movement coefficients (<1 cm ² / Vs) are too low to drive Organic Light-Emitting Diodes (OLEDs).

In contrast, crystalline p-Si TFTs, which are currently used as switching devices in AMOLED displays, have high coefficients of movement (> 50cm ² / Vs), and have large field-effect movement coefficients and critical voltage inhomogeneities in large-sized AMOLED displays Disadvantages.

The known bottom-gate TFT structure and top-gate TFT structure are not suitable for use in high-resolution displays because of their high parasitic capacitance and poor scalability. (scalability). The high parasitic capacitance in these TFT structures is related to the overlap between the source and the gate and / or between the drain and the gate. This overlap is due to the fact that the gate length of the transistor used is greater than the channel length, in order to avoid or limit the negative result of misalignment between the gate and the source and drain.

Therefore, a method for manufacturing a self-aligned top gate oxide TFT is currently being developed, in which a source and a drain align a gate, and among these, the TFTs will have good electrical performance and high stability. Several self-aligned top gate structures having an oxide semiconductor active layer have been described, in which the conductivity of the gold-oxygen semiconductor is locally improved in the source region and the drain region.

Several methods have been proposed to (locally) improve the conductivity of metal-oxide semiconductor materials. One of the methods consists of doping by ion implantation of impurities (for example, boron, phosphorus, or arsenic). However, ion implantation on a flexible substrate may be difficult because an annealing step is required to perform dopant activation, which is usually performed at a temperature above 450 ° C.

The other method consists of performing argon plasma treatment, hydrogen plasma treatment, or NH ₃ plasma treatment. However, it has been observed that the source and drain regions undergoing plasma treatment have poor stability, and the effects of plasma treatment may disappear as a result of the further processing steps required to integrate the OLED.

US 2012/0001167 describes a method for making a self-aligned metal-oxide-semiconductor thin-film transistor, in which an alternative method is used to locally increase the conductivity of the metal-oxide semiconductor layer. After depositing a metal oxide semiconductor layer, a gate insulator, and a gate electrode, a metal film made of metal (for example, Ti, Al, or In) is provided, and the thickness of the metal film is 10 nm or less. . Next, heat treatment is performed in an oxygen-containing environment, for example, at a temperature of 300 ° C. Office. Due to this thermal treatment, the metal film is oxidized. During the oxidation reaction of the metal film, a part of the oxygen contained in a source region and a drain region of the gold-oxygen semiconductor layer is transferred to the metal film. Because the source region and the oxygen concentration in the drain region are reduced, it will cause a low-resistance region to be formed in an upper portion of the gold-oxygen semiconductor layer. The thickness of the metal film is preferably 10 nm or less, so that the metal film can be completely oxidized in the oxygen-containing environment during the thermal treatment. In this way, it is not necessary to perform an etching step to remove non-oxidized metal.

The method described in US 2012/0001167 requires a temperature of at least 200 ° C, For example, a size of 300 ° C. Therefore, this method is not compatible with some low-cost flexible substrates, such as, for example, PET (polyethylene terephthalate), PEN (polyethylene naphthalate), and PC (poly Carbonate), and may require the use of higher price plastic sheets with high thermal and / or chemical stability, such as PI (polyimide), PES (polyether fluorene), or PEEK (polyether Ether ketone). The method also requires good and precise control of the thickness of the metal layer in order to avoid the need to perform an etching step to remove non-oxidized metal.

An object of the present disclosure is to provide a method for locally improving the conductivity of a metal-oxide semiconductor layer, wherein the high conductivity has good temperature stability, and wherein the method can be implemented at a temperature lower than 200 ° C. .

A further object of this disclosure is to provide a method for making a source with good source and drain contacts, a good field effect shift coefficient (for example, higher than 10 cm ² / Vs), good thermal stability, and good bias stability. A method of self-aligning the top gate metal-oxide semiconductor thin film transistor, wherein the transistors can be fabricated at a temperature lower than 200 ° C.

This disclosure relates to a method for improving the conductivity of a metal-oxide-semiconductor layer at a predetermined position. Electrical method. The method includes: providing a metal oxide semiconductor layer on a substrate; and providing an metal oxide layer on top of the metal oxide semiconductor layer by atomic layer deposition (ALD), wherein the metal oxide layer is on the substrate. The gold-oxide semiconductor layer is physically contacted (ie, interfaced by a direct physical interface) at the predetermined locations.

It was surprisingly found that depositing the gold-oxide layer by ALD would cause the gold-oxide semiconductor layer to have high conductivity at the location where the gold-oxide layer directly physically contacts the gold-oxide semiconductor layer.

In the embodiments of the present disclosure, for example, the thickness of the gold-oxide semiconductor layer may be in a range between 10 nm and 100 nm, or in a range between 11 nm and 99 nm. The present disclosure is not limited to this.

In the embodiments of the present disclosure, providing (for example, depositing) the gold oxide layer by atomic layer deposition may be performed at a temperature in a range between 150 ° C and 200 ° C.

In an embodiment of the present disclosure, the method may further include: providing an alkali metal (for example, Li, Na, K, Rb, Cs, or Is any one or any combination of Fr) or an alkaline earth metal (for example, any one or any combination of Be, Mg, Ca, Sr, Ba, or Ra) Suppose that the metal-oxide semiconductor layer is physically contacted at a position; a chemical reduction reaction is induced between the reduction layer and the metal-oxide semiconductor layer, for example, by a temperature in a range between 20 ° C and 200 ° C Performing an annealing step; and removing reaction byproducts of the reducing layer and the reduction reaction, for example, by rinsing in water or alcohol.

In the embodiment of the present disclosure, for example, the metal oxide semiconductor layer may include gallium indium zinc oxide (GIZO or IGZO); and, for example, the metal oxide layer may include Al ₂ O ₃ . However, the present disclosure is not limited to this. Other metal oxide semiconductors can also be used, for example, ZnO, ZnSnO, InO, InZnSnO, LaInZnO, GaInO, HfInZnO, MgZnO, LaInZnO, TiO, TiInSnO, ScInZnO, and SiInZnO and ZrInZnO, or ZrZnSnO. Other metal oxide layers can also be used, for example, HfO ₂ , Ta ₂ O ₅ , ZrO ₂ , or Ga ₂ O ₃ .

In the embodiment of the present disclosure in which the metal oxide layer is an Al ₂ O ₃ layer, the metal oxide layer may be deposited using trimethyl aluminum and water (H ₂ O) as precursors, or, for example, Triethyl aluminum and water were used as precursors or triisobutyl aluminum and water were used as precursors to deposit.

In the embodiment of the present disclosure, when forming the metal oxide layer, different precursor bodies may be mixed or different precursor bodies may be used alternately.

The present disclosure further relates to a method for fabricating a self-aligned (meaning that the source and the drain will self-align the gate) the top gate (the gate is provided on the top of the metal-oxide semiconductor layer) of the metal-oxide semiconductor thin film transistor. method. The method includes: providing a metal oxide semiconductor layer on a substrate; depositing a gate dielectric layer on top of the metal oxide semiconductor layer; depositing a gate electrode layer on the gate dielectric layer; patterning the gate The electrode electrode layer and the gate insulating layer are used to form a gate electrode and a gate insulator, thereby defining a channel region in the gold-oxide semiconductor layer; patterning the gold-oxide semiconductor layer, thereby forming a gold-oxide semiconductor layer A semiconductor region defines a source region and a drain region; and a metal oxide layer is deposited by atomic layer deposition, for example, at least in the source region and the drain region, and thus in the source region. Where the metal oxide layer is in direct physical contact with the metal oxide layer in the drain region (that is, interfaced by a direct physical interface), the metal oxide semiconductor layer improves the conductivity of the metal oxide layer .

The method may further include: providing a dielectric layer on top of the metal oxide layer; forming a through hole penetrating the dielectric layer and the metal oxide layer; and filling the through holes with a metal to form a source electrode The contact is connected to a drain contact.

In the embodiment of the present disclosure, the method can be applied to the metal-oxide semiconductor layer. The step of providing the metal oxide layer further includes: providing an alkali metal (for example, any one or any combination of Li, Na, K, Rb, Cs, or Fr) or an alkaline earth metal (for example , Any one or any combination of Be, Mg, Ca, Sr, Ba, or Ra)) physically contact the gold-oxygen semiconductor layer at the predetermined positions; the reduction layer and the gold A chemical reduction reaction is induced between the oxygen semiconductor layers, for example, by performing an annealing step at a temperature in a range between 20 ° C and 200 ° C; and removing the reaction side of the reduction layer and the reduction reaction Product, for example, by rinsing in water or alcohol.

An advantage of the method of the present disclosure is that it can be used at temperatures below 200 ° C, or below It is carried out at a temperature of 199 ° C, or lower than 190 ° C, or lower than 180 ° C, or lower than 170 ° C, or lower than 160 ° C. Therefore, these methods are compatible with low-cost flexible substrates such as, for example, PET (polyethylene terephthalate), PEN (polyethylene naphthalate), and PC (polycarbonate ).

An advantage of the method of the present disclosure is that it is less or not necessary to precisely control the layer thickness as is the case in some prior art approaches.

An advantage of the method of the present disclosure is that the deposition of the metal oxide layer not only results in improved conductivity of the underlying metal oxide semiconductor layer; in addition, the deposition of the metal oxide layer also causes passivation and encapsulation of the metal oxide semiconductor layer below ( For example, the gold-oxide semiconductor layer would be completely covered or encapsulated, that is, no longer exposed to the environment).

An advantage of the methods of the present disclosure is that they result in good stability of the high conductivity of the gold-oxide semiconductor layer; the high conductivity does not change over time.

The advantage of the methods of this disclosure is that they allow fabrication with good bias stability Qualitative and self-aligned top-gate metal-oxide semiconductor thin film transistor with good thermal stability.

The specific objects and advantages of the various innovative ideas of the invention have been described above herein. Of course, it should be understood that not all of these objects or advantages may be achieved according to any particular embodiment of the present disclosure. Thus, for example, those skilled in the art will understand that this disclosure may achieve or optimize one of the advantages or a group of advantages as taught herein but may not achieve other advantages that may be taught or suggested herein. A way to achieve or achieve a purpose or advantage. Further, it should be understood that the [Summary] is merely an example and is not intended to limit the scope of the present disclosure. With reference to the detailed description below, and accompanying drawings when reading, you can best understand this disclosure (organization and its operation method) and its characteristics and advantages.

10‧‧‧ substrate

11‧‧‧Active Level

12‧‧‧ Metal Oxide Semiconductor Layer

13‧‧‧Gate dielectric layer

14‧‧‧Gate electrode layer

15‧‧‧metal oxide layer

16‧‧‧ Dielectric layer

21‧‧‧Source electrode

22‧‧‧ Drain electrode

101‧‧‧ silicon substrate

102‧‧‧ Dielectric layer

110‧‧‧passage zone

111‧‧‧Source area

112‧‧‧ Drain

131‧‧‧Gate insulator

141‧‧‧Gate electrode

1 (a) to 1 (f) are a method for fabricating a gold-oxide semiconductor thin film transistor according to a method of the present disclosure.

The conversion characteristic curve (I _DS -V _GS ) of an a-IGZO thin film transistor manufactured according to a method of the present disclosure is shown in FIG. 2.

The output characteristic curve (I _DS -V _DS ) of an a-IGZO thin film transistor manufactured according to a method of the present disclosure is shown in FIG. 3.

Figure 4 shows the conversion characteristic curves (I _DS ) of a-IGZO TFT (W / L = 30 / 10μm / μm) fabricated according to a method of the present disclosure at different bias stress times. -V _GS ): Figure 4 (a) is the negative bias stress of -1MV / cm (V _GS = -12V and V _DS = 0V); Figure 4 (b) is + 1MV / cm (V _GS = + 12V and V _DS = + 12V).

The relationship between the V _TH offset of the a-IGZO TFT fabricated in accordance with one method of the present disclosure as a function of the stress time in the positive and negative directions is shown in FIG. 5.

The initial conversion characteristic curve (open circle) of the system a-IGZO TFT (W / L = 30 / 10μm / μm) shown in FIG. 6 and the conversion characteristic curve (solid square) after annealing at 150 ° C in nitrogen for 2 hours ).

Any element symbol in the scope of patent application shall not be considered as being limited to the scope of the present disclosure.

In different drawings, the same element symbol indicates the same or similar element.

Numerous specific details are set forth in the following detailed description in order to provide a clear understanding of the disclosure and how to implement the disclosure in particular embodiments. It should be understood, however, that the present disclosure can be practiced without these specific details. In other instances, well-known methods, procedures, and techniques will not be described in detail to avoid confusing the present disclosure.

Although the present disclosure is described with reference to specific embodiments and with reference to specific drawings, the present disclosure is not limited thereto. The drawings included and described herein are sketches and do not limit the scope of the disclosure. It should also be noted that in the drawings, for the purpose of explanation, the size of some elements may be enlarged, and therefore not drawn to scale.

Furthermore, the first, second, third, and similar words in the description are used to distinguish similar elements and do not necessarily describe the order of time or space in terms of rank or any other way. It should be understood that the terms used are interchangeable under appropriate circumstances and that the embodiments of the disclosure described herein can operate in other orders than described or shown herein.

In addition, the top, bottom, top, bottom, and the like in the description are for the purpose of description and do not necessarily describe relative positions. It should be understood that these terms are used interchangeably under appropriate circumstances and that the embodiments of the disclosure described herein can be used herein Work in directions other than those described or shown.

The present disclosure provides a method for improving (increasing) the conductivity of metal oxide semiconductor layers. For example, the location of the source and drain contacts of a metal oxide semiconductor thin film transistor can be improved locally. Conductivity. The increase in conductivity can be significant, for example, by at least 1 size level, for example, up to 3 size levels.

According to an aspect of the present disclosure, a method for improving the conductivity of a metal oxide semiconductor layer at a predetermined position is provided. The method includes: depositing a metal oxide layer at the predetermined positions by atomic layer deposition. On top of the metal oxide semiconductor layer and physically contacting (and thus interfacing) the metal oxide semiconductor layer.

It was surprisingly found that depositing the gold-oxide layer by ALD would cause the gold-oxide semiconductor layer to have high conductivity at the location where the gold-oxide layer directly physically contacts the gold-oxide semiconductor layer.

For example, the gold-oxygen layer may include Al ₂ O ₃ , HfO ₂ , Ta ₂ O ₅ , ZrO ₂ , or Ga ₂ O ₃ , but the present invention is not limited thereto.

In the embodiment of the present disclosure, for example, the gold-oxygen layer may be an Al ₂ O ₃ layer. For example, it may be trimethylaluminum _{(TMA, Al (CH 3)} 3) and water (H ₂ O) as a precursor to deposit. However, other precursors can also be used, for example, using triethylaluminum and water as the precursor or triisobutylaluminum and water as the precursor to form an Al ₂ O ₃ layer.

In the embodiment of the present disclosure, for example, the gold-oxygen layer may be a Ga ₂ O ₃ layer. For example, precursors that can be used in this layer include triethylgallium and water, trimethylgallium and water, triisopropylgallium and water, or tri-tert-butylgallium and water, but the invention does not Not limited to this.

In the embodiment of the present disclosure, when forming the metal oxide layer, different precursor bodies may be mixed or different precursor bodies may be used alternately.

For example, the thickness of the metal oxide layer can be in a range between 10 nm and 100 nm, and for example, it can be deposited at a temperature in a range between 150 ° C. and 200 ° C., for example Between 150 ° C and 170 ° C, but the invention is not limited to this.

The method of the present disclosure can be advantageously used in the manufacturing process of a thin film transistor having an active metal oxide layer to locally improve the conductivity at a predetermined position corresponding to the source region and the drain region, thereby Improve the charge emission from these source and drain contacts. This method can be advantageously used in the fabrication of self-aligned top gate thin film transistors.

This method can also be used in the fabrication of other metal-oxide-semiconductor-based devices (for example, diodes or transistors-diodes) to improve charge emission from the contacts.

For example, the gold-oxide semiconductor layer can include gallium indium zinc oxide (GIZO or IGZO), or a semiconductor based on other metal oxides. For example, the following composition (which is not ideally formulated) Ratio indication): ZnO, ZnSnO, InO, InZnSnO, LaInZnO, GaInO, HfInZnO, MgZnO, LaInZnO, TiO, TiInSnO, ScInZnO, SiInZnO, and ZrInZnO, ZrZnSnO. However, the present disclosure is not limited to this, and the method can be applied to other suitable metal-oxide semiconductors known to those skilled in the art. Semiconductor layers with a typical thickness between 5nm and 50nm, or between 6nm and 49nm, can be provided by many methods, such as, for example, sputtering, thermal evaporation, pulsed laser deposition And spin casting, inkjet printing, or drop casting precursor solution.

This article further illustrates a method for fabricating a self-aligned top gate metal-oxide-semiconductor thin film transistor, wherein the method of the present disclosure is used to locally improve the conductivity of the metal-oxide semiconductor layer in the source and drain regions. . In this device structure, the ALD metal oxide layer will The conductivity of the underlying source and drain regions is changed, and it also has a function of passivation and encapsulation.

An exemplary process flow for fabricating a metal-oxide-semiconductor thin film transistor according to the present disclosure is schematically illustrated in FIGS. 1 (a) to 1 (f).

In the first step shown in FIG. 1 (a), a gold-oxide semiconductor layer 12 (for example, a GIZO layer) is provided on a substrate 10, for example, by sputtering from a precursor solution Plating, laser ablation, or spin coating. In the example shown in FIG. 1 (a), the substrate 10 includes a silicon substrate 101 and a dielectric layer 102 (for example, a silicon oxide layer); however, other suitable substrates may be used. For example, the thickness of the GIZO layer 12 is about 10 nm or about 15 nm to 20 nm, for example, between 10 nm and 20 nm, or between 11 nm and 19 nm; however, other suitable thicknesses can be used. .

Next, as shown in FIG. 1 (b), a gate dielectric layer 13 (for example, a silicon dioxide layer) is deposited on top of the gold-oxide semiconductor layer 12, for example, by electricity Slurry enhanced chemical vapor deposition. Thereafter, a gate electrode layer 14 (for example, a Mo layer) is deposited on top of the gate dielectric layer 13 (FIG. 1 (b)).

The gate electrode layer 14 and the gate insulating layer 13 are then patterned. For example, by dry etching, a gate electrode 141 and a gate insulator 131 are formed, as shown in FIG. 1 (c). .

Then, the gold-oxygen semiconductor layer 12 is patterned to define the active layer 11 of the thin film transistor (FIG. 1 (d)). For example, the gold-oxide semiconductor layer can be patterned by wet etching, for example, using buffered HF or oxalic acid. The advantage of using oxalic acid in active layer patterning is its good selectivity to the underlying layers. The patterned gate electrode 141 defines a channel region 110, a source region 111, and a drain region 112 in the active layer 11, as shown in FIG. 1 (d). Medium outline display. The source and drain regions are directly adjacent to the channel region and are self-aligned.

In the example shown in FIG. 1, the metal-oxide semiconductor layer is patterned only after the gate electrode layer and the gate dielectric layer are patterned; however, the present disclosure is not limited thereto. For example, the gold-oxide semiconductor layer can also be patterned before the gate fabrication process, or it can be patterned at a later stage after the gate fabrication process.

Next, a metal oxide layer 15 (for example, an Al ₂ O ₃ layer) is processed by ALD (for example, trimethyl aluminum (TMA, Al (CH ₃ ) ₃ ) and water (H ₂ O ) As a precursor (as shown in Figure 1 (e)). It was surprisingly found that depositing this layer would cause the gold oxide semiconductor layer to have high electrical conductivity at the location where the Al ₂ O ₃ layer 15 directly contacts the gold oxide semiconductor layer 11. Therefore, enhanced conductivity is achieved in the source region 111 and the drain region 112 of the gold-oxide semiconductor layer 11, at least in an upper portion of the gold-oxide semiconductor layer. It is believed that because of the interaction between the ALD precursors and the surface of the metal oxide semiconductor layer, there will be a doping effect or a reduction reaction. For example, TMA and H ₂ O, which are precursors to ALD in Al ₂ O ₃ , can react with the surface of IGZO. For example, if H ₂ O, O ₂ , and O ₃ are present in the reaction, the doping effect will occur. The upper part preferably has a depth / thickness of a few nm to 10 or about 10 nm. If the ALD metal-oxide deposition is combined with additional doping (for example, using Ca, see above), then the enhanced conductivity is expected to extend deeper into the metal-oxide semiconductor layer, for example, Up to tens of nm, for example, up to 20 nm or up to 30 nm.

Next, a dielectric layer 16 (for example, a silicon nitride layer) is provided on top of the metal-oxide layer 15, and then a via is formed at a position where a source contact and a drain contact are to be formed. Holes penetrate through the dielectric layer 16 and the metal-oxide layer 15 below. The through holes are then filled with a suitable metal (for example, Mo) to form a source electrode 21 and a drain electrode 22. The generated structure is schematically shown in Fig. 1 (f).

The conversion characteristic curve (I _DS -V _GS ) of an a-IGZO thin film transistor manufactured according to a method of the present disclosure as described above is shown in FIG. 2, which has an ALD Al ₂ O ₃ metal oxide layer. 15. The output characteristic curve (I _DS -V _DS ) of this transistor is shown in FIG. 3.

The a-IGZO TFT exhibits high thermal stability and good electrical performance. From the figure, a field-effect movement coefficient of 14.82 cm ² / VS, a critical voltage of 3.6 V, a subcritical swing of 0.42 V / dec, and an on / off current ratio of about 10 ⁸ are observed.

The present invention has studied the effect of bias stress on the electrical performance of a TFT. Corresponding to a positive and negative / cm gate electric field is applied for up to ¹⁰⁴ seconds of stress at the time in a dark room temperature to +/- 1.0MV. If it is a positive gate bias stress, which corresponds to a fully conducting condition (V _DS = 12V and V _GS = 12V), a threshold voltage shift of 0.8V will be observed. If it is a negative bias stress (V _DS = 0V and V _GS = -12V), a critical voltage offset of 1.0V will be observed. Figures 4 (a) and 4 (b) show that the negative gate bias stress (Figure 4 (a)) and the positive gate bias stress (Figure 4 (b)) are in different bias stress times below. The conversion characteristic curve: 0s (that is, no bias stress), 100s, 300s, 1000s, 3000s, and 10000s. The system shown in Figure 5 shifts V _TH as a function of stress time in the positive and negative directions. From these results, it is concluded that the stability under various stress conditions is very good.

The initial conversion characteristic curve (open circle) of the system a-IGZO TFT (W / L = 30 / 10μm / μm) shown in FIG. 6 and the conversion characteristic curve (solid square) after annealing at 150 ° C in nitrogen for 2 hours ). It can be concluded from these results that the effect of the annealing step on the device characteristic curve is negligible, which indicates that it has good thermal stability.

Although the foregoing description details specific embodiments of the disclosure; however, it should be understood that no matter how detailed the foregoing text is, the disclosure can be made in many ways Implemented. It should be noted that the use of special terms when describing particular features and perspectives of this disclosure should not be considered as metaphors. This term is redefined herein to include only features that are associated with this term in this disclosure or The specific characteristics of a viewpoint.

Although the above detailed description has shown, explained, and pointed out the novel features of the present invention applied to various embodiments; it should be understood that those skilled in the art can understand the device or process shown in the text. Various omissions, substitutions, and changes are made to the form and details without departing from the general concept of the point of view of the present invention.

Claims (11)

A method for fabricating a self-aligned top gate metal oxide semiconductor thin film transistor, comprising: providing a metal oxide semiconductor layer (12) on a substrate (10); and depositing a gate dielectric layer (13) on the metal oxide Top of the semiconductor layer (12); depositing a gate electrode layer (14) on the gate dielectric layer (13); patterning the gate electrode layer (14) and the gate insulation layer (13), Forming a gate electrode (141) and a gate insulator (131); patterning the gold-oxide semiconductor layer (12), thereby defining a source region (111) and a channel region (110) of the thin film transistor And a drain region (112); and a gold-oxygen layer (15) is deposited by atomic layer deposition so that the gold-oxygen is in the source region (111) and the drain region (112) Where the layer directly contacts the gold-oxide semiconductor layer, the conductivity of the gold-oxide semiconductor layer is improved. The method according to item 1 of the patent application range, wherein the thickness of the gold oxide layer (15) is in a range between 10 nm and 100 nm. The method according to item 1 of the scope of patent application, wherein the metal oxide layer (15) is deposited at a temperature in a range between 150 ° C and 200 ° C. The method according to item 1 of the patent application scope, wherein the gold-oxygen semiconductor layer (12) is a gallium indium zinc oxide layer. The method according to item 1 of the patent application scope, wherein the metal oxide layer (15) is an Al ₂ O ₃ layer. The method according to item 5 of the application, wherein the Al ₂ O ₃ layer is deposited using trimethylaluminum and water (H ₂ O) as reagents. The method according to item 1 of the patent application scope, wherein before depositing the metal oxide layer, further comprising: providing a reducing layer including an alkali metal or an alkaline earth metal to physically contact the metal oxide semiconductor at the predetermined positions A layer; inducing a chemical reduction reaction between the reducing layer and the gold-oxygen semiconductor layer; and removing reaction byproducts of the reducing layer and the reduction reaction. The method according to item 1 of the patent application scope, further comprising: providing a dielectric layer (16) on the top of the metal oxide layer (15); forming a through hole penetrating the dielectric layer (16) and the metal oxide layer ( 15); and filling the through holes with a metal to form a source electrode (21) and a drain electrode (22). The method according to item 1 of the patent application scope, wherein the method is carried out at a temperature below 200 ° C. The method according to item 1 of the patent application scope, wherein the substrate is a low-cost flexible substrate. The method according to item 1 of the patent application scope, wherein the substrate comprises PET (polyethylene terephthalate), PEN (polyethylene naphthalate), or PC (polycarbonate).