TW201405835A - A method for fabricating a thin film transistor - Google Patents

Abstract

A method for fabricating a bottom-gate top-contact metal oxide semiconductor thin film transistor, the method comprising: forming a gate electrode on a substrate; providing a gate dielectric layer covering the gate electrode; depositing a metal oxide semiconductor layer on the gate dielectric layer; depositing a metal layer on top of the metal oxide semiconductor layer; patterning said metal layer to form source and drain contacts, wherein patterning the metal layer comprises dry etching of the metal layer; and thereafter patterning the metal oxide semiconductor layer.

Description

Method of manufacturing thin film transistor

The disclosed technology relates to a method of fabricating a metal oxide semiconductor thin film transistor, and more particularly to a method of fabricating a metal oxide semiconductor bottom-gate top-contact thin film transistor, and a system Regarding the thin film transistor thus obtained.

Metal oxide semiconductors have potential applications in thin film electronic devices such as large area displays and circuits due to their ability to achieve excellent electrical characteristics at low processing temperatures. For example, a thin film transistor (TFT) using an amorphous gallium-indium-zinc-oxide (a-GIZO) as an active layer has been shown. Achieving good mobility (μ) and good threshold voltage (V _TH ) control is an important parameter for successfully replacing a conventional amorphous Si TFT substrate in a display with an amorphous metal oxide semiconductor TFT substrate.

In the fabrication of a bottom gate top contact type (BGTC) metal oxide semiconductor thin film transistor, an etch stop layer is typically used to protect the metal oxide semiconductor layer from plasma damage during further processing. In such a process, after the gate and gate dielectric layers are provided on the substrate, a metal oxide semiconductor layer is deposited over the gate dielectric layer and patterned. Next, depositing an etch stop layer on top of the metal oxide semiconductor layer, followed by patterning etch termination Floor. A metal layer is then deposited and patterned by dry plasma etching to form source and drain contacts. During this patterning to define the source and drain contacts, the etch stop layer protects the underlying metal oxide semiconductor layer from damage that may be caused by the metal etch process.

In an alternative process flow, the use of an etch stop layer can be avoided by patterning the metal layer on top of the metal oxide semiconductor layer using a wet etch process. However, finding an etchant that provides good etch selectivity between the metal layer and the metal oxide semiconductor layer is a major challenge that limits the combination of materials that can be used.

An inventive aspect relates to a method of fabricating a good metal oxide semiconductor thin film transistor, wherein patterning of source contacts and drain contacts on top of the metal oxide semiconductor layer is performed by dry etching, and There is no need to use an etch stop layer.

An inventive aspect relates to a method of fabricating a bottom gate top contact type metal oxide semiconductor thin film transistor, wherein the method comprises: forming a gate electrode on a substrate to provide a gate dielectric layer covering the gate electrode, And depositing a metal oxide semiconductor layer on the gate dielectric layer. The method may further comprise: depositing a metal layer or a metal layer on top of the metal oxide semiconductor layer; and patterning the metal layer or the metal layer stack to form a source contact and a drain contact of the thin film transistor, wherein the pattern The metal layer or metal layer stack comprises: a dry etched metal layer or a metal layer stack; and thereafter (eg, immediately thereafter) the patterned metal oxide semiconductor layer. The method can further include additional processing, such as depositing a passivation layer and/or annealing. The annealing step is preferably adapted to recover damage that may have been caused by the plasma process during device fabrication and/or to achieve good passivation.

The metal oxide semiconductor layer can be, for example, amorphous IGZO (indium gallium zinc oxide) Layer). However, the present invention is not limited thereto, and other metal oxide semiconductor layers such as an InZnO layer, an HfInZnO layer, a SiInZnO layer, a ZnO layer, a CuO layer, or a SnO layer may be used.

In a method according to an aspect of the invention, the patterned metal oxide semiconductor layer is performed after the metal layer or the metal layer stack on top of the patterned metal oxide semiconductor layer, that is, the source contact is defined and After the bungee contact. An advantage of the process steps using this sequence is that during metal dry etching, the risk of damaging the metal oxide semiconductor layer (eg, in the channel region of the thin film transistor) is compared to where the patterned metal oxide semiconductor layer is dried The process sequence (plasma) etched to pattern the metal layer or metal layer stack can be greatly reduced.

An advantage of the method according to one inventive aspect is that there is no need to provide and pattern an etch stop layer, thereby reducing the number of reticle required and thus reducing the number of process steps and reducing manufacturing costs.

An advantage of the method according to one inventive aspect is that the transistor size can be reduced, and in more detail the channel length can be reduced, relative to the method using an etch stop layer. For example, depending on the size of the substrate and the lithography tool used, a transistor having a channel length of about 2 microns to 5 microns can be fabricated using a method according to an inventive aspect, while prior art using an etch stop layer In the method, the lower limit of the channel length is about 5 microns to 20 microns. In general, the channel length can be reduced to about 1/3 relative to a thin film transistor fabricated using an etch stop layer. Therefore, when a method according to an inventive aspect is used in a manufacturing process of a display, a more compact pixel can be formed and a display with improved resolution can be manufactured.

An advantage of the method according to an inventive aspect is that it allows manufacturing to have good characteristics (such as good field effect mobility (for example, ranging between about 2 cm ² /Vs and 100 cm ² /Vs), low I _OFF current A metal oxide semiconductor thin film transistor (e.g., less than about 10 pA) and a low sub-threshold slope (e.g., less than about 1 V/decimal).

An advantage of the method according to one inventive aspect is that it is compatible with existing fabrication lines currently used for mass production of amorphous germanium thin film transistors and circuits. More specifically, the manufacturing steps used in accordance with aspects of the present invention can be performed in existing production lines for amorphous germanium TFTs. This also implies that the metal oxide TFT can be produced using a method according to a specific example of the present invention in an existing production line for an amorphous germanium TFT.

The method according to an inventive aspect can be advantageously used to fabricate an array of metal oxide semiconductor thin film transistors, such as for selecting or driving pixels of a display.

Certain objects and advantages of some inventive aspects have been described herein above. Of course, it should be understood that not all such objectives or advantages may be realized in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the present invention can be implemented or carried out in a manner that achieves or optimizes an advantage or advantage. Other goals or advantages. In addition, it should be understood that this summary is only an example and is not intended to limit the scope of the invention. The invention (as regards to the organization and method of operation), as well as its features and advantages, may be best understood by reference to the following embodiments in conjunction with the accompanying drawings.

Figure 1 schematically illustrates a process sequence in accordance with a specific example of the present invention.

2(a) through 2(e) illustrate a method in accordance with a specific example of the present invention.

Figure 3 shows the measured transmission characteristics of two GIZO thin film transistors: a GIZO thin film transistor (LO Mo) having a source contact and a drain contact formed by metal lift-off. And a GIZO thin film transistor (DE Mo) having a source contact and a drain contact deposited and patterned by dry etching after GIZO patterning without using an etch stop layer.

4 shows the measured transmission characteristics of a GIZO thin film transistor fabricated in accordance with the method of the specific example of the present invention.

Figure 5 shows the transmission characteristics of a GIZO thin film transistor measured at different locations of an array fabricated on a 6-inch substrate in accordance with an embodiment of the present invention.

Figure 6 shows three different treatments using standard BCE (S/D etching after IGZO etching), BCE process according to the aspect of the invention (S/D etching before IGZO etching), and conventional lift-off process. - Comparison result of transmission characteristics (V _GS -I _DS ) of IGZO TFT.

Figure 7 shows a capacitance comparison of MIS (with a-IGZO) and MIM (without a-IGZO) structures of area 500 x 500 μm ² showing less than 5% difference.

Figure 8 shows (a) a-IGZO TFT with W _GS = +12V and V _DS = +12V and (b) with V _GS = -12V and V _DS =0V with stress time (W/L = The transmission characteristic of 70/10 μm/μm) (V _GS -I _DS ), and the V _TH shift of the a-IGZO TFT as a function of stress time in both the positive and negative directions.

Figure 9 illustrates (a) transmission (V _GS -I _DS ) characteristics and (b) output (V _DS -I _DS ) characteristics of a driving TFT of W/L = 55/5 μm/μm, (c) spanning a 150 mm PEN foil substrate The transmission curves of the nine TFTs were measured (at V _DS = 10 V).

In the different figures, the same reference numerals are used to refer to the same or similar elements.

In the following embodiments, numerous specific details are set forth in order to provide a comprehensive understanding of the invention However, it should be understood that the present invention may be without such special Implemented under the details. In other instances, well-known methods, procedures, and techniques have not been described in detail so as not to obscure the invention. Although the invention will be described with respect to particular embodiments and with reference to certain drawings, the invention is not limited thereto. The drawings included and described herein are illustrative and not limiting of the scope of the invention. It is also noted that the size of some of the elements may be exaggerated in the drawings and, therefore, are not drawn to scale for illustrative purposes.

In addition, the terms first, second, third and the like in this specification are used to distinguish similar elements and are not necessarily used to describe a certain order, regardless of time, space, level or any other aspect. It is understood that the terms so used are interchangeable under appropriate circumstances and the specific embodiments of the invention described herein are capable of operation other than the sequence described or illustrated herein.

In addition, the terms top, bottom, upper, lower, and the like in this specification are used for descriptive purposes and are not necessarily used to describe relative positions. It is to be understood that the terms so used are interchangeable, where appropriate, and that the specific embodiments of the invention described herein are capable of operation other than the positioning described or illustrated herein.

It should be noted that the term "comprising" should not be construed as being limited to the components listed hereinafter; it does not exclude other elements or steps. It is therefore intended to be interpreted as indicating that the described features, integers, steps, or components are present, but do not exclude the presence or addition of one or more other features, integers, steps or components or groups thereof. Therefore, the expression "a device includes components A and B" should not be limited to that the device consists only of components A and B.

Some specific examples provide a method of fabricating a bottom gate top contact type metal oxide semiconductor thin film transistor, wherein the method comprises: forming a gate electrode on a substrate, providing a gate dielectric layer covering the gate electrode, and depositing Metal oxide semiconductor layer On the floor. In one embodiment, the method further includes: depositing a metal layer on top of the metal oxide semiconductor layer; and patterning the metal layer to form a source contact and a drain contact, wherein the patterned metal layer comprises: dry etching a metal layer; and a patterned metal oxide semiconductor layer thereafter. The method may further comprise additional steps such as depositing a passivation layer (such as a layer comprising hafnium oxide, tantalum nitride, and/or aluminum oxide) and/or annealing.

In a method according to a specific example, the patterned metal oxide semiconductor layer is performed (by dry etching) after patterning the metal layer on top of the metal oxide semiconductor layer, that is, defining the source contact and After the bungee contact.

An example of a process flow for fabricating a metal oxide semiconductor thin film transistor according to one specific example is schematically illustrated in FIG. 1 and further illustrated in FIG. Depositing a gate metal layer or a metal stack (such as a Mo layer, a Ti layer, a Cr layer, or a Cu layer of about 30 nm to 300 nm thick, or a Ti/Mo stack or a Mo/Al/Mo stack) on the electrically insulating substrate 10 (process) 1) Thereafter, a gate metal layer or a metal stack (process 2) is patterned by photolithography and wet or dry etching to form a gate electrode 11. A gate dielectric layer 12 (process 3) is then deposited, such as a hafnium oxide layer, a tantalum nitride layer, or an aluminum oxide layer, or any other suitable dielectric layer or layer stack known to those skilled in the art. The resulting structure is illustrated in Figure 2(a). The substrate can be a rigid substrate, a flexible substrate, or an extended substrate. When processed on a flexible or extended substrate, the substrate can be provided on a (temporary) rigid carrier during processing.

A via (not illustrated) may be formed in the gate dielectric layer to contact the gate. Next, the metal oxide semiconductor layer 13 is deposited (process 4) on top of the gate dielectric layer 12 (such as an amorphous IGZO (indium gallium zinc oxide) layer) (Fig. 2(b)). However, the present invention is not limited thereto, and other metal oxide semiconductor layers may be used. A preferred metal oxide semiconductor can be, for example, InZnO, HfInZnO, SiInZnO, ZnO, CuO or SnO. The deposited metal oxide semiconductor layer may, for example, comprise DC or RF sputtering or evaporation. The thickness of the semiconductor layer 13 can range, for example, between about 10 nm and 80 nm.

In the next process, a metal layer 14 or a metal stack is deposited (process 5) on the metal oxide semiconductor layer 13 by evaporation or sputtering, for example (Fig. 2(c)). The metal layer or metal stack may, for example, comprise Mo and may, for example, have a thickness ranging between about 50 nm and 300 nm. For example, a Mo/Al/Mo stack, a Mo/Au stack, a Mo/Ti stack, a Mo/Ti/Al/Mo stack, or a Mo/ITO stack may be used, and the present invention is not limited thereto. The metal layer or metal stack is patterned by lithography and dry (plasma) etching to form source contact 141 and drain contact 142 (process 6), as illustrated in Figure 2(d). The channel length can range, for example, between 2 microns and 100 microns.

After etching the metal layer to form the source contact and the drain contact, the metal oxide semiconductor layer 13 is patterned by lithography and wet or dry etching (process 7) (FIG. 2(e)) to form The active layer 131 of the transistor.

Next, a passivation layer (such as a germanium oxide, tantalum nitride or aluminum oxide layer of about 50 nm to 300 nm thick) is deposited by sputtering, ALD or CVD (process 8) and patterned using plasma etching or wet etching (process) 9). Finally, the structure is annealed, for example, in a nitrogen atmosphere or air at a temperature ranging between about 50 ° C and 175 ° C (Process 10).

When a thin film transistor circuit is fabricated according to a specific example, the capacitor formed in this circuit further includes a metal oxide semiconductor layer in addition to the dielectric layer between the metal layers.

A thin film transistor was fabricated according to the process flow of FIG. 1 and FIG. On the electrically insulating substrate, a patterned Mo gate (having a thickness of about 100 nm) is provided. Next, a 100 nm thick SiN gate dielectric layer was deposited by CVD. In the next process, an a-IGZO layer (In:Ga:Zn = 1:1:1 atomic %, thickness of about 20 nm) was deposited by RF/DC sputtering in an O ₂ environment. Mo source provides a DC sputtering and then by using a dry etching process (SF ₆ + O ₂ plasma) and patterned on the top layer of a-IGZO electrode - drain terminals (thickness of about 100nm). In the following process, the active region (patterned a-IGZO layer) is defined by photolithography of the metal oxide layer and wet etching. Finally, a passivation layer (about 100 nm SiO _x ) was sputtered and then the transistor was annealed at 150 ° C for about 1 hour in an N ₂ atmosphere.

The transistor characteristics measured for a transistor having a channel length of about 10 microns are shown in FIG. The transistor has a high mobility (about 14.06 cm ² /Vs), a low sub-preventive slope (about 0.24 V / decimal), low hysteresis, I _on /I _off greater than 10 ⁸ and V _TH near zero ( About 0.5V).

For reference, a GIZO thin film transistor is fabricated without using an etch stop layer, but following a different process flow, wherein metal oxide semiconductor patterning is performed prior to metal deposition rather than after source and drain metal patterning. And etching. As an additional reference, a transistor is fabricated in which a source contact and a drain contact are formed by means of a lift-off process which is not suitable for increasing the scale due to yield problems. The transistor characteristics of such reference transistors are shown in FIG. A transistor fabricated using a metal oxide semiconductor etch without an etch stop layer and before metal deposition ("DE Mo" in Figure 3) has a significantly low I _ON /I _OFF ratio, a high sub-slope slope, and a large hysteresis Sex. This may be related to the negative effects of the plasma for source and drain etching on the GIZO layer, and more specifically, the uneven distribution of the plasma on the wafer surface due to the distribution. Semi-conductive channel area.

In the method according to the preferred embodiment, the metal oxide semiconductor layer is unpatterned while etching the source and the drain. Therefore, the plasma can be more uniformly distributed over the entire substrate, resulting in a decrease in local plasma unevenness on the metal oxide semiconductor layer and/or a reduction in local plasma charging effect.

A working display is fabricated that includes a thin film GIZO transistor array for selecting and driving a pixel array. The GIZO transistor has a channel length of about 5 microns and is fabricated according to the method of one specific example. A transistor array is fabricated on a substrate of about 6 inches. Figure 5 shows the measured transmission characteristics of five transistors from the array, one transistor being located at the center of the substrate and the other four transistors being located at opposite edges of the substrate. The results show a good uniformity of the crystal characteristics on the substrate.

Other experimental results are described below.

A test apparatus was implemented on a thermally grown SiO ₂ (120 nm) gate dielectric on top of a highly doped Si (common gate) substrate. The active layer was deposited by DC sputtering containing 6% O ₂ in argon (Ar), which was a 15 nm thick a-IGZO (In:Ga:Zn=1:1:1) film. The thickness and O ₂ /Ar ratio are optimized to achieve the desired TFT performance at low processing temperatures. In addition, a 100 nm thick Mo source and drain (S/D) junction was formed by PVD and patterned by SF ₆ /O ₂ dry etching chemistry. After the S/D formation, the active layer was patterned by a wet etch procedure using an oxalic acid solution. On top of the active layer, a 100 nm SiO ₂ passivation layer was deposited by reactive pulsed DC PVD.

Parameter analyzer measured the electrical characteristics of the individual TFT N ₂ in an inert environment.

By reversing the processing sequence of a-IGZO patterning and S/D contact patterning relative to prior art methods, isolated islands of a-IGZO are avoided in the method of the present invention, thereby suppressing charge during plasma etching Local accumulation. By modifying the standard BCE process flow in this way, major TFT parameters such as hysteresis, mobility, and overall sub-slope slope show significant improvements. The IV characteristics of three series of test TFTs are depicted in FIG. 6, which are respectively subjected to a conventional separation process, a standard BCE process (S/D etching after semiconductor patterning), and a mode according to the present invention. Modify the BCE process (S/D etching before semiconductor patterning) fabrication. All test devices were implemented on a thermally grown SiO ₂ (120 nm) gate dielectric on top of a highly doped Si (common gate) substrate. The a-IGZO test apparatus fabricated using the modified BCE process according to the aspect of the present invention clearly showed only a slight amount of hysteresis between the forward gate voltage scan and the reverse gate voltage scan in the transmission curve. In fact, the results are very similar to those obtained using a device based on S/D. Table 1 gives an overview of the main performance parameters for three different processes.

The transmission characteristics of TFTs processed by standard BCE show a lower mobility of only 5cm ² /(Vs) to 12cm ² /(Vs), a subcritical swing of 0.60V/decimal drop, and a negative threshold of -0.5V Voltage. In addition, the hysteresis in the transmission curve is significantly increased relative to the other two processes. The latter indicates that more damage is caused during the dry etching of the S/D metal layer on top of the small island of a-IGZO. This damage is due to localized charge accumulation due to plasma exposure during the dry etch process in the isolated active region. In summary, it was observed that the modified BCE process resulted in a significant improvement in device characteristics.

It has been further confirmed that regardless of whether the a-IGZO layer is under the metal line, the parasitic capacitance of the signal line may be potentially affected. This is especially important for (TFT-) displays and circuit applications. To confirm this effect, two capacitors were compared corresponding to a gate dielectric having a-IGZO and no a-IGZO. Only a 5% change in total capacitance was measured, as shown in Figure 7. In addition, the effect of bias stress on the electrical performance of the TFT was investigated. Corresponding to the applied in the positive and reverse directions +/- 1.0MV / cm electric field of the gate in the dark at room temperature, the stress duration time ¹⁰⁴ seconds. In the case of a positive gate bias, a threshold voltage shift of 0.9V is observed corresponding to the fully on condition (V _DS = 12V and V _GS = 12V). In the case of a negative bias (V _DS =0 V and V _GS = -12 V), a threshold voltage shift of 1.0 V was observed. Figures 8(a) and 8(b) show the variation of the transmission characteristics with the bias stress time of both the positive gate bias and the negative gate bias. Figure 8(c) gives a comparison of _VTH shifts as a function of stress time in both the positive and negative directions.

Finally, a modified BCE process flow in accordance with a specific embodiment of the present invention is integrated on a PEN foil having 200 nm ICP-CVD SiN as the gate dielectric and 100 nm MoCr as the gate metallization.

A foil substrate embodied in a 25 [mu]m thick thermally stabilized PEN foil from a commercial supplier was laminated to a 150 mm rigid glass carrier. The carrier provides support during the entire manufacturing process of the digital circuitry and display. In the first step, a 200 nm SiN barrier layer was deposited on top of the PEN foil by inductively coupled plasma chemical vapor deposition (ICP-CVD) at 150 °C. The gate metallization consists of a 100 nm thick layer of MoCr alloy formed by physical vapor deposition (PVD) followed by a wet etch patterning process. Next, a 200 nm thick SiN gate dielectric layer was deposited by ICP-CVD at 150 °C. TFTs used as building blocks in circuits and in display backplanes require low gate leakage current and high breakdown electric field. Achieving good dielectric properties using conventional CVD deposition at low temperatures (<200 °C) required for processing on PEN foils is a major challenge. Therefore, the processing conditions of the SiN dielectric layer deposited by ICP-CVD at 150 ° C are optimized. A breakdown electric field of ~8 MV/cm was reached, and a leakage of 1.3e ^-6 mA/cm ² at 2 MV/cm (dielectric constant ε = 7.1) was achieved.

Subsequently, an active layer was deposited by DC sputtering containing 6% O ₂ in argon (Ar), which was a 15 nm thick a-IGZO (In:Ga:Zn=1:1:1) film. The thickness and O ₂ /Ar ratio are optimized to achieve the desired TFT performance at low processing temperatures. In addition, a 100 nm thick Mo source and drain (S/D) junction was formed by PVD and patterned by SF ₆ /O ₂ dry etching chemistry. After the S/D formation, the active layer was patterned by a wet etch procedure using an oxalic acid solution. On top of the active layer, a 100 nm SiO ₂ passivation layer was deposited by reactive pulsed DC PVD. The transmission characteristics and output characteristics of the obtained TFT (W/L = 55/5 μm/μm) are shown in FIG. TFT display 12cm ² / (Vs) to 15cm ² / (Vs) of the linear mobility (μ), - 1.0V of V _TH, the alkylene ¹⁰⁸ I _{ON / OFF} ratio and 0.3V / decimal swing of the threshold . In Figure 9(c), the V _ON and I _ON spreads of nine measured TFTs are shown across a 6-inch wafer containing PEN foil. The dispersion of V _ON and I _ON at V _D =10 V and V _G =20 V is less than 5%.

The above description details some specific examples of the invention. However, it should be understood that the present invention may be embodied in various forms, no matter how the foregoing is presented in detail herein. It should be noted that the specific terms used in describing certain features or aspects of the invention are not to be construed as a limitation that the term is to be re-defined herein, and is limited to any of the features or aspects of the invention that are associated with the term. Specific characteristics.

While the above-described embodiments have been shown, described and illustrated in the present invention, the invention may be Various forms, details and details of the process are omitted, replaced and changed.

1‧‧‧ gate metal deposition

2‧‧‧gate patterning/etching

3‧‧‧ gate dielectric deposition

4‧‧‧ Metal oxide semiconductor layer deposition

5‧‧‧ Source and Deuterium Metal Deposition

6‧‧‧Source and drain metal patterning/etching

7‧‧‧Metal Oxide Semiconductor Patterning/Etching

8‧‧‧ Passivation layer deposition

9‧‧‧ Passivation layer patterning/etching

10‧‧‧ Annealing

Claims (11)

A method for fabricating a bottom gate contact type metal oxide semiconductor thin film transistor, the method comprising: forming a gate electrode on a substrate; providing a gate dielectric layer covering the gate electrode; and depositing a metal oxide semiconductor layer Depositing a metal layer or a metal layer on top of the metal oxide semiconductor layer; patterning the metal layer or the metal layer stack to form a source contact and a drain contact, wherein the patterning The metal layer or metal layer stack comprises dry etching the metal layer or metal layer stack; and thereafter patterning the metal oxide semiconductor layer. The method of claim 1, further comprising depositing a passivation layer and performing an annealing process. The method of claim 1, wherein the metal oxide semiconductor layer comprises an amorphous IGZO (indium gallium zinc oxide) layer or an amorphous IGZO (indium gallium zinc oxide) layer. The method of claim 1, wherein the metal oxide semiconductor layer comprises any one or any combination of an InZnO layer, an HfInZnO layer, a SiInZnO layer, a ZnO layer, a CuO layer or a SnO layer, or an InZnO layer, Any one or any combination of an HfInZnO layer, a SiInZnO layer, a ZnO layer, a CuO layer, or a SnO layer. The method of claim 1, wherein the metal oxide semiconductor layer has a thickness of between 10 nm and 80 nm. The method of claim 1, wherein the metal layer comprises or consists of Mo, or wherein the metal layer stack comprises a Mo/Al/Mo stack, a Mo/Au stack, a Mo/Ti stack, a Mo/Ti/Al /Mo stack or Mo/ITO stack or consist of Mo/Al/Mo stack, Mo/Au stack, Mo/Ti stack, Mo/Ti/Al/Mo stack or Mo/ITO stack. The method of claim 1, wherein the metal layer or the metal layer stack has a thickness ranging between about 50 nm and 300 nm. The method of claim 1, wherein patterning the metal oxide semiconductor layer occurs on the metal layer or metal layer stack patterned on top of the metal oxide semiconductor layer to define the source contact and the germanium After the pole contact. The method of claim 1, wherein the substrate comprises a polyethylene naphthalate foil. The method of claim 1, further comprising forming a via in the gate dielectric layer to contact the gate. Use of the method of claim 1 for the manufacture of a transistor having a channel length of from about 2 microns to 5 microns.