KR102099860B1 - A method for fabricating a thin film transistor - Google Patents

Abstract

A method of fabricating a bottom-gate top-contact metal oxide semiconductor thin film transistor, comprising: forming a gate electrode on a substrate; Providing a gate dielectric layer covering the gate electrode; Depositing a metal oxide semiconductor layer on the gate dielectric layer; Depositing a metal layer over the metal oxide semiconductor layer; Patterning the metal layer to form source and drain contacts, wherein patterning the metal layer includes dry etching of the metal layer; And thereafter, patterning the metal oxide semiconductor layer.

Description

Manufacturing method of thin film transistor {A METHOD FOR FABRICATING A THIN FILM TRANSISTOR}

The present disclosure relates to a method for fabricating a metal oxide semiconductor thin film transistor, specifically a method for fabricating a metal oxide semiconductor lower-gate upper-contact thin film transistor, and a thin film transistor obtained by such a method.

Metal oxide semiconductors are potentially applicable in thin film electronics, such as large area displays and circuits, because they can achieve excellent electrical properties at low processing temperatures. For example, a thin film transistor (TFT) using amorphous gallium-indium-zinc-oxide (a-GIZO) as the active layer has already been specified. The implemented good mobility (μ) and good threshold voltage (V _TH ) control are important parameters for successfully replacing a conventional amorphous Si TFT backplane with an amorphous metal oxide semiconductor TFT backplane in a display.

In a method of fabricating a bottom-gate top-contact (BGTC) metal oxide semiconductor thin film transistor, an etch stop layer is often used to protect the metal oxide semiconductor layer from plasma defects during further processing. In this process, a gate and gate dielectric layer is provided on the substrate, and then a metal oxide semiconductor layer is deposited and patterned on the gate dielectric layer. Then, after the etch stop layer is deposited on the metal oxide semiconductor layer, the etch stop layer is patterned. The metal layer is then deposited and patterned by dry plasma etching to form source and drain contacts. The etch stop layer protects the underlying metal oxide semiconductor layer from defects that may be caused by the metal etch process during patterning defining source and drain contacts.

In another process flow, by using a wet etching process to pattern the metal layer on top of the metal oxide semiconductor layer, the etch stop layer may not be used. However, it is difficult to find an etchant that provides good etch selectivity between the metal layer and the metal oxide semiconductor layer, which limits the combination of materials that can be used.

One aspect of the invention relates to a method of fabricating an excellent metal oxide semiconductor thin film transistor in which patterning of source and drain contacts on the top of the metal oxide semiconductor layer is performed by dry etching, and an etch stop layer is not required.

One aspect of the invention includes forming a gate electrode on a substrate, providing a gate dielectric layer covering the gate electrode, and depositing a metal oxide semiconductor layer on the gate dielectric layer, the bottom-gate top-contact. It relates to a method of manufacturing a metal oxide semiconductor thin film transistor. The method also includes depositing a metal layer or metal layer stack over the metal oxide semiconductor layer, and patterning the metal layer or metal layer stack to form source and drain contacts of the thin film transistor-patterning the metal layer or metal layer stack is Dry etching of the metal layer or metal layer stack; And then, for example, patterning the metal oxide semiconductor layer. The method may further include additional processing steps, such as depositing a passivation layer and / or annealing. The annealing step is preferably suitable for handling damage by the plasma process and / or obtaining good passivation during device fabrication.

The metal oxide semiconductor layer may be an amorphous IGZO (indium gallium zinc oxide) layer. However, the present disclosure is not limited to these, and other metal oxide semiconductor layers may be, for example, InZnO, HfInZnO, SiInZnO, ZnO, CuO or SnO layers.

In the method according to one aspect of the invention, the step of patterning the metal oxide semiconductor layer is performed after patterning the metal layer or the metal layer stack over the metal oxide semiconductor layer, that is, after defining the source and drain contacts. The risk of damaging the metal oxide semiconductor layer during the dry etching of the metal, for example, in the channel region of the thin film transistor, is a process of patterning the metal oxide semiconductor layer before patterning the metal layer or the metal layer stack by dry (plasma) etching Compared to the procedure, there is an advantage that can be significantly reduced by performing the above series of process steps.

The method according to one aspect of the invention has the advantage that the number of masks required is reduced, as a result the number of process steps is reduced, and manufacturing costs are reduced, since it is not necessary to provide an etch stop layer and perform patterning.

In the method according to one aspect of the invention, the transistor size, specifically the channel length, has an advantage that can be reduced compared to a method using an etch stop layer. The size of the transistor, for example, depends on the substrate size and the lithography tool used, but the channel length of the transistor produced by the method according to one aspect of the invention is on the order of about 2 μm to 5 μm, while the etch stop layer The lower limit of the channel length produced by the conventional method using is about 5 μm to 20 μm. In general, the channel length can be reduced by about 3 times compared to the thin film transistor manufactured by the etch stop layer. Therefore, when using the method according to an aspect of the invention in the manufacturing process of a display, a more compact pixel can be formed, and a display having an improved resolution can be manufactured.

The method according to one aspect of the invention, excellent field effect mobility (eg, about 2 cm ² / Vs to 100 cm ² / Vs), low I _OFF Advantages that enable the fabrication of metal oxide semiconductor thin film transistors with excellent characteristics such as current (eg, less than about 10 pA) and low sub-threshold slope (eg, less than about 1 V / decade) have.

The method according to the aspect of the invention has the advantage of being compatible with existing production lines used for mass production of amorphous silicon thin film transistors and circuits. Specifically, the manufacturing steps used in accordance with aspects of the present invention can be performed in an existing manufacturing line of amorphous silicon TFTs. This means that a metal oxide TFT can be produced in the production line of an existing amorphous silicon TFT by the method of the embodiment of the present invention.

In the method according to one aspect of the invention, there is an advantage that can be used to fabricate an array of metal oxide semiconductor thin film transistors, for example to select or drive pixels of a display.

The specific purpose and advantages of some aspects are described above. Among them, it is understood that all such objects or advantages are achieved in accordance with certain embodiments of the present disclosure. Thus, for example, one of ordinary skill in the art recognizes that, as taught or suggested herein, other objectives or advantages are not necessarily achieved, but implemented or performed in a way that achieves or optimizes one advantage or group taught herein. something to do. Also, it is understood that this summary is an example and is not intended to limit the scope of the present disclosure. The disclosure of the operating method and instrument along with its features and advantages can be understood with reference to the detailed description in conjunction with the accompanying drawings.

1 schematically depicts a process sequence according to one embodiment of the present disclosure.
2 (a) -2 (e) show a method according to one embodiment of the present disclosure.
FIG. 3 shows the measured transition characteristics of a GIZO thin film transistor (DE Mo) without an etch stop layer, where the source and drain contacts are deposited after the GIZO is patterned, and patterned by dry etching, the source and by metal lift-off It shows the measured transition characteristics of the GIZO thin film transistor (LO Mo) in which the drain contact is formed.
4 shows measured transition characteristics of a GIZO thin film transistor fabricated in accordance with one embodiment of the method of the present invention.
5 shows the transition characteristics of a GIZO thin film transistor measured at different locations in an array fabricated on a 6 inch substrate according to one embodiment of the present invention.
Figure 6 is a standard BCE (S / D etching after IGZ etching), BCE process according to aspects of the present invention (S / D etching before IGZ etching) and three a-IGZO TFTs each processed by a conventional lift-off process The comparison result of the transition characteristic (V _GS -I _DS ) is shown.
7 shows the capacitance comparison of MIS (with a-IGZO) and MIM (without a-IGZO) in the region of 500 x 500 um ² showing less than 5% difference.
Figure 8 (a) V _GS = + 12V and V _DS = + 12V, (b) V _GS = -12 V and V _DS = 0 V, the transition characteristics of a-IGZO TFT ((W / L = 70/10 μm / μm) as a function of stress time (V _GS- I _DS ), (c) V _TH shift of a-IGZO TFTs with stress time in both positive and negative directions.
9 shows (a) transition (V _GS -I _DS ) and (b) output (V _DS -I _DS ) characteristics for a driving TFT having W / L = 55/5 μm / μm, (c) 150 mm PEN The transition curve (V _DS = 10 V) of 9 TFTs measured on a foil substrate is shown.
In different drawings, the same reference numbers refer to the same or similar elements.

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure and how it is performed in specific embodiments. However, the present disclosure may be performed without these specific details. In other instances, well-known methods, procedures, and techniques are not described in detail so as not to obscure the present disclosure. The present disclosure may be described with respect to specific embodiments with reference to specific drawings, but the present disclosure is not limited thereto. The included and described drawings are schematic and do not limit the scope of the present disclosure. It should be noted that in the drawings, the size of some elements may be exaggerated and, therefore, not drawn to the exact scale for illustration purposes.

In addition, in the detailed description, "first, second, third", etc. are used to distinguish similar elements, and do not necessarily describe the order of temporal order, spatial order, order, or any other method. It is understood that the terms so used may be interchanged under appropriate circumstances, and embodiments of the present disclosure described herein may operate in a different order than the order described or described herein.

In addition, in the detailed description, "upper", "lower", "upper", "lower", etc. are used to describe, and do not necessarily describe relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances, and embodiments of the present disclosure described herein are operable in other directions than those described or described herein.

It should be noted that “comprising” is not to be construed as limiting to the means listed thereafter, and does not exclude other elements or steps. The term is interpreted to indicate the presence of the described feature, sign, step, or component, but does not exclude the presence or addition of one or more other features, sign, step, or component, or group. Thus, the scope of "apparatus comprising means A and B" is not limited to devices consisting solely of components A and B.

Certain embodiments include forming a gate electrode on a substrate, providing a gate dielectric layer covering the gate electrode, and depositing a metal oxide semiconductor layer on the gate dielectric layer, the bottom-gate top-contact metal. Provided is a method of manufacturing an oxide semiconductor thin film transistor. In one embodiment, the method further comprises depositing a metal layer or stack of metal layers over the metal oxide semiconductor layer; And patterning the metal layer to form source and drain contacts, wherein patterning the metal layer includes a dry etching step of the metal layer; And then patterning the metal oxide semiconductor layer. The method may further include additional processing steps, such as depositing a passivation layer (eg, silicon oxide, silicon nitride and / or aluminum oxide) and / or annealing.

In the method according to one embodiment, after the metal layer over the metal oxide semiconductor layer is patterned by dry etching, that is, after defining source and drain contacts, the step of patterning the metal oxide semiconductor layer is performed.

An example of a process flow for fabricating a metal oxide semiconductor thin film transistor according to one embodiment is schematically illustrated in FIG. 1 and illustrated in FIG. 2. After depositing a gate metal layer or metal stack on the electrically insulating substrate 10, for example, a Mo, Ti, Cr or Cu layer of about 30 nm to 300 nm thickness or a Ti / Mo or Mo / Al / Mo stack ( Step 1), the gate metal layer or metal stack is patterned by photolithography or by wet or dry etching to form the gate electrode 11 (step 2). Next, the gate dielectric layer 12 is deposited with, for example, a silicon oxide layer, a silicon nitride layer or an aluminum oxide layer or any other suitable dielectric layer or layer stack known to those skilled in the art (step 3). The obtained structure is shown in Fig. 2 (a). The substrate can be a rigid substrate, a flexible substrate, or a stretched substrate. When processed on a flexible or stretched substrate, the substrate may be provided on a (temporary) rigid carrier during processing.

Vias may be formed in the gate dielectric layer (not shown) to be coupled to the gate. Next, a metal oxide semiconductor layer 13, for example, amorphous IGZO (indium gallium zinc oxide) is deposited on top of the gate dielectric layer 12 (Fig. 2 (b)) (step 4). However, the present disclosure is not limited to these, and other metal oxide semiconductor layers may be used. Preferred metal oxide semiconductors can be, for example, InZnO, HfInZnO, SiInZnO, ZnO, CuO or SnO. Depositing a metal oxide semiconductor layer may include, for example, DC or RF sputtering or evaporation. The thickness of the semiconductor layer 13 may be, for example, in the range of about 10 nm to 80 nm.

In the following process, a metal layer 14 or a metal stack is deposited on the metal oxide semiconductor layer 13, for example, by evaporation or sputtering (Fig. 2 (c)) (process 5). The metal layer or metal stack includes, for example, Mo, and for example, the thickness may be about 50 nm to 300 nm. For example, a Mo / Al / Mo stack, a Mo / Au stack, a Mo / Ti stack, a Mo / Ti / Al / Mo stack or a Mo / ITO stack can be used, but the present disclosure is not limited to these. To form the source contact 141 and the drain contact 142, the metal layer or metal stack is patterned by lithography and dry (plasma) etching, as shown in Fig. 2 (d) (step 6). The channel length can be, for example, 2 μm to 100 μm.

After forming the source and drain contacts by etching the metal layer, to form the active layer 131 of the transistor, the metal oxide semiconductor layer 13 is patterned by lithography and wet or dry etching (Fig. 2 (e)) ( Process 7).

Next, a passivation layer such as, for example, a silicon oxide, silicon nitride or aluminum oxide layer of about 50 nm to 300 nm thickness is deposited by sputtering, ALD or CVD (step 8), and plasma etching or wet etching is performed. It is patterned using (Step 9). Finally, the structure is annealed, for example, in a nitrogen atmosphere or air at about 50 ° C to about 175 ° C (step 10).

When manufacturing a thin film transistor circuit according to an embodiment, the capacitor formed in the circuit includes a metal oxide semiconductor layer in addition to a dielectric layer between the metal layers.

Thin film transistors were fabricated according to the process flows of FIGS. On the electrically insulating substrate, a patterned Mo gate (about 100 nm thick) was provided. Next, a SiN gate dielectric layer about 100 nm thick was deposited by CVD. In the following process, a-IGZO layer (In: Ga: Zn = 1: 1: 1 atomic%, thickness about 20 nm) was deposited by RF / DC sputtering in an O ₂ environment. The Mo source-drain contact (about 100 nm thick) was applied on top of the a-IGZO layer using a dry etching process (SF ₆ + O ₂ plasma) and by DC sputtering and patterning. In a later process, the active region was defined by photolithography and wet etching of the metal oxide layer (a-IGZO layer was patterned). Finally, the passivation layer was sputtered about 100 nm SiO _x , and then the transistor was annealed at 150 ° C. for about 1 hour in an N ₂ environment.

The measured transistor characteristics of a transistor with a channel length of about 10 μm are shown in FIG. 4. Transistors have high mobility (approximately 14.06 cm ² / Vs), low sub-threshold slope (approximately 0.24 V / decade), low hysteresis, greater than 10 ⁸ I _on / I _off and V _TH close to 0 (approximately 0.5 V) Have

For reference, GIZO thin film transistors are fabricated without using an etch stop layer, but metal oxide semiconductor patterning and etching were performed before metal deposition instead of after source and drain metal patterning, following the following different process flow. For reference, transistors in which source and drain contacts are manufactured by a lift-off process were fabricated (this is not suitable for scale expansion due to yield problems). The transistor characteristics of this reference transistor are shown in FIG. 3. A transistor fabricated by performing metal oxide semiconductor etching without an etch stop layer prior to metal deposition ('DE Mo' in FIG. 3) clearly has a low I _ON / I _OFF rate, a high sub-threshold slope, and a large hysteresis. This may be related to the negative effect of the plasma used for source and drain etching on the GIZO layer, specifically the non-uniform distribution of plasma over the wafer surface due to the distributed semiconductor channel region.

In the method according to the preferred embodiment, the metal oxide semiconductor layer has not yet been patterned when the source and drain are etched. Thus, the plasma is distributed more uniformly over the entire substrate, leading to reduced local plasma non-uniformity and / or reduced local plasma implantation effect on the metal oxide semiconductor layer.

The operational display was built to include an array of thin film GIZO transistors to select and drive an array of pixels. The GIZO transistor has a channel length of about 5 μm and was fabricated by a method according to one embodiment. The array of transistors was fabricated on about a 6 inch substrate. 5 shows the measured transition characteristics of five transistors from this array, one transistor located at the center of the substrate, and the other four transistors located at the facing edges of the substrate. As a result, it exhibits excellent uniformity characteristics of the transistor on the substrate.

Another experimental result is described below. The test setup was implemented on a thermally grown SiO ₂ (120 nm) gate dielectric on top of a very doped Si (typical gate) substrate. The active layer, a 15 nm thick a-IGZO (In: Ga: Zn = 1: 1: 1) film, was deposited by DC sputtering with 6% O ₂ under argon (Ar). The thickness and O ₂ / Ar ratio were optimized to achieve desirable TFT performance at low processing temperatures. In addition, 100 nm thick Mo source and drain (S / D) contacts are formed by PVD and SF ₆ / O ₂ It was patterned by dry etching chemicals. After S / D formation, the active layer was patterned by wet-etching procedure with oxalic acid solution. On top of the active layer, a 100 nm SiO ₂ passivation layer was deposited by reaction pulse DC PVD.

The electrical properties of the industrial TFT were measured using a parameter analyzer in an inert N ₂ environment.

Compared to the prior art, by changing the order of a-IGZO patterning and S / D contact patterning, the occurrence of isolated islands of a-IGZO in the method of the present invention is prevented, and local accumulation of charge during plasma etching is suppressed. . By changing the standard BCE process flow in this way, significant TFT parameters are exhibited, such as hysteresis, mobility, and overall sub-threshold slope.

Three series of TFTs fabricated by conventional lift-off flow, standard BCE flow (S / D etching after semiconductor patterning), and BCE flow modified according to aspects of the present invention (S / D etching before semiconductor patterning) The IV characteristics of the test are shown in FIG. 6. All test devices were implemented on a thermally grown SiO ₂ (120 nm) gate dielectric on top of a highly doped Si (typical gate) substrate. The a-IGZO test apparatus fabricated with a BCE flow modified in accordance with aspects of the present invention clearly exhibited negligible hysteresis in the transition curve between the front gate voltage sweep and the rear gate voltage sweep. The actual results were very similar to those obtained with a lift-off S / D based device. Table 1 gives the results of the main performance parameters for three different flows.

TFT  parameter lift- off  Device S / D
a- IGZO  S / D after etching device
a- IGZO  S / D before etching device
? _{E range}  (cm ² /(V.s) 12-15 5-12 12-15 SS ^-One
(V / decade ) 0.3-04 0.3-0.8 0.3-04 Hysteresis  (V) <0.5 <1.0 <0.5

The transition characteristics of the standard BCE-treated TFT exhibited low mobility 5-12 cm ² / (Vs), degraded sub-threshold swing 0.60V / decade, and negative threshold voltage -0.5V. In addition, the hysteresis in the transition curve increased significantly compared to the other two flows. The latter indicates that many defects occur during the dry etching of the S / D metal layer on the top of the small island of a-IGZO. This damage is due to the local accumulation of charges by plasma exposure during the dry etch process in a separate active region. Overall, it has been observed that the modified BCE flow leads to significant improvements in device characteristics.

It has been demonstrated whether the a-IGZO layer present under the metal line could potentially affect the parasitic capacitance of the signal line. This is particularly important for (TFT) display and circuit applications. To demonstrate this effect, two capacitors corresponding to the gate dielectric were compared with or without a-IGZO. As shown in Figure 7, only 5% of the total capacitance change was measured. In addition, the effect of bias stress on the electrical performance of the TFT was investigated. A gate field corresponding to +/- 1.0 MV / cm in the positive and negative directions was applied in the dark at room temperature for a stress time of 10 ⁴ seconds. In the case of a positive gate bias corresponding to a fully-on condiction (V _DS = 12 V and V _GS = 12 V), a threshold voltage shift of 0.9 V was observed. In the case of negative bias (V _DS = 0 V and V _GS = -12 V), a threshold voltage shift of 1.0 V was observed. 8 (a) and 8 (b) show the change in transition properties as a function of bias stress time for positive and negative gate bias. Figure 8 (c) provides a V _TH shift comparison as a function of stress time, in both positive and negative directions.

Finally, a BCE process flow modified according to an embodiment of the present invention was incorporated on a PEN foil with 200 nm ICP-CVD SiN as the gate dielectric and 100 nm MoCr as the gate metallization.

The substrate foil was implemented as a 25 μm thick heat stabilized PEN foil from a commercial supplier, and the substrate foil was laminated on a 150 mm rigid glass carrier. The carrier serves as a support during the entire manufacturing process of digital circuits and displays. In the first step, a 200 nm SiN barrier layer was deposited on the PEN foil at 150 ° C. by inductively coupled plasma chemical vapor deposition (ICP-CVD). The gate metal is formed by forming a 100 nm thick MoCr alloy layer by physical vapor deposition (PVD), and then performing a wet etching patterning procedure. Next, a 200 nm thick SiN gate dielectric layer was deposited at 150 ° C by ICP-CVD. For low gate leakage currents and high breakage fields, TFTs used as mounting blocks in circuit and display backplanes are required. It is difficult to achieve good dielectric properties by conventional CVD deposition at low temperatures (below 200 ° C.) required for processing on PEN foils. Therefore, the processing conditions of the SiN dielectric layer deposited by ICP-CVD at 150 ° C were optimized. At 2 MV / cm, the leakage current was 1.3 e- ⁶ mA / cm ² , and a breakage field of ˜8 MV / cm was obtained (permittivity ε = 7.1).

Next, a 15 nm thick a-IGZO (In: Ga: Zn = 1: 1: 1) film, which is an active layer, was deposited by DC-sputtering containing 6% O ₂ in argon. The thickness and O ₂ / Ar ratio were optimized to obtain desirable TFT performance at low processing temperatures. In addition, 100 nm thick Mo source and drain (S / D) contacts are formed by PVD and SF ₆ / O ₂ It was patterned with a dry etching chemical. After S / D formation, the active layer was patterned by a wet etching procedure using an oxalic acid solution. On top of the active layer, a 100 nm SiO ₂ passivation layer was deposited by reactive pulse-DC PVD.

The transition and output characteristics of the obtained TFT (W / L = 55/5 µm / µm) are shown in FIG. 9. The TFT displays linear mobility (μ) 12-15cm ² / (Vs), -1.0V V _TH , 10 ⁸ I _{ON / OFF} rate and 0.3V / decade sub-threshold swing. In Fig. 9 (c), the diffused V _ON and I _ON of the nine measured TFTs appear on the whole of a 6 inch wafer containing PEN foil. The diffusion of V _ON and I _ON at V _D = 10V and V _G = 20V is less than 5%.

The above description describes specific embodiments of the present disclosure. However, even if the above disclosure is described in detail, it can be seen that the present disclosure can be implemented in various ways. When using certain terms to describe certain features or aspects of the present disclosure, it is not intended that the terms are redefined herein so as not to be limited to include any specific features of the features or aspects of the present disclosure related to the term. Be careful.

While the above detailed description marks, describes and describes new features of the present invention that apply to various embodiments, various omissions, substitutions and modifications of the details and forms of the illustrated devices and processes do not depart from the scope of the present invention. It is possible without a person skilled in the art.

Claims (11)

A method of manufacturing a bottom-gate top-contact metal oxide semiconductor thin film transistor,
Forming a gate electrode on the substrate;
Providing a gate dielectric layer covering the gate electrode;
Depositing a metal oxide semiconductor layer on the gate dielectric layer;
Depositing a metal layer or a metal layer stack directly above the metal oxide semiconductor layer;
Patterning the metal layer or metal layer stack to form source and drain contacts-The patterning of the metal layer or metal layer stack is performed by dry etching the metal layer or metal layer stack using plasma uniformly distributed over the entire substrate, thereby localizing the metal layer or metal layer stack. Including reducing plasma non-uniformity and local plasma implantation effect on the metal oxide semiconductor layer; And
Then, patterning the metal oxide semiconductor layer;
A method of manufacturing a bottom-gate top-contact metal oxide semiconductor thin film transistor comprising a.
According to claim 1,
A method of fabricating a bottom-gate top-contact metal oxide semiconductor thin film transistor further comprising depositing a passivation layer and performing an annealing process.
The method according to claim 1 or 2,
The metal oxide semiconductor layer comprises or consists of an amorphous IGZO (indium gallium zinc oxide) layer, a method of manufacturing a bottom-gate top-contact metal oxide semiconductor thin film transistor.
The method according to claim 1 or 2,
The metal oxide semiconductor layer comprises or consisting of any one or any combination of InZnO, HfInZnO, SiInZnO, ZnO, CuO or SnO layers, the method of manufacturing a bottom-gate top-contact metal oxide semiconductor thin film transistor.
The method according to claim 1 or 2,
The metal oxide semiconductor layer has a thickness of 10 nm to 80 nm, a method of manufacturing a bottom-gate top-contact metal oxide semiconductor thin film transistor.
The method according to claim 1 or 2,
The metal layer includes or consists of Mo, or the metal layer stack includes a Mo / Al / Mo stack, a Mo / Au stack, a Mo / Ti stack, a Mo / Ti / Al / Mo stack, or a Mo / ITO stack, or A method of manufacturing a bottom-gate top-contact metal oxide semiconductor thin film transistor made of these.
The method according to claim 1 or 2,
The metal layer or the metal layer stack, the thickness of which is in the range of 50 nm to 300 nm, a method of manufacturing a bottom-gate top-contact metal oxide semiconductor thin film transistor.
The method according to claim 1 or 2,
The step of patterning the metal oxide semiconductor layer is performed after the step of patterning a metal layer or a metal layer stack over the top of the metal oxide semiconductor layer, in order to define the source and drain contacts. Method for manufacturing a metal oxide semiconductor thin film transistor.
The method according to claim 1 or 2,
The substrate comprises a polyethylene naphthalate foil, a method of manufacturing a bottom-gate top-contact metal oxide semiconductor thin film transistor.
The method according to claim 1 or 2,
And forming a via in the gate dielectric layer to contact the gate dielectric layer.
The method according to claim 1 or 2,
A method of fabricating a bottom-gate top-contact metal oxide semiconductor thin film transistor for fabricating a transistor having a channel length of 2 to 5 micrometers.

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