WO2014005841A1

WO2014005841A1 - A method for fabricating a thin film transistor

Info

Publication number: WO2014005841A1
Application number: PCT/EP2013/062767
Authority: WO
Inventors: Manoj NAG; Sören STEUDEL
Original assignee: Imec; Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek (Tno); K.U. Leuven Research And Development
Priority date: 2012-07-03
Filing date: 2013-06-19
Publication date: 2014-01-09
Also published as: TW201405835A; JP2018074178A; JP6498745B2; KR102099860B1; CN104685633B; KR20150028997A; TWI664734B; CN104685633A; JP2015521804A

Abstract

A method for fabricating a bottom-gate top-contact metal oxide semiconductor thin film transistor, the method comprising: - forming a gate electrode on a substrate; - providing a gate dielectric layer covering the gate electrode; - depositing a metal oxide semiconductor layer on the gate dielectric layer; - depositing a metal layer on top of the metal oxide semiconductor layer; - patterning said metal layer to form source and drain contacts, wherein patterning the metal layer comprises dry etching of the metal layer; and thereafter patterning the metal oxide semiconductor layer.

Description

A method for fabricating a thin film transistor- Technical field

The disclosed technology relates to methods for fabricating metal oxide semiconductor thin film transistors, more in particular to methods for fabricating metal oxide semiconductor bottom-gate top-contact thin film transistors, and to thin film transistors thus obtained.

Background art

Metal oxide semiconductors find potential applications in thin film electronics such as large area displays and circuits because of their ability to achieve excellent electrical properties at low processing temperatures. For example, thin film transistors (TFTs) using amorphous gallium-indium-zinc-oxide (a-GIZO) as an active layer have already been demonstrated. Realizing a good mobility (μ) and a good threshold voltage (V_TH) control are important parameters for the successful replacement of the conventional amorphous Si TFT backplanes in displays by amorphous metal oxide semiconductor TFT backplanes.

In a process for fabricating bottom-gate top-contact (BGTC) metal oxide semiconductor thin film transistors, an etch stop layer is often used to protect the metal oxide semiconductor layer from plasma damage during further processing. In such a process, after providing a gate and a gate dielectric layer on a substrate, a metal oxide semiconductor layer is deposited on the gate dielectric layer and patterned. Next an etch stop layer is deposited on top of the metal oxide semiconductor layer, followed by patterning of the etch stop layer. Then a metal layer is deposited and patterned by dry plasma etching to form source and drain contacts. During this patterning for defining the source and drain contacts, the etch stop layer protects the underlying metal oxide semiconductor layer from damage that may be caused by the metal etching process.

In an alternative process flow, the use of an etch stop layer can be avoided by using a wet etching process for patterning the metal layer on top of the metal oxide semiconductor layer. However, it is a challenge to find an etchant that provides a good etching selectivity between the metal layer and the metal oxide semiconductor layer, which limits the material combinations that can be used.

Summary of the disclosure

One inventive aspect relates to a method for fabricating good metal oxide semiconductor thin film transistors wherein patterning of the source and drain contacts on top of the metal oxide semiconductor layer is done by dry etching and wherein there is no need for using an etch stop layer.

One inventive aspects relates to a method for fabricating bottom-gate top- contact metal oxide semiconductor thin film transistors, wherein the method comprises forming a gate electrode on a substrate, providing a gate dielectric layer covering the gate electrode and depositing a metal oxide semiconductor layer on the gate dielectric layer. The method may further comprise: depositing a metal layer or metal layer stack on top of the metal oxide semiconductor layer; and patterning the metal layer or metal layer stack to form source and drain contacts of the thin film transistor, wherein patterning the metal layer or metal layer stack comprises dry etching of the metal layer or metal layer stack; and, thereafter, for instance directly thereafter, patterning the metal oxide semiconductor layer. The method may further comprise additional processing such as depositing a passivation layer and/or annealing. The anneal step is preferably adapted for curing damage that may have been caused by plasma processes during device fabrication and/or for obtaining a good passivation.

The metal oxide semiconductor layer can for example be an amorphous IGZO (indium gallium zinc oxide) layer. However, the present disclosure is not limited thereto, and other metal oxide semiconductor layers can be used such as InZnO, HflnZnO, SilnZnO, ZnO, CuO or SnO layers

In a method according to one inventive aspect, patterning the metal oxide semiconductor layer is done after patterning the metal layer or metal layer stack on top of the metal oxide semiconductor layer, i.e. after defining the source and drain contacts. It is an advantage of using such sequence of process steps that the risk of damaging the metal oxide semiconductor layer, e.g. in the channel region of the thin film transistor, during metal dry etching may be strongly reduced as compared to a process sequence wherein patterning the metal oxide semiconductor layer is done before patterning the metal layer or metal layer stack by dry (plasma) etching.

It is an advantage of a method according to one inventive aspect that there is no need for providing and patterning an etch stop layer, thus reducing the number of masks needed and consequently reducing the number of process steps and reducing the manufacturing cost.

It is an advantage of a method according to one inventive aspect that the transistor size, more in particular the channel length, can be reduced as compared to methods using an etch stop layer. For example, depending on the substrate size and the lithography tools used, transistors with a channel length in the order of about 2 micrometer to 5 micrometer can be fabricated using a method in accordance with one inventive aspect, while in prior art methods using an etch stop layer the lower limit for the channel length is in the order of about 5 micrometer to 20 micrometer. In general, the channel length can be reduced by about a factor of 3 as compared to thin film transistors fabricated with the use of an etch stop layer. Therefore, when using a method according to one inventive aspect in a fabrication process of displays, more compact pixels can be formed and displays with improved resolution can be fabricated.

It is an advantage of a method according to one inventive aspect that it allows fabricating metal oxide semiconductor thin film transistors with good characteristics such as a good field-effect mobility (e.g. in the range between about 2 cm²/Vs and 100 cm²/Vs), a low I₀FF current (e.g. lower than about 10 pA) and a low sub-threshold slope (e.g. lower than about 1 V/decade).

It is an advantage of a method according to one inventive aspect that it is compatible with existing fabrication lines currently used for mass production of amorphous silicon thin film transistors and circuits. More specifically, the fabrication steps used in accordance with aspects of the present invention can be performed in existing manufacturing lines for amorphous silicon TFTs. This implies also that metal oxide TFTs can be produced in existing manufacturing lines for amorphous silicon TFTs, with methods according to embodiments of the present invention. A method according to one inventive aspect can advantageously be used for fabricating arrays of metal oxide semiconductor thin film transistors, e.g. for selecting or driving pixels of a display.

Certain objects and advantages of some inventive aspects have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the disclosure. Thus, for example, those skilled in the art will recognize that the disclosure may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein. Further, it is understood that this summary is merely an example and is not intended to limit the scope of the disclosure. The disclosure, both as to organization and method of operation, together with features and advantages thereof, may best be understood by reference to the following detailed description when read in conjunction with the accompanying drawings.

Brief description of the drawings

Figure 1 schematically illustrates a process sequence in accordance with an embodiment of the present disclosure.

Figures 2(a) to 2(e) illustrate a method in accordance with an embodiment of the present disclosure.

Figure 3 shows measured transfer characteristics of a GIZO thin film transistor with source and drain contacts formed by metal lift-off (LO Mo) and of a GIZO thin film transistor with source and drain contacts deposited and patterned by dry etching after GIZO patterning, without using an etch stop layer (DE Mo).

Figure 4 shows measured transfer characteristics of a GIZO thin film transistor fabricated in accordance with a method in an embodiment of the present invention.

Figure 5 shows transfer characteristics of GIZO thin film transistors measured at different locations of an array fabricated on a 6 inch substrate in accordance with an embodiment of the present invention.

Figure 6 shows comparative results of the transfer characteristics (V_GS- IDS) of three a-IGZO TFTs, processed respectively with standard BCE (S/D etch after IGZO etch), with the BCE process according to aspects of the present invention (S/D etch before IGZO etch) and with conventional lift-off processes.

Figure 7 shows a capacitance comparison of a MIS (with a-IGZO) and a MIM (without a-IGZO) structure for an area of 500 x500 urn² showing less than 5% difference.

Figure 8 shows transfer characteristics (V_GS-l_Ds) of an a-IGZO TFT (W/L = 70/10 μηι/μΓη) as function of stress time (a) at V_GS = +12V and V_DS = +12V, (b) at V_GS = -12 V and V_DS = 0 V (c) V_TH shift of a-IGZO TFTs as a function of the stress time in both positive and negative directions.

Figure 9 illustrates (a) Transfer (V_GS-l_Ds) and (b) output (V_DS-l_Ds) characteristics for a drive TFT with W/L = 55/5 μηι/μΓη, (c) Transfer curves (at V_DS = 10 V) of 9 TFTs measured across a 150mm PEN foil substrate.

In the different drawings, the same reference signs refer to the same or analogous elements.

Detailed description of preferred embodiments

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure and how it may be practiced in particular embodiments. However, it will be understood that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures and techniques have not been described in detail, so as not to obscure the present disclosure. While the present disclosure will be described with respect to particular embodiments and with reference to certain drawings, the disclosure is not limited hereto. The drawings included and described herein are schematic and are not limiting the scope of the disclosure. It is also noted that in the drawings, the size of some elements may be exaggerated and, therefore, not drawn to scale for illustrative purposes.

Furthermore, the terms first, second, third and the like in the description, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the disclosure described herein are capable of operation in other sequences than described or illustrated herein.

Moreover, the terms top, bottom, over, under and the like in the description are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the disclosure described herein are capable of operation in other orientations than described or illustrated herein.

It is to be noticed that the term "comprising" should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B.

Certain embodiments provide a method for fabricating bottom-gate top- contact metal oxide semiconductor thin film transistors, wherein the method comprises forming on a substrate a gate electrode, providing a gate dielectric layer covering the gate electrode and depositing a metal oxide semiconductor layer on the gate dielectric layer. In one embodiment, the method further comprises: depositing a metal layer on top of the metal oxide semiconductor layer; and patterning the metal layer to form source and drain contacts, wherein patterning the metal layer comprises dry etching of the metal layer; and, thereafter, patterning the metal oxide semiconductor layer. The method may further comprise additional steps such as depositing a passivation layer (such as a layer comprising silicon oxide, silicon nitride and/or aluminum oxide) and/or annealing.

In a method according to one embodiment, patterning the metal oxide semiconductor layer is done after patterning the metal layer (by dry etching) on top of the metal oxide semiconductor layer, i.e. after defining the source and drain contacts.

An example of a process flow for fabricating a metal oxide semiconductor thin film transistor in accordance with one embodiment is schematically shown in Figure 1 and further illustrated in Figure 2. After depositing on an electrically insulating substrate 10 a gate metal layer or metal stack (process 1 ), such as an about 30 nm to 300 nm thick Mo, Ti, Cr or Cu layer or a Ti/Mo or Mo/AI/Mo stack, the gate metal layer or metal stack is patterned by means of photolithography and wet or dry etching (process 2), to form a gate electrode 1 1 . Next a gate dielectric layer 12 is deposited (process 3), such as a silicon oxide layer, a silicon nitride layer or an aluminum oxide layer, or any other suitable dielectric layer or layer stack known by a person skilled in the art. The resulting structure is illustrated in Figure 2(a). The substrate can be a rigid substrate, a flexible substrate or a stretchable substrate. When processing on a flexible or a stretchable substrate, the substrate can be provided on a (temporary) rigid carrier during processing.

Vias can be formed in the gate dielectric layer (not illustrated) to contact the gate. Next a metal oxide semiconductor layer 13 is deposited (process 4) on top of the gate dielectric layer 12 (Figure 2(b)), such as an amorphous IGZO (Indium Gallium Zinc Oxide) layer. However, the present disclosure is not limited thereto, and other metal oxide semiconductor layers can be used. Preferred metal oxide semiconductors can be for instance InZnO, HflnZnO, SilnZnO, ZnO, CuO or SnO. Depositing the metal oxide semiconductor layer can for example comprise DC or RF sputtering or evaporation. The thickness of this semiconductor layer 13 can for example be in the range between about 10 nm and 80 nm.

In a next process a metal layer 14 or metal stack is deposited (process 5), e.g. by evaporation or sputtering, on the metal oxide semiconductor layer 13 (Figure 2(c)). The metal layer or metal stack can for example comprise Mo and can for example have a thickness in the range between about 50 nm and 300 nm. For example, a Mo/AI/Mo stack, a Mo/Au stack, a Mo/Ti stack, a Mo/Ti/AI/Mo stack or a Mo/ITO stack can be used, the present disclosure not being limited thereto. The metal layer or metal stack is patterned by lithography and dry (plasma) etching to form a source contact 141 and a drain contact 142 (process 6), as illustrated in Figure 2(d). The channel length can for example be in the range between 2 micrometer and 100 micrometer. After etching the metal layer to form source and drain contacts, the metal oxide semiconductor layer 13 is patterned by lithography and wet or dry etching (process 7) (Figure 2(e)) to form the active layer 131 of the transistor.

Next a passivation layer such as an about 50 nm to 300 nm thick silicon oxide, silicon nitride or aluminum oxide layer is deposited by sputtering, ALD or CVD (process 8) and patterned (process 9) using plasma etching or wet etching. Finally the structure is annealed (process 10), e.g. at a temperature in the range between about 50^QC and 175^QC in a nitrogen atmosphere or in air.

When fabricating a thin film transistor circuit in accordance with one embodiment, capacitors formed in such circuit comprise a metal oxide semiconductor layer in addition to a dielectric layer between the metal layers.

Thin film transistors were fabricated in accordance with the process flow of Figure 1 and Figure 2. On an electrically insulating substrate a patterned Mo gate (thickness about 100 nm) was provided. Next an about 100 nm thick SiN gate dielectric layer was deposited by CVD. In the next process an a-IGZO layer (ln:Ga:Zn = 1 :1 :1 atomic %, thickness about 20 nm) was deposited by RF/DC sputtering in an 0₂ environment. Mo source-drain contacts (thickness about 100 nm) were then provided on top of the a-IGZO layer by DC sputtering and patterning using a dry etching process (SF₆ + 0₂ plasma). In the following process the active areas were defined (the a-IGZO layer was patterned) by photolithography and wet etching of the metal oxide layer. Finally, a passivation layer was sputtered (about 100 nm SiO_x) and the transistors were subsequently annealed for about 1 hour at 150 'C in a N₂ environment.

The measured transistor characteristics for a transistor with about 10 micrometer channel length are shown in Figure 4. The transistors have a high mobility (about 14.06 cm²/V.s), a low sub-threshold slope (about 0.24 V/decade), low hysteresis, l_on/l_0ff larger than 10⁸ and V_TH close to zero (about 0.5V).

As a reference, GIZO thin film transistors were fabricated without using an etch stop layer but following a different process flow, wherein the metal oxide semiconductor patterning and etching was done before metal deposition instead of after source and drain metal patterning. As an additional reference, a transistor was fabricated wherein the source and drain contacts were made by means of a lift-off process (which is not suitable for upscaling due to yield issues). The transistor characteristics of these reference transistors are shown in Figure 3. The transistor fabricated without etch stop layer and with metal oxide semiconductor etching before metal deposition ('DE Mo' in Figure 3) clearly has a low ION/IOFF ratio, a high sub-threshold slope and a large hysteresis. This may be related to a negative impact on the GIZO layer of the plasma used for source and drain etching, more in particular to a non-uniform distribution of the plasma over the wafer surface due to a distributed semiconducting channel area.

In a method according to a preferred embodiment, the metal oxide semiconductor layer is not yet patterned when the source and drain are etched. Therefore the plasma may be more uniformly distributed over the entire substrate, leading to reduced local plasma non-uniformities and/or reduced local plasma charging effects on the metal oxide semiconductor layer.

A working display was fabricated including an array of thin film GIZO transistors for selecting and driving an array of pixels. The GIZO transistors had a channel length of about 5 micrometer and were fabricated in accordance with a method in one embodiment. The array of transistors was fabricated on an about 6 inch substrate. Figure 5 shows the measured transfer characteristics of five transistors from this array, one transistor being located at the centre of the substrate, and the other four transistors being located at opposite edges of the substrate. The results show a good uniformity of the transistor characteristics over the substrate.

Further experimental results are described below.

Test devices were realized on a thermally grown Si0₂ (120nm) gate dielectric on top of a highly doped Si (common gate) substrate. The active layer, a 15nm thick a-IGZO (ln:Ga:Zn=1 :1 :1 ) film, was deposited by dc-sputtering containing 6%0₂ in Argon(Ar). The thickness and 0₂/Ar ratio were optimized in order to achieve the desired TFT performance at low processing temperature. Further, 100 nm thick Mo source and drain (S/D) contacts were formed by PVD and patterned by SF₆/0₂dry etch chemistry. After the S/D formation, the active layer was patterned by a wet-etch procedure with an anoxalic acid solution. On top of the active layer, a 1 00nm Si0₂ passivation layer was deposited by reactive pulsed-DC PVD.

The electrical characteristics of the individual TFTs were measured using a parameter analyser in an inert N₂ environment. By reversing the processing order of a-IGZO patterning and S/D contact patterning as compared to prior art approaches, isolated islands of a-IGZO are avoided in a method of the present invention, suppressing local accumulation of charges during plasma etching. By modifying the standard BCE process flow in this way, the main TFT parameters such as hysteresis, mobility and overall subthreshold slope show significant improvement.

The l-V characteristics of three series of test TFTs are depicted in Fig. 6, fabricated with respectively a conventional lift-off flow, the standard BCE flow (S/D etching after semiconductor patterning), and the modified BCE flow (S/D etching before semiconductor patterning) according to aspects of the present invention. All test devices were realized on a thermally grown Si0₂ (120nm) gate dielectric on top of a highly doped Si (common gate) substrate. The a-IGZO test devices fabricated with the modified BCE flow according to aspects of the present invention clearly showed only a negligible amount of hysteresis in the transfer curves between forward and reverse gate-voltage sweeps. In fact, the results were quite similar to the results obtained with the lift-off S/D based devices. Table. 1 gives an overview of the main performance parameters for the three different flows.

The transfer characteristics of standard BCE processed TFTs showed a lower mobility of only 5- 12cm²/(V.s), a deteriorated sub-threshold swing of 0.60V/decade, and a negative threshold voltage of -0.5V. Moreover, the hysteresis in the transfer curves significantly increased in comparison with the other two flows. The latter indicates that more damage was induced during dry etching of the S/D metal layer on top of small islands of a-IGZO. The damage is attributed to local charge accumulation due to plasma exposure during the dry etch process in the isolated active areas. Overall, it was observed that the modified BCE flow resulted in a significant improvement in the device characteristics.

It was further verified whether the fact that an a-IGZO layer stays under the metal lines, could potentially affect the parasitic capacitance of the signal lines. This is particularly important for (TFT-) display and circuit applications. To verify the effect, the two capacitors were compared, corresponding to the the gate-dielectric with and without a-IGZO. A change of only 5% in the total capacitive was measured, as shown in Fig. 7. Furthermore, the influence of bias stress on the electrical performance of the TFTs was investigated. A gate-field corresponding to +/-1 .0MV/cm in positive and negative direction was applied for 10⁴ seconds of stress time at room temperature in the dark. In case of positive gate bias, corresponding to fully-on conditions, (V_DS = 12V and V_Gs = 12V) a threshold voltage shift of 0.9V was observed. In case of the negative bias (V_DS = 0V and V_GS = -12V ) a threshold voltage shift of 1 .0V was observed. Fig. 8 (a) and (b) show the change in the transfer characteristics as a function of the bias-stress time for both positive and negative gate bias. Fig. 8(c) gives a comparison of the V_TH shift as function of the stress time in both positive and negative directions.

Finally, the modified BCE process flow according to embodiments of the present invention was integrated on PEN foil with 200nm ICP-CVD SiN as gate dielectric and 100nm MoCr as gate-metallization.

A substrate foil, embodied as a 25μηι μηι thick heat-stabilized PEN foil from a commercial supplier was laminated on a 150 mm rigid glass carrier. The carrier provides support during the entire fabrication process of the digital circuits and displays. In a first step, a barrier layer of 200nm SiN was deposited at 150°C by Inductively-Coupled Plasma Chemical Vapor Deposition (ICP-CVD) on top of the PEN foil. The gate metallization consisted of a 100nm thick MoCr alloy layer, formed by Physical Vapor Deposition (PVD), followed by a wet etch patterning procedure. Next, a 200nm thick gate dielectric layer of SiN was deposited at 150°C by ICP-CVD. A low gate leakage current and high breakdown field is required for TFTs which are used as building blocks in circuits and in display backplanes. It is challenging to achieve good dielectric properties with conventional CVD deposition at the low temperatures (<200°C) required for processing on PEN foil. Therefore the processing conditions were optimized of a SiN dielectric layer deposited by ICP-CVD at 1 50°C. A breakdown field of ~8MV/cm with a leakage of 1 .3e ⁵mA/cm²at 2MV/cm (dielectric constant ε=7.1 ) was achieved.

Subsequently, the active layer, a 1 5nm thick a-IGZO (ln:Ga:Zn=1 :1 :1 ) film, was deposited by dc-sputtering containing 6%0₂ in Argon(Ar). The thickness and 0₂/Ar ratio were optimized in order to achieve the desired TFT performance at low processing temperature. Further, 100 nm thick Mo source and drain (S/D) contacts were formed by PVD and patterned by SF₆/0₂dry etch chemistry. After the S/D formation, the active layer was patterned by a wet-etch procedure with an anoxalic acid solution. On top of the active layer, a 1 00nm Si0₂ passivation layer was deposited by reactive pulsed-DC PVD.

The transfer and output characteristics of the resulting TFTs (W/L=55/5 μηι/μΓη ) are shown in Fig. 9. The TFTs show linear mobilities (μ) of 1 2-15cm²/(V.s), a V-mOf - 1 .0V, an ION/OFF ratio of 1 0⁸ and a sub-threshold swing of 0.3V/decade. In Fig. 9 (c) the V₀N and ION spread of 9 measured TFTs is shown across a 6- inchwafer containing PEN foil. The spread of V₀N and ION at V_D =1 0V and V_G = 20V is less than 5%.

The foregoing description details certain embodiments of the disclosure. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the disclosure may be practiced in many ways. It should be noted that the use of particular terminology when describing certain features or aspects of the disclosure should not be taken to imply that the terminology is being re-defined herein to be restricted to including any specific characteristics of the features or aspects of the disclosure with which that terminology is associated.

While the above detailed description has shown, described, and pointed out novel features of the disclosure as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the technology without departing from the spirit of the disclosure.

Claims

A method for fabricating a bottom-gate top-contact metal oxide semiconductor thin film transistor, the method comprising:

- forming a gate electrode on a substrate;

- providing a gate dielectric layer covering said gate electrode;

- depositing a metal oxide semiconductor layer on said gate dielectric layer;

- depositing a metal layer or metal layer stack on top of said metal oxide semiconductor layer;

- patterning said metal layer or metal layer stack to form source and drain contacts,

wherein patterning said metal layer or metal layer stack comprises dry etching of said metal layer or metal layer stack; and

thereafter, patterning said metal oxide semiconductor layer.

A method according to claim 1 , further comprising depositing a passivation layer and performing an anneal process.

A method according to any of the previous claims, wherein said metal oxide semiconductor layer comprises or consists of an amorphous IGZO (indium gallium zinc oxide) layer.

A method according to any of the previous claims 1 to 2, wherein said metal oxide semiconductor layer comprises or consists of any of or any combination of InZnO, HflnZnO, SilnZnO, ZnO, CuO or SnO layers.

A method according to any of the previous claims, wherein said metal oxide semiconductor layer has a thickness in between 10 and 80 nm.

A method according to any of the previous claims, wherein said metal layer comprises or consists of Mo or wherein said metal layer stack comprises or consists of a Mo/AI/Mo stack, a Mo/Au stack, a Mo/Ti stack, a Mo/Ti/AI/Mo stack or a Mo/ITO stack.

A method according to any of the previous claims, wherein said metal layer or said metal layer stack has a thickness in the range between about 50 nm and 300 nm.

A method according to any of the previous claims, wherein patterning the metal oxide semiconductor layer occurs after patterning the metal layer or metal layer stack on top of the metal oxide semiconductor layer for defining said source and drain contacts.

9. A method according to any of the previous claims, wherein said substrate comprises a Polyethylene Naphtalate foil.

10. A method according to any of the previous claims, further comprising forming via's in said gate dielectric layer for contacting said gate.

1 1 . Use of the method according to any of the previous claims, for fabricating transistors with a channel length in the order of 2 to 5 micrometer.