JP5437776B2 - Thin film transistor using oxide semiconductor and method of manufacturing the same - Google Patents

Description

  The present invention relates to a thin film transistor using an oxide semiconductor and a manufacturing method thereof.

  In recent years, an oxide semiconductor such as In-Ga-Zn-O (hereinafter also referred to as IGZO) has attracted attention as a next-generation semiconductor material. This IGZO has a remarkably fast electron mobility and a high on / off ratio as compared with conventionally used amorphous silicon, so that it is a display device as a thin film transistor (hereinafter also referred to as TFT), particularly an organic EL element. When used in current-driven display devices such as the above, it is expected to bring about a significant improvement in image quality. However, since IGZO is weak to both acid and alkali, various devices have been devised for use in thin film transistors.

  For example, a lift-off method has been proposed in which IGZO is covered with a photoresist, and after a necessary film forming process is completed, unnecessary portions are lifted and removed together with the photoresist (see Patent Document 1). If this lift-off method is used, the surface of the IGZO can be subjected to a lamination process without being damaged by the etching solution. However, since there is a problem that particles are generated as the photoresist is removed, there is an industrial problem. Not suitable for mass production.

  A technique using IGZO in a top gate type TFT has also been proposed (see Patent Documents 2 and 3). However, in the case of a liquid crystal display (LCD), since the backlight is irradiated from the back side of the substrate and the semiconductor layer is irradiated with light, the resistance value changes due to undesired light excitation, and the off characteristics are deteriorated. For this reason, a bottom gate type structure is adopted in the amorphous silicon TFT currently used.

  A technology using IGZO in this bottom gate type TFT has also been proposed, and a structure in which an insulating layer made of a-SiOx is formed as a channel protective film on the IGZO semiconductor layer (see Patent Document 4). However, this structure increases the number of manufacturing steps and makes it difficult to obtain a heat treatment effect for improving the characteristics of IGZO.

JP 2006-173580 A JP 2006-165527 A JP 2007-73701 A JP 2009-99847 A

  In the thin film transistor using an oxide semiconductor, the present inventor has recently provided a carbon buffer layer between the oxide semiconductor layer (active layer) and the source electrode and between the oxide semiconductor layer (active layer) and the drain electrode. It was found that the provision of a high-quality thin film transistor that effectively prevents deterioration of the oxide semiconductor due to chemical processing such as etching during manufacturing and that has excellent off characteristics and carrier mobility can be obtained. .

  Therefore, an object of the present invention is to provide a high-quality thin film transistor using an oxide semiconductor, which has excellent off characteristics and carrier mobility, and a method for manufacturing the thin film transistor.

That is, according to the present invention, a thin film transistor including a source electrode, a drain electrode, a gate electrode, a gate insulating film, and an active layer made of an oxide semiconductor,
There is provided a thin film transistor in which a carbon buffer layer is provided between the active layer and the source electrode and between the active layer and the drain electrode.

Further, according to the present invention, there is provided a manufacturing method of a bottom gate type thin film transistor,
Forming a gate electrode on the substrate;
Forming a gate insulating film on the gate electrode;
Forming an active layer made of an oxide semiconductor on the gate insulating film;
Forming a carbon buffer layer on the active layer;
Forming an electrode layer for a source electrode and a drain electrode on the buffer layer;
Removing a part of the electrode layer by etching, forming a source electrode and a drain electrode apart from each other, and exposing the buffer layer between the source electrode and the drain electrode; and Removing the exposed portion by oxygen ashing to expose the active layer between the source electrode and the drain electrode.

Furthermore, according to the present invention, there is provided a method of manufacturing a top gate type thin film transistor,
Forming an active layer made of an oxide semiconductor on a substrate;
Forming a carbon buffer layer on the active layer;
Forming an electrode layer for a source electrode and a drain electrode on the buffer layer;
Removing a part of the electrode layer by etching, forming a source electrode and a drain electrode apart from each other, and exposing the buffer layer between the source electrode and the drain electrode; and Removing the exposed portion by oxygen ashing to expose the active layer between the source electrode and the drain electrode; and exposing the drain electrode, the source electrode, and the source electrode and the drain electrode Forming a gate insulating film on the active layer;
Forming a gate electrode on the gate insulating film.

  Moreover, according to this invention, the device provided with the said thin-film transistor is also provided.

It is a schematic cross section which shows an example of the bottom gate type thin-film transistor by this invention. It is a schematic cross section which shows an example of the top gate type thin-film transistor by this invention. It is a figure which shows the flow of the first half (process 1-5) of the manufacturing process of the bottom gate type thin-film transistor by Example 1 in Example 1. FIG. It is a figure which shows the flow of the latter half (process 6-9) of the manufacturing process of the bottom gate type thin-film transistor by this invention in Example 1. FIG. 6 is a graph showing a relationship between a gate voltage Vg and a drain current Id in a thin film transistor having an active layer (IGZO layer) with various thicknesses, measured in Example 2. 10 is a graph showing the relationship between the gate voltage Vg and the drain current Id measured in Example 3 when there is an amorphous carbon buffer layer and when there is no amorphous carbon buffer layer.

Thin Film Transistor FIG. 1 is a schematic cross-sectional view of an example of a thin film transistor according to the present invention. Although the thin film transistor shown in FIG. 1 is a bottom gate type, the present invention is not limited to this and can be applied to a top gate type. As shown in FIG. 1, the thin film transistor 10 according to the present invention includes a source electrode 11, a drain electrode 12, a gate electrode 13, a gate insulating film 14, and an active layer 15. The active layer 15 is made of an oxide semiconductor. In addition, as the source electrode 11, the drain electrode 12, the gate electrode 13, and the gate insulating film 14, a well-known thing can be employ | adopted widely in the thin-film transistor field | area, and it does not specifically limit.

  In the present invention, a carbon buffer layer 16 is provided between the active layer 15 and the source electrode 11 and between the active layer 15 and the drain electrode 12. Thereby, even if it is a case where an active layer is comprised with an oxide semiconductor weak to acids and alkalis, such as IGZO, degradation of the oxide semiconductor by chemical treatments, such as subsequent etching, can be prevented effectively. In particular, according to the knowledge of the present inventor, the carbon buffer layer can be etched by dry etching (hereinafter also referred to as oxygen ashing) using oxygen plasma. This is because etching is performed using the same oxygen as the constituent element of the oxide semiconductor active layer, so that the active layer is not damaged, but rather the oxygen deficiency of the oxide semiconductor active layer is compensated. In this case, various characteristics are improved. As a result, in a thin film transistor, a high on / off ratio, a threshold voltage in the vicinity of 0 V advantageous for device design, and a remarkably fast carrier mobility can be realized, and a display device, particularly a current-driven display device such as an organic EL element, It is expected to bring about a significant improvement in image quality when used in

Therefore, the thin film transistor according to the present invention can have a high on / off ratio of preferably 6 digits or more, more preferably 8 digits or more, and even more preferably 10 digits or more. In addition, the thin film transistor according to the present invention can have a fast carrier mobility of preferably 5 cm ² / sV or more, more preferably 10 cm ² / sV or more, and further preferably 12 cm ² / sV or more. Furthermore, the thin film transistor according to the present invention can have a threshold voltage advantageous in terms of device design, preferably −15 to +5 V, more preferably −10 to +5 V, and still more preferably −5 to +5 V.

The active layer in the present invention is made of an oxide semiconductor. The oxide semiconductor is not particularly limited as long as it has an acceptable performance as a thin film transistor. For example, zinc oxide, tin oxide, indium oxide, gallium oxide, copper oxide, lanthanum oxide, bismuth oxide, titanium oxide, silicon oxide , Aluminum oxide, calcium oxide, strontium oxide, barium oxide, yttrium oxide, and composite oxides composed of two or more thereof. A preferred oxide semiconductor comprises at least one selected from the group consisting of zinc oxide, tin oxide, indium oxide, and gallium oxide, more preferably at least zinc oxide, and even more preferably gallium oxide and It further comprises indium oxide. The most preferred oxide semiconductor is In-Ga-Zn-O (IGZO), typically amorphous In-Ga-Zn-O (a-IGZO). A preferable composition of In-Ga-Zn-O (IGZO) is 1.0 ≦ m when In _x Ga _y Zn _z O _m (where x> 0, y> 0, z> 0, m> 0). /(X+y+z)≦2.5, more preferably 1.3 ≦ m / (x + y + z) ≦ 2.0, and further preferably 1.3 ≦ m / (x + y + z) ≦ 1.5. . Since the thickness of the active layer may affect the on / off ratio depending on the structure of the TFT, it is preferably 200 to 1000 mm, more preferably 200 to 500 mm, and still more preferably 250 to 500 tons.

  The buffer layer in the present invention is made of carbon, and various carbon materials such as amorphous carbon and diamond-like carbon can be used. A preferred buffer layer is made of amorphous carbon, more preferably conductive amorphous carbon. The conductive amorphous carbon preferably has a hydrogen concentration of 15 at% or less, more preferably 12 at% or less, and further preferably 5 at% or less. Note that the lower limit of the hydrogen concentration is not particularly limited and may be zero. However, considering the inevitable mixing of hydrogen due to the film formation environment during sputtering, 3 at% is an example of the lower limit. In addition, although the measurement of the hydrogen concentration in a buffer layer can be performed by well-known various methods, it is preferable to be performed by HFS (Hydrogen Forward Scattering). Thus, by making the hydrogen concentration extremely low, it is possible to avoid a decrease in conductivity or an expression of insulation due to the carbon constituting the buffer layer being terminated with hydrogen. Therefore, it is preferable that the amorphous carbon is not substantially doped with impurities other than carbon and hydrogen. Here, “substantially undoped” means that impurities are not intentionally doped in order to provide some function, and inevitably mixed due to the film forming environment during sputtering. Impurities are allowed. From such a viewpoint, in the present invention, the conductive amorphous carbon preferably has an oxygen concentration of 0 to 300 ppm, a halogen element concentration of 0 to 1000 ppm, and a nitrogen concentration of 0 to 500 ppm. Although the film thickness of a buffer layer is not specifically limited, It is preferable that it is 3-30 nm, More preferably, it is 3-15 nm, More preferably, it is 5-10 nm. If the thickness is within such a range, the thin film transistor avoids an increase in film resistance due to the increase in film thickness while sufficiently securing the shielding against the semiconductor active layer in a chemical process such as etching in the TFT manufacturing process. It is possible to prevent a decrease in the on-characteristic. The buffer layer can be produced based on a known method such as sputtering or CVD.

  The structure of the thin film transistor of the present invention may be either a top gate type or a bottom gate type. As shown in FIG. 1, the bottom-gate thin film transistor 10 includes a gate electrode 13, a gate insulating film 14, an active layer 15, a buffer layer 16, and a source electrode 11 that is disposed apart from each other on a substrate 17. Typically, the drain electrode 12 and the drain electrode 12 are sequentially stacked. In the illustrated example, a passivation layer 18 (insulating film) is further provided so as to cover all of the source electrode 11, the drain electrode 12, and the active layer 15 exposed between the source electrode and the drain electrode. On the other hand, as shown in FIG. 2, the top-gate thin film transistor 20 includes an active layer 25, a buffer layer 26, a source electrode 21 and a drain electrode 22 provided apart from each other, a gate insulating film 24, In addition, it is typical that the gate electrode 23 is sequentially laminated. In particular, it is advantageous for a liquid crystal display (LCD) application that the thin film transistor of the present invention can be configured as a bottom gate type. This is because, according to the bottom gate type, it is possible to avoid the deterioration of the off characteristics due to the light excitation of the semiconductor active layer caused by the backlight irradiation from the back side of the substrate in the top gate type.

Manufacturing Method The thin film transistor according to the present invention can be manufactured as follows.

(1) Production of Bottom Gate Thin Film Transistor The bottom gate thin film transistor 10 as shown in FIG. 1 can be produced as follows. First, after forming the gate electrode 13 on the substrate 17, the gate insulating film 14 is formed on the gate electrode 13, and the active layer 15 made of an oxide semiconductor is further formed on the gate insulating film 14. Any of these forming steps can be performed according to known film formation, patterning, and etching techniques.

  Then, a carbon buffer layer 16 is formed on the active layer 15. The carbon buffer layer can be produced based on a known method such as sputtering or CVD. In order to obtain a buffer layer made of conductive amorphous carbon, the buffer layer is preferably formed by sputtering. This sputtering is preferably performed using a carbon-based target such as graphite or glassy carbon in an argon gas atmosphere to which no hydrogen gas is added. However, as long as the desired function as the buffer layer 16 is not impaired, it is allowed to mix a trace amount of additive gas such as hydrocarbon and hydrogen into the argon gas. For example, when the buffer layer is made of conductive amorphous carbon, the amount of additive gas is preferably set so that the hydrogen concentration in the conductive amorphous carbon film is 15 at% or less. The flow ratio of the additive gas to the argon gas is preferably 0.4% by volume or less, more preferably 0.2% by volume or less. A large amount of an additive gas such as hydrocarbon or hydrogen is not preferable because amorphous carbon is terminated with hydrogen and conductivity may be lowered to be insulative. The sputtering method may be a known method such as DC sputtering, DC magnetron sputtering, RF sputtering, or RF magnetron sputtering, and may be performed based on known film formation conditions.

  Next, electrode layers for the source electrode 11 and the drain electrode 12 are formed on the buffer layer 16. A part of the electrode layer is removed by etching so that the source electrode 11 and the drain electrode 12 are formed apart from each other, and the buffer layer 16 is exposed as a channel portion between the source electrode 11 and the drain electrode 12. Any of these forming steps can be performed according to known film formation, patterning, and etching techniques. Then, the exposed portion of the buffer layer 16 is removed by oxygen ashing to expose the active layer 15 as a channel portion between the source electrode 11 and the drain electrode 12. Oxygen ashing is dry etching using oxygen plasma, and can be performed according to a known technique. In particular, oxygen ashing is performed by using the same oxygen as the constituent element of the oxide semiconductor active layer to be exposed, so that it does not damage the active layer, but rather the oxygen of the oxide semiconductor active layer. As a result, the characteristics (particularly off characteristics) can be improved when a thin film transistor is formed. Therefore, dry etching using Cl, F-based gas is not desirable because, as a result of etching the buffer layer, ion damage such as Cl, F enters the channel portion, which may cause deterioration of thin film transistor characteristics. Subsequently, if desired, a passivation layer 18 (insulating film) is formed so as to cover the source electrode 11, the drain electrode 12, and the active layer 15 exposed between the source electrode 11 and the drain electrode 12. A part is removed by dry etching to form a pad portion.

(2) Manufacture of Top Gate Type Thin Film Transistor The top gate type thin film transistor 20 as shown in FIG. 2 can be manufactured as follows. First, the active layer 25 made of an oxide semiconductor is formed on the substrate 27 according to a known film formation, patterning and etching technique. Then, a carbon buffer layer 26 is formed on the active layer 25. The formation method and conditions of the buffer layer 26 are the same as in the case of the above-described (1) bottom-gate thin film transistor.

  Next, electrode layers for the source electrode 21 and the drain electrode 22 are formed on the buffer layer 26. A part of the electrode layer is removed by etching so that the source electrode 21 and the drain electrode 22 are formed apart from each other, and the buffer layer 26 is exposed as a channel portion between the source electrode 21 and the drain electrode 22. Then, the exposed portion of the buffer layer 26 is removed by oxygen ashing to expose the active layer 25 as a channel portion between the source electrode 21 and the drain electrode 22. A gate insulating film 24 is formed on the source electrode 21, the drain electrode 22, and the active layer 25 exposed between the source electrode 21 and the drain electrode 22, and a gate electrode 23 is further formed on the gate insulating film 24. Any of these forming steps can be performed according to known film formation, patterning, and etching techniques.

  In the production methods (1) and (2) above, known etching techniques include dry etching, wet etching, and combinations thereof. The region to be etched may be defined based on a known method such as patterning by photolithography, and is not particularly limited.

Applications The thin film transistor according to the present invention can be applied to various devices using the thin film transistor. Preferable examples of such devices include (1) display devices such as organic EL displays, liquid crystal displays, and electronic paper, and (2) storage devices such as various RAMs and flash memories.

  The present invention is more specifically described by the following examples.

Example 1: Fabrication of thin film transistor
A bottom-gate thin film transistor in which a conductive amorphous carbon buffer layer was formed on the IGZO active layer was manufactured as follows while following the procedure shown in FIGS. 3A and 3B. First, an Al—Ni—B alloy thin film having a thickness of 2000 mm was formed as an electrode layer for the gate electrode 32 on a glass substrate 31 (Corning # 1737 (50 mm square × 0.7 mm thick)). After mounting an aluminum alloy target (diameter 203.2 × 8 mm) having a composition of Ni-0.2B (at.%) On a magnetron sputtering apparatus (MSL-464, manufactured by Tokki Co., Ltd.) connected to a Cryo pump, Input power (DC): 1000 W (3.1 W / cm ² ), ultimate vacuum: 5 × 10 ⁻⁵ Pa, sputtering pressure: 0.5 Pa, Ar flow rate: 100 sccm, substrate temperature: room temperature.

The resist was patterned on the electrode layer by photolithography. First, TFR-970 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied on the substrate as a positive resist. The resist was applied by a spin coater under the condition of 3000 rpm so that the resist thickness was about 1.5 μm. Next, after prebaking at 110 ° C. for 1.5 minutes on a hot plate, UV exposure was performed at an exposure amount of 15 mJ / cm ² through a Cr mask capable of forming the elements shown in FIGS. 3A and 3B. A developer (TMAH 2.38%, 23 ° C.) was prepared and developed for 1 minute by the dip method (Dip). After sufficiently removing the developer with deionized (DI) running water, post-baking at 110 ° C. for 3 minutes was performed on a hot plate. Through the resist pattern thus formed, unnecessary portions of the electrode layer were removed by wet etching to give the shape of the gate electrode 32 (step 1 in FIG. 3A). This wet etching was performed using a phosphoric acid etching solution (manufactured by Kanto Chemical Co., Inc.) under the conditions of an etching solution temperature of 40 ° C. and an etching time of 1 minute, and rinsed with deionized (DI) water for 3 minutes. Next, the resist was removed using TST-AQ8 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) as a stripping solution. Peeling was performed for 5 minutes at a liquid temperature of 40 ° C., and for 3 minutes while flowing deionized (DI) water.

A SiNx (silicon nitride) gate insulating film 33 having a thickness of 3000 mm was formed on the gate electrode 32 by CVD (step 2 in FIG. 3A). This CVD uses a CVD device (manufactured by Samco) connected with TMP + RP (turbomechanical pump and rotary pump), effective discharge range: φ203.2mm, input power (RF): 250W (0.8W / cm ² ), Ultimate vacuum: 5 × 10 ⁻⁴ Pa, deposition pressure: 80 Pa, SiH ₄ flow rate: 100 sccm, NH ₃ flow rate: 10 sccm, N ₂ flow rate: 200 sccm, substrate heating: 350 ° C. (heating holding time: 3 minutes) It went on condition of.

An IGZO active layer 34 having a thickness of 125 mm, 250 mm, 500 mm, and 1000 mm was formed on the gate insulating film 33 by sputtering (step 3 in FIG. 3A). In this sputtering, an IGZO target (diameter 203.2 mm × thickness 8 mm) having a composition of In: Ga: Zn: O = 1: 1: 1: 4 (at ratio) is connected to a cryochamber with a multi-chamber. After mounting on a magnetron sputtering device (MSL-464, manufactured by Tokki Co., Ltd.), input power (DC): 300 W (0.9 W / cm ² ), ultimate vacuum: 5 × 10 ⁻⁵ Pa, sputtering pressure: 0.4 Pa, Ar flow rate: 80 sccm, O ₂ flow rate: 10 sccm, substrate temperature: room temperature. At this time, by changing the sputtering time to 0.5 minutes, 1 minute, 2 minutes, and 4 minutes, IGZO active layers having thicknesses of 125 mm, 250 mm, 500 mm, and 1000 mm were formed, respectively.

A 70 cm thick amorphous carbon buffer layer 35 was formed on the IGZO active layer 34 by sputtering (step 4 in FIG. 3A). This sputtering is a multi-chamber magnetron sputtering system in which a graphite target (1G-70, manufactured by Toyo Tanso Co., Ltd., diameter 203.2 mm x thickness 8 mm) made by sintering graphite powder is connected to a Cryo pump ( After mounting on MSL-464 (manufactured by Tokki Corporation), input power (DC): 250 W (0.8 W / cm ² ), ultimate vacuum: 5 × 10 ^-5 Pa, sputtering pressure: 0.5 Pa, Ar flow rate: 100 sccm Substrate temperature: performed at room temperature.

An electrode layer 36 having a thickness of 1500 mm for the source and drain electrodes was formed on the amorphous carbon buffer layer 35 by sputtering (step 5 in FIG. 3A). In this sputtering, an aluminum alloy target (diameter 203.2 mm × thickness 8 mm) having a composition of Al-3.2Ni-0.2B (at.%) Is connected to a multi-chamber magnetron sputtering apparatus (MSL-) connected with a Cryo pump. 464, manufactured by Tokki Co., Ltd.), input power (DC): 1000 W (3.1 W / cm ² ), ultimate vacuum: 5 × 10 ⁻⁵ Pa, sputtering pressure: 0.5 Pa, Ar flow rate: 100 sccm, substrate Temperature: Performed at room temperature.

  Resist patterning was performed on the electrode layer 36 by the same method as in Step 1. An unnecessary portion of the electrode layer 36 was removed by wet etching through the formed resist pattern (step 6 in FIG. 3B). This wet etching was performed using a phosphoric acid etching solution (manufactured by Kanto Chemical Co., Inc.) under the conditions of an etching solution temperature of 40 ° C. and an etching time of 45 seconds, and rinsed with deionized (DI) water for 3 minutes.

Subsequently, unnecessary portions of the amorphous carbon buffer layer 35 were removed by dry etching through the resist pattern (step 7 in FIG. 3B). This dry etching was performed using a dry etching apparatus (10NR, manufactured by Samco Corporation) under the conditions of gas: CF ₄ / O ₂ = 50/60 sccm, RF: 50 W, pressure: 5 Pa, etching time: 25 seconds. Further, unnecessary portions of the IGZO active layer 34 were removed by wet etching through the resist pattern (step 7 in FIG. 3B). This wet etching was performed using a phosphoric acid etching solution (manufactured by Kanto Chemical Co., Inc.) under the conditions of an etching solution temperature of 25 ° C. and an etching time of 1 minute, and rinsed with deionized (DI) water for 3 minutes. Next, the resist pattern was removed by the same method as in Step 1.

Resist patterning was performed on the electrode layer 36 by the same method as in Step 1. Through the formed resist pattern, a portion to be a channel portion in the electrode layer 36 was removed by wet etching to give the shapes of the source electrode 36a and the drain electrode 36b (Step 8 in FIG. 3B). This wet etching was performed using a phosphoric acid etching solution (manufactured by Kanto Chemical Co., Inc.) under the conditions of an etching solution temperature of 40 ° C. and an etching time of 45 seconds, and rinsed with deionized (DI) water for 3 minutes. Subsequently, a portion to be a channel portion of the amorphous carbon buffer layer 35 exposed between the source electrode and the drain electrode was removed by oxygen ashing (dry etching). This oxygen ashing was performed using a dry etching apparatus (10NR, manufactured by Samco) under the conditions of gas: O ₂ = 50 sccm, RF: 100 W, pressure: 10 Pa, etching time: 2 minutes. Next, the resist pattern was removed by the same method as in Step 1.

A passivation layer 37 (insulating film) having a thickness of 1500 mm was formed by reactive sputtering so as to cover the uppermost surface of the thin film transistor laminated structure thus obtained (step 9 in FIG. 3B). In this reactive sputtering, a silicon target (diameter 203.2 mm × thickness 8 mm) is mounted on a multi-chamber magnetron sputtering apparatus (MSL-464, manufactured by Tokki Co., Ltd.) connected with a Cryo pump, and then input power (DC ): 300 W (0.9 W / cm ² ), ultimate vacuum: 5 × 10 ⁻⁵ Pa, sputtering pressure: 0.5 Pa, Ar flow rate: 80 sccm, O ₂ flow rate: 10 sccm, substrate temperature: room temperature.

Resist patterning was performed on the passivation layer 37 in the same manner as in Step 1. A part of the passivation layer 37 was removed by dry etching through the formed resist pattern to form a pad portion (not shown). This dry etching was performed using a dry etching apparatus (10NR, manufactured by Samco) under the conditions of gas: CF ₄ / O ₂ = 60/5 sccm, RF: 100 W, pressure: 4 Pa, etching time: 5 minutes and 30 seconds. . Next, the resist pattern was removed by the same method as in Step 1. Thus, the bottom gate type thin film transistor 30 shown in FIG. 3B was obtained. The obtained thin film transistor was heat-treated in the atmosphere at a temperature of 250 ° C. for 10 minutes.

Example 2: Measurement of on / off ratio and carrier mobility The relationship between the gate voltage Vg and the drain current Id of the thin film transistor having an amorphous carbon buffer layer manufactured in Example 1 was measured. This measurement is performed using a semiconductor analyzer device (B1500A, manufactured by Agilent Technologies) under the conditions of source / drain voltage: 5 V, gate voltage: -30 to +20 V (scanning from minus to plus every 0.5 V). It was. The obtained result was as shown in FIG. Based on the obtained results, the on / off ratio and the carrier mobility μ (cm ² / sV) were calculated. The on / off ratio was calculated by determining the ratio of the drain current between the on state and the off state with the gate voltage of −10 V off (Off) and +15 V on (V) on the basis of Vth. The carrier mobility was calculated by expressing the Id-Vg characteristic line with a linear scale and determining its proportionality constant. The results were as shown in Table 1.

  From the results shown in Table 1, it can be seen that a transistor capable of high-speed reaction can be realized by reducing the film thickness of IGZO to 250 mm. In a general structure, process damage occurs, so when the IGZO film thickness is reduced, the off current tends to increase. However, by providing an amorphous carbon film buffer layer, it is 10 digits at 250 mm. The extremely high on / off ratio was achieved.

Example 3: Influence on various properties by presence or absence of conductive amorphous carbon buffer layer Regarding the thin film transistor having an amorphous carbon buffer layer (IGZO active layer thickness: 500 mm) produced in Example 1, Similarly, the relationship between the gate voltage Vg and the drain current Id was measured. The obtained result was as shown in FIG. In FIG. 5, the upper two Id-Vg characteristic lines correspond to the left logarithmic scale, and the lower two Id-Vg characteristic lines correspond to the right linear scale. Based on the obtained results, threshold voltage Vth (V) and carrier mobility μ (cm ² / sV) were calculated. The threshold voltage Vth was determined by reading the gate voltage Vg when the drain current Id exceeded 0A from the Id-Vg characteristic line using a linear scale. The carrier mobility was calculated by obtaining a proportional constant of the Id-Vg characteristic line using a linear scale. For comparison, the same measurement was performed on a thin film transistor sample manufactured in the same manner as in Example 1 except that the amorphous carbon buffer layer was not provided. The results were as shown in Table 2.

Example 4: Fabrication and evaluation of thin film transistor using conductive carbon buffer layer of other composition
IGZO target having a composition of In: Ga: Zn: O = 2: 2: 1: 7 (at ratio) instead of a composition of In: Ga: Zn: O = 1: 1: 1: 4 (at ratio) A thin film transistor was fabricated in the same manner as in Example 1 except that the above was used, and the same evaluation as in Examples 2 and 3 was performed. As a result, almost the same result as that of the thin film transistor manufactured in Example 1 was obtained.

Claims (14)

A thin film transistor including a source electrode, a drain electrode, a gate electrode, a gate insulating film, and an active layer made of an oxide semiconductor,
A thin film transistor in which a carbon buffer layer is provided between the active layer and the source electrode and between the active layer and the drain electrode.   2. The thin film transistor according to claim 1, wherein the oxide semiconductor comprises at least one selected from the group consisting of zinc oxide, tin oxide, indium oxide, and gallium oxide.   The thin film transistor according to claim 1, wherein the oxide semiconductor includes at least zinc oxide.   The thin film transistor according to claim 1, wherein the oxide semiconductor comprises gallium oxide and indium oxide.   The thin film transistor according to claim 1, wherein the oxide semiconductor is In—Ga—Zn—O (IGZO).   The thin film transistor according to claim 1, wherein the active layer has a thickness of 200 to 1000 mm.   The thin film transistor according to claim 1, wherein the buffer layer is made of amorphous carbon. Wherein the amorphous carbon, not impurity Gad-loop other than carbon and hydrogen, a thin film transistor according to claim 7.   The thin film transistor according to any one of claims 1 to 8, wherein the buffer layer has a thickness of 3 to 30 nm.   The bottom gate type in which the gate electrode, the gate insulating film, the active layer, the buffer layer, and the source electrode and the drain electrode that are spaced apart from each other are sequentially stacked on a substrate. The thin-film transistor as described in any one of 1-9.   2. The top gate type in which the active layer, the buffer layer, the source and drain electrodes, the gate insulating film, and the gate electrode, which are provided apart from each other, are sequentially stacked on a substrate. The thin-film transistor as described in any one of -9. A manufacturing method of a bottom gate type thin film transistor,
Forming a gate electrode on the substrate;
Forming a gate insulating film on the gate electrode;
Forming an active layer made of an oxide semiconductor on the gate insulating film;
Forming a carbon buffer layer on the active layer;
Forming an electrode layer for a source electrode and a drain electrode on the buffer layer;
Removing a part of the electrode layer by etching, forming a source electrode and a drain electrode apart from each other, and exposing the buffer layer between the source electrode and the drain electrode; and Removing the exposed portion by oxygen ashing to expose the active layer between the source electrode and the drain electrode. A method of manufacturing a top gate type thin film transistor,
Forming an active layer made of an oxide semiconductor on a substrate;
Forming a carbon buffer layer on the active layer;
Forming an electrode layer for a source electrode and a drain electrode on the buffer layer;
Removing a part of the electrode layer by etching, forming a source electrode and a drain electrode apart from each other, and exposing the buffer layer between the source electrode and the drain electrode; and Removing the exposed portion by oxygen ashing to expose the active layer between the source electrode and the drain electrode; and exposing the drain electrode, the source electrode, and the source electrode and the drain electrode Forming a gate insulating film on the active layer;
Forming a gate electrode on the gate insulating film. A device comprising the thin film transistor according to any one of claims 1 to 11 , wherein the device is a display device selected from the group consisting of an organic EL display, a liquid crystal display, and electronic paper, or a RAM and a flash memory. A device that is a storage device selected from the group consisting of:

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