KR102350155B1 - Oxide semiconductor thin film, thin film transistor and sputtering target - Google Patents

Abstract

[PROBLEMS] An object of the present invention is to provide an oxide semiconductor thin film having a relatively low manufacturing cost and high carrier mobility and light stress resistance when a thin film transistor is formed.
[Solutions] The present invention is an oxide semiconductor thin film containing a metal element, wherein the metal element consists of In, Zn, Fe and unavoidable impurities, and the number of atoms of In relative to the total number of atoms of In, Zn and Fe is The number is 58atm% or more and 80atm% or less, the number of atoms of Zn is 19atm% or more and 41atm% or less, and the number of atoms of Fe is 0.6atm% or more and 3atm% or less.

Description

Oxide semiconductor thin film, thin film transistor and sputtering target

The present invention relates to an oxide semiconductor thin film, a thin film transistor, and a sputtering target.

An amorphous oxide semiconductor has high carrier mobility when a thin film transistor (TFT) is formed compared with an amorphous silicon semiconductor, for example. In addition, the amorphous oxide semiconductor has a large optical band gap and high transmittance of visible light. In addition, the thin film of the amorphous oxide semiconductor can be formed at a lower temperature than that of the amorphous silicon semiconductor. Taking advantage of these characteristics, the amorphous oxide semiconductor thin film is expected to be applied to a next-generation large-scale display capable of high-resolution and high-speed driving, and a flexible display using a resin substrate that requires film formation at a low temperature.

As such an amorphous oxide semiconductor thin film, an In-Ga-Zn-O (IGZO) amorphous oxide semiconductor thin film containing indium, gallium, zinc and oxygen is known (for example, refer to Unexamined-Japanese-Patent No. 2010-219538). Compared to the carrier mobility of the thin film transistor using the amorphous silicon semiconductor is also 0.5cm ² / Vs level, IGZO TFT using an amorphous oxide semiconductor thin film described in the above publication has a 1cm ² / Vs or more mobility.

As an amorphous oxide semiconductor thin film with improved mobility, an oxide semiconductor thin film containing indium, gallium, zinc and tin and an oxide semiconductor thin film containing indium, gallium, tin and oxygen are known (for example, Japanese Patent Laid-Open No. 2010- 118407 (see Japanese Patent Application Laid-Open No. 2013-249537). For example, in the TFT using the In-Ga-Zn-Sn amorphous oxide semiconductor thin film described in the above publication, the carrier mobility ^{exceeds 20 cm 2} /Vs at a channel length of 1000 µm. However, in a TFT with a short channel length, carrier mobility tends to decrease, and there is a concern that carrier mobility in a short channel region is insufficient for use in, for example, next-generation large-sized displays that require high speed. there is

Moreover, since these amorphous oxide semiconductors contain gallium (Ga) which is a rare element, manufacturing cost is comparatively high. For this reason, the oxide semiconductor which does not contain Ga is calculated|required.

In addition, in order to use the amorphous oxide semiconductor thin film used for the thin film transistor for a display, it is desired that the threshold voltage shift in time is small even when light is irradiated to the thin film transistor, that is, the so-called light stress resistance is high. have.

Japanese Patent Laid-Open No. 2010-219538 Japanese Patent Laid-Open No. 2010-118407 Japanese Patent Laid-Open No. 2013-249537

The present invention has been made based on the circumstances described above, and the manufacturing cost is relatively low and the carrier mobility and light stress resistance when the thin film transistor is formed are high. An oxide semiconductor thin film, a thin film transistor using the oxide semiconductor thin film; And it aims at provision of the sputtering target for forming this oxide semiconductor thin film.

The present inventors discovered that an oxide semiconductor thin film which has high carrier mobility and light stress resistance even if it does not contain Ga can be obtained by including iron (Fe) in a predetermined amount in an oxide semiconductor thin film, and completed this invention.

That is, the oxide semiconductor thin film according to an aspect of the present invention is an oxide semiconductor thin film containing a metal element, wherein the metal element consists of In, Zn, Fe and unavoidable impurities, and the total number of atoms of In, Zn and Fe , the number of atoms of In is 58 atm% or more and 80 atm% or less, the number of atoms of Zn is 19 atm% or more and 41 atm% or less, and the number of atoms of Fe is 0.6 atm% or more and 3 atm% or less.

Since the said oxide semiconductor thin film makes the number of atoms of In and Zn into the said range, and makes the number of atoms of Fe more than the said lower limit, it has high light stress resistance. Moreover, since the said oxide semiconductor thin film makes the number of Fe atoms below the said upper limit, carrier mobility at the time of forming a thin film transistor using the said oxide semiconductor thin film can be improved. Moreover, since the said oxide semiconductor thin film does not need to contain Ga, manufacturing cost can be reduced.

The said oxide semiconductor thin film is used suitably for a display apparatus.

The present invention includes a thin film transistor having the oxide semiconductor thin film. Since the said thin film transistor has the said oxide semiconductor thin film, manufacturing cost is comparatively low, and carrier mobility and light stress resistance are high.

As a threshold voltage shift by light irradiation of the said thin film transistor, 5 V or less is preferable. By carrying out the said threshold voltage shift below the said upper limit, the performance stability of a thin film transistor can be improved.

The carrier mobility of the thin film transistor ^{is preferably 32 cm 2} /Vs or more. By making the said carrier mobility more than the said lower limit, it can utilize suitably for the large-size display of the next generation, for example in which high speed is calculated|required.

In addition, the sputtering target according to another aspect of the present invention is a sputtering target used for the formation of an oxide semiconductor thin film containing a metal element, wherein the metal element consists of In, Zn, Fe and unavoidable impurities, In, With respect to the total number of atoms of Zn and Fe, the number of atoms of In is 58 atm% or more and 80 atm% or less, the number of atoms of Zn is 19 atm% or more and 41 atm% or less, and the number of atoms of Fe is 0.6 atm% or more and 3 atm% or less.

Since the sputtering target contains In, Zn, and Fe whose atomic number is within the above range, by forming an oxide semiconductor thin film using the sputtering target, the manufacturing cost is relatively low, and the carrier mobility and light stress resistance are high. can do.

Here, the "carrier mobility" represents the field effect mobility in the saturation region of the thin film transistor, and the "field effect mobility" means the gate voltage Vg[V], the threshold voltage Vth[V], and the drain current Id[ A], the channel length L [m], the channel width W [m], and the capacitance C _ox [F] of the gate insulating film, in the saturation region of the current-voltage characteristic of the thin film transistor (Vg>Vd-Vth), It points out the value calculated|required by _{mu FE} [m ² /Vs] shown in the following formula (1).

On the other hand, the "threshold voltage" of the thin film transistor refers to the gate voltage at which ^{the drain current of the transistor becomes 10 -9 A.}

In addition, "threshold voltage shift by light irradiation" means when a white LED is irradiated to a thin film transistor for 2 hours at a substrate temperature of 60°C, under a voltage condition of 10 V between the source and drain of the thin film transistor and -10 V between the gate and source. indicates the absolute value of the difference in threshold voltage before and after irradiation of

As described above, the thin film transistor using the oxide semiconductor thin film has a relatively low manufacturing cost and high carrier mobility and light stress resistance. Moreover, by using the said sputtering target, manufacturing cost is comparatively low, and the oxide semiconductor thin film with high carrier mobility and light stress resistance can be formed.

BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic sectional drawing which shows the thin film transistor of one Embodiment of this invention formed in the substrate surface.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail, referring drawings suitably.

[Thin Film Transistor]

The said thin film transistor shown in FIG. 1 can be used for manufacture of display apparatuses, such as a next-generation large-size display and a flexible display, for example. The thin film transistor is a bottom gate transistor formed on the surface of the substrate X. The thin film transistor includes a gate electrode 1, a gate insulating film 2, an oxide semiconductor thin film 3, an ESL (Etch Stop Layer) protective film 4, source and drain electrodes 5, a passivation insulating film 6, and It has a conductive film (7).

(Board)

Although it does not specifically limit as the board|substrate X, For example, the board|substrate used for a display apparatus is mentioned. Transparent substrates, such as a glass substrate and a silicone resin substrate, are mentioned as such a board|substrate X. It does not specifically limit as glass used for the said glass substrate, For example, alkali-free glass, high strain-point glass, soda-lime glass, etc. are mentioned. In addition, as the substrate X, a metal substrate such as a stainless thin film or a resin substrate such as a polyethylene terephthalate (PET) film may be used.

As for the average thickness of the board|substrate X, 0.3 mm or more and 1.0 mm or less are preferable from a viewpoint of workability. In addition, the size and shape of the board|substrate X are suitably determined according to the size and shape of the display apparatus etc. used. Here, the "average thickness" measures the thickness of 10 arbitrary points, and points out the average value computed from them.

(gate electrode)

The gate electrode 1 is formed on the surface of the substrate X and has conductivity. Although it does not specifically limit as a thin film which comprises the gate electrode 1, What laminated|stacked thin films, such as Mo, Cu, Ti, or an alloy film, on the surface of Al alloy or Al alloy can be used.

As a lower limit of the average thickness of the gate electrode 1, 50 nm is preferable and 170 nm is more preferable. On the other hand, as an upper limit of the average thickness of the gate electrode 1, 500 nm is preferable and 400 nm is more preferable. When the average thickness of the gate electrode 1 is less than the above lower limit, since the resistance of the gate electrode 1 is large, there is a fear that power consumption in the gate electrode 1 may increase or disconnection may easily occur. Conversely, if the average thickness of the gate electrode 1 exceeds the upper limit, planarization of the gate insulating film 2 or the like laminated on the surface side of the gate electrode 1 becomes difficult, and there is a risk that the characteristics of the thin film transistor may be deteriorated. have.

On the other hand, in order to improve the coverage of the gate insulating film 2 , the cross section in the thickness direction of the gate electrode 1 may have a tapered shape extending toward the substrate X . As a taper angle, 30 degrees or more and 40 degrees or less are preferable.

(Gate Insulation Film)

The gate insulating film 2 is laminated|stacked on the surface side of the board|substrate X so that the gate electrode 1 may be covered. As the thin film constituting the gate insulating film 2 is not particularly limited, but may be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, such as Al ₂ O ₃ or Y ₂ O ₃ such as a metal oxide film. In addition, the gate insulating film 2 may have a single-layer structure of these thin films, or a multilayer structure in which two or more types of thin films are laminated|stacked may be sufficient as it.

The shape of the gate insulating film 2 is not limited as long as the gate electrode 1 is covered, and for example, the gate insulating film 2 may cover the entire surface of the substrate X.

As a lower limit of the average thickness of the gate insulating film 2, 50 nm is preferable and 100 nm is more preferable. Moreover, as an upper limit of the average thickness of the gate insulating film 2, 300 nm is preferable and 250 nm is more preferable. When the average thickness of the gate insulating film 2 is less than the lower limit, the withstand voltage of the gate insulating film 2 is insufficient, and there is a risk that the gate insulating film 2 may be broken down by application of the gate voltage. Conversely, when the average thickness of the gate insulating film 2 exceeds the above upper limit, the capacitance of the capacitor formed between the gate electrode 1 and the oxide semiconductor thin film 3 becomes insufficient, and there is a fear that the drain current becomes insufficient. On the other hand, when the gate insulating film 2 has a multilayer structure, the "average thickness of the gate insulating film" refers to the average thickness of the total.

(Oxide semiconductor thin film)

The oxide semiconductor thin film 3 itself is another embodiment of the present invention. The oxide semiconductor thin film 3 contains a metal element. In the oxide semiconductor thin film 3, the metal element consists of In, Zn, Fe and unavoidable impurities. That is, the said oxide semiconductor thin film 3 does not contain metal elements other than In, Zn, and Fe substantially.

The lower limit of the number of atoms of In with respect to the total number of atoms of In, Zn and Fe is 58 atm%, more preferably 60 atm%, and still more preferably 65 atm%. On the other hand, the upper limit of the number of atoms of In is 80 atm%, more preferably 75 atm%, and still more preferably 69 atm%. When the number of atoms of In is less than the lower limit, the carrier mobility of the thin film transistor may decrease. Conversely, when the number of atoms of In exceeds the upper limit, the leakage current of the oxide semiconductor thin film 3 increases or the threshold voltage shifts to the negative side, so there is a risk that the oxide semiconductor thin film 3 becomes conductive. have.

The lower limit of the number of atoms of Zn with respect to the total number of atoms of In, Zn and Fe is 19 atm%, more preferably 24 atm%, and still more preferably 30 atm%. On the other hand, the upper limit of the number of atoms of Zn is 41 atm%, more preferably 39 atm%, and still more preferably 34 atm%. When the number of atoms of Zn is less than the lower limit, the number of atoms of other metals is relatively large, so that there is a fear of becoming a conductor. Conversely, when the number of atoms of Zn exceeds the upper limit, the carrier concentration is suppressed, and there is a fear that the carrier mobility of the thin film transistor is lowered.

The lower limit of the number of atoms of Fe with respect to the total number of atoms of In, Zn, and Fe is 0.6 atm%, more preferably 0.8 atm%, and still more preferably 0.9 atm%. On the other hand, the upper limit of the number of atoms of Fe is 3 atm%, more preferably 2 atm%, and still more preferably 1.5 atm%. There exists a possibility that the threshold voltage shift by light irradiation may become large that the number of atoms of the said Fe is less than the said minimum. Conversely, when the number of atoms of Fe exceeds the upper limit, the carrier concentration is suppressed and there is a fear that the carrier mobility of the thin film transistor is lowered.

As a lower limit of the ratio (In/Fe) of the number of atoms of In to the number of atoms of Fe, 25 is preferable, 50 is more preferable, and 55 is still more preferable. On the other hand, as an upper limit of In/Fe, 100 is preferable, 80 is more preferable, and 60 is still more preferable. If In/Fe is less than the said lower limit, carrier mobility may fall. Conversely, when In/Fe exceeds the upper limit, the S value (Subthreshold Swing value, described later) of the thin film transistor may increase.

Although it does not specifically limit as a planar shape shape of the said oxide semiconductor thin film 3, From a viewpoint of the controllability of the channel length and channel width of the said thin film transistor, the shape similar to the gate electrode 1 is preferable. The size of the oxide semiconductor thin film 3 in plan view may be any size capable of ensuring the channel length and channel width of the thin film transistor.

In addition, the size of the oxide semiconductor thin film 3 in plan view is the size of the gate electrode 1 in plan view in order to ensure that the oxide semiconductor thin film 3 is disposed directly above the gate electrode 1 . It is preferably smaller than the size. The lower limit of the difference between the lengths of the sides of the oxide semiconductor thin film 3 and the gate electrode 1 in the channel direction and the channel width direction is preferably 2 nm, more preferably 4 nm. On the other hand, as an upper limit of the difference in the length of the said side, 10 nm is preferable and 8 nm is more preferable. If the difference in the lengths of the sides is less than the lower limit, a part of the oxide semiconductor thin film 3 deviates from directly above the gate electrode 1 due to patterning shift or the like, and as a result, the flatness of the oxide semiconductor thin film 3 deteriorates, There exists a possibility that the characteristic of the said thin film transistor may deteriorate. Conversely, when the difference in the lengths of the sides exceeds the upper limit, there is a fear that the thin film transistor becomes unnecessarily large.

The average thickness of the oxide semiconductor thin film 3 can be, for example, 20 nm or more and 60 nm or less.

On the other hand, in order to improve the coverage of the source and drain electrodes 5 , the cross section in the thickness direction of the oxide semiconductor thin film 3 may have a tapered shape extending toward the substrate X . As a taper angle, 30 degrees or more and 40 degrees or less are preferable.

Art oxide as the lower limit of the carrier concentration of the semiconductor thin film ^{(3), 1 × 10 12} cm -3 is preferable, and more preferably 1 × 10 ¹³ cm ^-3, and more preferably, 1 × 10 ¹⁴ cm ^-3. On the other hand, as the upper limit of the carrier concentration, 1×10 ²⁰ cm ^-3 is preferable, 1×10 ¹⁹ cm ^-3 is more preferable, and 1×10 ¹⁸ cm ^-3 is still more preferable. When the carrier concentration is less than the lower limit, the drain current of the thin film transistor may be insufficient. Conversely, since it becomes difficult to completely deplete the inside of the said oxide semiconductor thin film 3 when the said carrier concentration exceeds the said upper limit, there exists a possibility that it may not function as a switching element.

As the lower limit of the art oxide hole mobility of the semiconductor thin film 3 is also, 32cm ² / Vs is preferably, 35cm ² / Vs is more preferable and, more preferably 38cm ² / Vs. If the hole mobility is less than the lower limit, the switching characteristics of the thin film transistor may be deteriorated. In addition, the upper limit of the said hole mobility is not specifically limited. "Hall mobility" refers to carrier mobility obtained by Hall effect measurement.

(ESL protective film)

The ESL protective film 4 is a protective film that prevents the oxide semiconductor thin film 3 from being damaged and the characteristics of the thin film transistor from being deteriorated when the source and drain electrodes 5 are formed by etching. Although it does not specifically limit as a thin film which comprises the ESL protective film 4, A silicon oxide film is used suitably.

(source and drain electrodes)

The thin film constituting the source and drain electrodes 5 is not particularly limited as long as it has conductivity, and, for example, a thin film similar to that of the gate electrode 1 can be used.

As a lower limit of the average thickness of the source and drain electrodes 5, 100 nm is preferable and 150 nm is more preferable. On the other hand, as an upper limit of the average thickness of the source and drain electrodes 5, 400 nm is preferable and 300 nm is more preferable. When the average thickness of the source and drain electrodes 5 is less than the above lower limit, since the resistance of the source and drain electrodes 5 is large, there is a risk of increased power consumption in the source and drain electrodes 5 or disconnection easily occurs. There is a risk of quality. Conversely, when the average thickness of the source and drain electrodes 5 exceeds the upper limit, planarization of the passivation insulating film 6 becomes difficult, and there is a fear that wiring by the conductive film 7 becomes difficult.

(Passivation Insulation Film)

The passivation insulating film 6 covers the gate electrode 1 , the gate insulating film 2 , the oxide semiconductor thin film 3 , the ESL protective film 4 , the source electrode 5a and the drain electrode 5b , and the thin film transistor to prevent deterioration of its properties. Although it does not specifically limit as a thin film which comprises the passivation insulating film 6, A silicon nitride film whose sheet resistance is comparatively easy to control by hydrogen content is used suitably. Further, in order to further improve the controllability of the sheet resistance, the passivation insulating film 6 may have a two-layer structure of, for example, a silicon oxide film and a silicon nitride film.

As a lower limit of the average thickness of the passivation insulating film 6, 100 nm is preferable and 250 nm is more preferable. On the other hand, as an upper limit of the average thickness of the passivation insulating film 6, 500 nm is preferable and 300 nm is more preferable. When the average thickness of the passivation insulating film 6 is less than the said lower limit, there exists a possibility that the deterioration prevention effect of the characteristic of the said thin film transistor may run short. Conversely, when the average thickness of the passivation insulating film 6 exceeds the above upper limit, the passivation insulating film 6 becomes unnecessarily thick, and there is a fear that an increase in the manufacturing cost of the thin film transistor or a decrease in production efficiency may occur. On the other hand, when the passivation insulating film 6 has a multilayer structure, the "average thickness of the passivation insulating film" refers to the average thickness of the total.

(conductive film)

The conductive film 7 is connected to the drain electrode 5b through a contact hole 8 drilled in the passivation insulating film 6 . A wiring for acquiring a drain current from the thin film transistor is constituted by the conductive film 7 .

Although it does not specifically limit as the conductive film 7, A transparent conductive film suitable for application to a display is preferable. As such a transparent conductive film, an ITO film, a ZnO film, etc. are mentioned.

The position where the conductive film 7 connects to the drain electrode 5b is preferably a position where the drain electrode 5b contacts the gate insulating film 2 and not directly above the gate electrode 1 . By connecting the conductive film 7 to the drain electrode 5b at such a position, the flatness of the connection portion between the conductive film 7 and the drain electrode 5b is increased, so that an increase in the contact resistance can be suppressed.

As a lower limit of the average wiring width of the conductive film 7, 5 micrometers is preferable and 10 micrometers is more preferable. On the other hand, as an upper limit of the average wiring width of the conductive film 7, 50 micrometers is preferable and 30 micrometers is more preferable.

As a lower limit of the average thickness of the conductive film 7, 50 nm is preferable and 80 nm is more preferable. On the other hand, as an upper limit of the average thickness of the conductive film 7, 200 nm is preferable and 150 nm is more preferable.

(Characteristics of thin film transistors)

As the lower limit of the carrier mobility (electron mobility) of such a thin film transistor, 32cm ² / Vs is preferably, 35cm ² / Vs is more preferable and, more preferably 38cm ² / Vs. There exists a possibility that the switching characteristic of the said thin film transistor may fall that the carrier mobility of the said thin film transistor is less than the said minimum. In addition, although it does not specifically limit as an upper limit of the carrier mobility of the said thin film transistor, Usually, the carrier mobility of the said thin film transistor is 100 cm<^2> /Vs or less.

As a lower limit of the threshold voltage of the said thin film transistor, -1V is preferable and 0V is more preferable. On the other hand, as an upper limit of the threshold voltage of the said thin film transistor, 3V is preferable and 2V is more preferable. When the threshold voltage of the said thin film transistor is less than the said lower limit, the leakage current in the OFF state as a switching element which does not apply a voltage to the gate electrode 1 may become large, and there exists a possibility that the standby power of the said thin film transistor may become large too much. Conversely, when the threshold voltage of the thin film transistor exceeds the above upper limit, there is a fear that the drain current in the ON state as a switching element in which a voltage is applied to the gate electrode 1 may become insufficient.

As an upper limit of the threshold voltage shift by light irradiation of the said thin film transistor, 5V is preferable, 3V is more preferable, and 2V is still more preferable. When the said threshold voltage shift exceeds the said upper limit, when the said thin-film transistor is used for a display device, the performance of the said thin-film transistor is not stable, and there exists a possibility that the required switching characteristic may not be acquired. As a lower limit of the said threshold voltage shift, it is preferable that 0V, ie, the said threshold voltage shift, does not generate|occur|produce.

As an upper limit of the S value (Subthreshold Swing value) of the said thin film transistor, 0.7V is preferable and 0.5V is more preferable. When the S value of the said thin film transistor exceeds the said upper limit, there exists a possibility that switching of the said thin film transistor may require time. In addition, although it does not specifically limit as a lower limit of the S value of the said thin film transistor, Usually, S value of the said thin film transistor is 0.2V or more. Here, the "S value" of the thin film transistor refers to the minimum value of the amount of change in the gate voltage required to increase the drain current by one digit.

[Manufacturing method of thin film transistor]

The thin film transistor is, for example, a gate electrode film forming process, a gate insulating film forming process, an oxide semiconductor thin film forming process, an ESL protective film forming process, a source and drain electrode film forming process, a passivation insulating film forming process, a conductive film forming process, and a post annealing process. It can be manufactured by a manufacturing method comprising

<Gate electrode film forming process>

In the gate electrode film-forming process, the gate electrode 1 is formed into a film on the surface of the board|substrate X. As shown in FIG.

Specifically, first, a conductive film is laminated on the surface of the substrate X by a known method, for example, a sputtering method to a desired film thickness. The conditions at the time of the conductive laminated film by a sputtering method is not particularly limited, for example, a substrate temperature of 20 ℃ 50 ℃ or less, the deposition power density of 3W / cm ² more than 4W / cm ² or less, or more pressure 0.1Pa 0.4Pa Hereinafter, it can be set as the conditions of carrier gas Ar.

Next, the gate electrode 1 is formed by patterning this conductive film. Although it does not specifically limit as a method of patterning, For example, after performing photolithography, the method of performing wet etching can be used. At this time, the end face of the gate electrode 1 may be etched in a tapered shape extending toward the substrate X so that the coverage of the gate insulating film 2 is improved.

<Gate Insulation Film Formation Process>

In the gate insulating film forming step, the gate insulating film 2 is formed on the surface side of the substrate X so as to cover the gate electrode 1 .

Specifically, first, an insulating film is laminated to a desired film thickness on the surface side of the substrate X by a known method, for example, various CVD methods. For example, in the case of laminating a silicon oxide film by plasma CVD, the substrate temperature is 300°C or more and 400°C or less, the film-forming power density is 0.7W/cm ² or more and 1.3W/cm ² or less, and the pressure is 100Pa or more and 300Pa or less. , by using a mixed _{gas of N 2} O and SiH ₄ as the source gas.

<Oxide semiconductor thin film formation process>

In the oxide semiconductor thin film forming step, the oxide semiconductor thin film 3 is formed on the surface of the gate insulating film 2 and directly on the gate electrode 1 . Specifically, after laminating an oxide semiconductor layer on the surface of the substrate X, the oxide semiconductor layer is patterned to form the oxide semiconductor thin film 3 .

(Lamination of oxide semiconductor layers)

First, the oxide semiconductor layer is laminated|stacked on the surface of the board|substrate X by the sputtering method using a well-known sputtering apparatus, for example. By using the sputtering method, an oxide semiconductor layer excellent in the in-plane uniformity of its components and film thickness can be easily formed.

The sputtering target used for the sputtering method itself is another embodiment of this invention. That is, the said sputtering target is a sputtering target used for formation of the said oxide semiconductor thin film 3, The said metal element consists of In, Zn, Fe, and an unavoidable impurity. Specific examples of the sputtering target include an oxide target (IZFO target) containing In, Zn, and Fe.

The lower limit of the number of atoms of In with respect to the total number of atoms of In, Zn, and Fe of the sputtering target is 58 atm%, more preferably 60 atm%, and still more preferably 65 atm%. On the other hand, the upper limit of the number of atoms of In is 80 atm%, more preferably 75 atm%, and still more preferably 69 atm%. The lower limit of the number of atoms of Zn with respect to the total number of atoms of In, Zn and Fe is 19 atm%, more preferably 24 atm%, and still more preferably 30 atm%. On the other hand, the upper limit of the number of atoms of Zn is 41 atm%, more preferably 39 atm%, and still more preferably 34 atm%. Moreover, as a lower limit of the number of atoms of Fe with respect to the total number of atoms of In, Zn, and Fe, it is 0.6 atm%, 0.8 atm% is more preferable, and 0.9 atm% is still more preferable. On the other hand, the upper limit of the number of atoms of Fe is 3 atm%, more preferably 2 atm%, and still more preferably 1.5 atm%. By forming the said oxide semiconductor thin film 3 into a film using the said sputtering target, manufacturing cost is comparatively low, and the said thin film transistor with high carrier mobility and light stress resistance can be manufactured.

It is preferable that the said sputtering target sets it as the desired oxide semiconductor layer and the same composition. Thus, by making the composition of the said sputtering target the same as that of a desired oxide semiconductor layer, since the composition shift of the oxide semiconductor layer to be formed can be suppressed, it is easy to obtain the oxide semiconductor layer which has a desired composition.

Although it does not specifically limit as conditions at the time of laminating|stacking an oxide semiconductor layer by sputtering method, For example, A board|substrate temperature 20 degreeC or more and 50 degrees C or less, film-forming power density 2 W/cm ² or more 3 W/cm ² or less, and a pressure of 0.1 Pa or more. It can be set as the conditions of 0.3 Pa or less or carrier gas Ar. Moreover, what is necessary is just to contain oxygen in atmosphere as an oxygen source. As content of oxygen in atmosphere, it can be set as 3 volume% or more and 5 volume% or less.

(patterning)

Next, the oxide semiconductor thin film 3 is formed by patterning the oxide semiconductor layer.

On the other hand, you may perform a pre-annealing process after patterning, and you may reduce the density of the trap level of the said oxide semiconductor thin film 3 . Thereby, the threshold voltage shift by light irradiation of the thin film transistor manufactured by this can be reduced.

As a lower limit of the temperature of a pre-annealing process, 300 degreeC is preferable and 350 degreeC is more preferable. On the other hand, as an upper limit of the temperature of an annealing process, 450 degreeC is preferable and 400 degreeC is more preferable.

And pressure conditions of the time of the pre-annealing treatment is not particularly limited, for example, in N ₂ atmosphere at atmospheric pressure (0.9 atm 1.1 atm or less), it is possible to use the time conditions of 60 minutes or less 10 minutes or more.

<ESL protective film forming process>

In the ESL protective film forming step, the ESL protective film 4 is formed on the surface of the oxide semiconductor thin film 3 where the source and drain electrodes 5 are not formed.

Specifically, first, an insulating film is laminated to a desired film thickness on the surface side of the substrate X by a known method, for example, various CVD methods. For example, and with a substrate temperature of more than ² 100 ℃ more than 300 ℃ or less, film forming 0.2W / cm power density of 0.5W / cm ² or less, more than 100Pa pressure condition of 300Pa or less if the case of laminating a silicon oxide film by plasma CVD , by using a mixed _{gas of N 2} O and SiH ₄ as the source gas.

<Source and drain electrode film formation process>

In the source and drain electrode film forming step, a source electrode 5a and a drain electrode 5b that are electrically connected to the oxide semiconductor thin film 3 at both ends of the channel of the thin film transistor are formed.

〔advantage〕

In the oxide semiconductor thin film 3, the number of atoms of In is 58 atm% or more and 80 atm% or less, and the number of atoms of Zn is 19 atm% or more and 41 atm% or less with respect to the total number of atoms of In, Zn and Fe, and Fe atoms Since the number is 0.6 atm% or more, it has high light stress resistance. Moreover, since the said oxide semiconductor thin film 3 makes the number of atoms of Fe 3 atm% or less, carrier mobility at the time of forming a thin film transistor using the said oxide semiconductor thin film 3 is high. Moreover, since the said oxide semiconductor thin film 3 does not need to contain Ga, manufacturing cost can be reduced.

Example

Hereinafter, the present invention will be described in detail based on Examples, but the present invention is not to be construed as being limited based on the description of these Examples.

[Example 1]

A glass substrate ("EagleXG" manufactured by Corning Corporation, 6 inches in diameter, 0.7 mm in thickness) was prepared, and first, a Mo thin film was formed on the surface of this glass substrate so that the average thickness might be 100 nm. Film-forming conditions were made into the substrate temperature of 25 degreeC (room temperature), the film-forming power density of 3.8 W/cm<^2> , the pressure of 0.266 Pa, and carrier gas Ar. After the Mo thin film was formed, a gate electrode was formed by patterning.

Next, as a gate insulating film, a silicon oxide film having an average thickness of 250 nm was formed by CVD to cover the gate electrode. As the raw material gas, a mixed gas of _{N 2} O and SiH _{4 was used.} The film formation conditions were a substrate temperature of 320°C, a film formation power density of 0.96 W/cm ^{2 ,} and a pressure of 133 Pa.

Next, an oxide semiconductor layer having an average thickness of 40 nm and substantially containing only In, Zn, and Fe as metal elements as an oxide semiconductor layer was formed on the surface side of the glass substrate by sputtering.

For the sputtering method, a method established conventionally as a method of investigating the optimum composition ratio was used. Specifically, _{three targets of In 2} O ₃ , ZnO, and In ₂ O ₃ equipped with an Fe chip are arranged at different positions around the glass substrate, and sputtering is performed on the stopped glass substrate. By doing so, an oxide semiconductor layer was formed into a film. According to such a method, since three targets from which a structural element differs are arrange|positioned at the different positions around a glass substrate, the distance from each target differs with the position on a glass substrate. Since the element supplied from the target decreases as it moves away from the sputtering target, for example, at a position close to the ZnO target and _{far from the In 2} O ₃ target, Zn increases compared to In, and conversely, close to the _{In 2} O _{3 target and ZnO} At a position farther from the target, In is greater than that of Zn. That is, the oxide semiconductor layer from which a composition ratio differs according to the position on a glass substrate can be obtained.

Using a sputtering apparatus ("CS200" manufactured by Ulbak Co., Ltd.), the film formation conditions were a substrate temperature of 25°C (room temperature), a film formation power density of 2.55 W/cm ² , a pressure of 0.133 Pa, and a carrier gas Ar. In addition, the oxygen content of the atmosphere was made into 4 volume%.

The obtained oxide semiconductor layer was patterned by photolithography and wet etching, and the oxide semiconductor thin film from which a composition differs according to the position on a glass substrate was formed. In addition, "ITO-07N" manufactured by Kanto Chemical Co., Ltd. was used for the wet etchant.

Here, in order to improve the film quality of this oxide semiconductor thin film, the pre-annealing process was performed. In addition, the conditions of a pre-annealing process were made into 60 minutes in the environment of 350 degreeC in atmospheric atmosphere (atmospheric pressure).

Next, a silicon oxide film was formed on the surface side of the glass substrate by CVD so that the average thickness might be 100 nm. As the raw material gas, a mixed gas of _{N 2} O and SiH _{4 was used.} Film-forming conditions were made into 230 degreeC of board|substrate temperature, film-forming power density 0.32 W/cm<^2>, and pressure 133 Pa. After the silicon oxide film was formed, an ESL protective film was formed by patterning.

Next, the Mo thin film was formed into a film on the surface side of a glass substrate so that an average thickness might be set to 200 nm. Film-forming conditions were made into the substrate temperature of 25 degreeC (room temperature), the film-forming power density of 3.8 W/cm<^2> , the pressure of 0.266 Pa, and carrier gas Ar. After the Mo thin film was formed, a source electrode and a drain electrode were formed by patterning.

Next, a passivation insulating film having a two-layer structure of a silicon oxide film (average thickness of 100 nm) and a silicon nitride film (average thickness of 150 nm) was formed on the surface side of the glass substrate by the CVD method. _{As the source gas, a mixed gas of N 2} O and SiH ₄ was used to form the silicon oxide film, and a mixed gas of NH ₃ and SiH ₄ was used to form the silicon nitride film. The film formation conditions were a substrate temperature of 150°C, a film formation power density of 0.32 W/cm ^{2 ,} and a pressure of 133 Pa.

Next, a contact hole was formed by photolithography and dry etching, and a pad for electrically connecting to the drain electrode was provided. Electrical measurement of the thin film transistor is performed by placing a probe on this pad.

Finally, a post-annealing process was performed. On the other hand, the conditions of the post-annealing treatment, and in N ₂ atmosphere at atmospheric pressure and 30 minutes in the environment of 250 ℃.

In this way, the thin film transistor of Example 1 was obtained. In addition, the channel length of this thin film transistor was set to 20 micrometers, and the channel width was set to 200 micrometers. In addition, the composition of the oxide semiconductor thin film in the thin film transistor of Example 1 was as shown in Table 1.

[Examples 2 to 4, Comparative Examples 1 to 5]

The number of atoms of In, Zn, and Fe with respect to the total number of atoms of In, Zn and Fe of the sputtering target used, that is, the number of atoms of In, Zn and Fe with respect to the total number of atoms of In, Zn, and Fe of the oxide semiconductor thin film to be formed Except having changed as shown in Table 1, it carried out similarly to Example 1, and obtained the thin film transistors of Examples 2-4 and Comparative Examples 1-5.

[How to measure]

About the thin film transistors of Examples 1-4 and Comparative Examples 1-5, carrier mobility, threshold voltage, threshold voltage shift, and S value were measured.

Among these measurements, the measurement of carrier mobility, threshold voltage, and S value were all computed from the positive characteristics (Id-Vg characteristics) of the thin film transistor of the transistor. The measurement of the said static characteristic was performed using the semiconductor parameter analyzer ("HP4156C" manufactured by Agilent Technology). As the measurement conditions, the source voltage was fixed at 0 V, the drain voltage was fixed at 10 V, and the gate voltage was changed from -30 V to 30 V at 0.25 V intervals. In addition, the measurement was performed at room temperature (25 degreeC). Below, the calculation method of carrier mobility, threshold voltage, and S value from the said positive characteristic is described.

<Carrier mobility>

The carrier mobility was defined as the field-effect mobility μ _FE [m ² /Vs] in the saturated region of the positive characteristics. This field-effect mobility μ _FE [m ² /Vs] was calculated according to the above formula (1). A result is shown in Table 1.

<Threshold voltage>

The threshold voltage was a value calculated from the positive characteristics of the thin film transistor at a gate voltage at which the drain current of the transistor was 10 ^{−9 A.} A result is shown in Table 1.

<S value>

For the S value, the amount of change in the gate voltage required to raise the drain current by one digit was calculated from the above-mentioned positive characteristics, and it was set as the minimum value. A result is shown in Table 1.

<Threshold voltage shift>

Threshold voltage shift is performed at a substrate temperature of 60°C, with a source voltage of 0 V, a drain voltage of 10 V, and a gate voltage of -10 V of the thin film transistor, and a white LED (“LXHL-PW01” manufactured by PHILIPTS) is applied to the thin film transistor by 2 Time was investigated, and it computed as the absolute value of the difference of the threshold voltage before and behind irradiation. It can be said that light stress tolerance is so high that this numerical value is small. A result is shown in Table 1.

[Judgment]

Comprehensive judgment was performed on the basis of the above-described measurement results in accordance with the following criteria. A result is shown in Table 1.

A: The carrier mobility is 32 m ² /Vs or more, and the threshold voltage shift is 5 V or less, making it suitable for next-generation large-scale displays and flexible displays.

B: The carrier mobility is ^{less than 32m 2} /Vs, or the threshold voltage shift is more than 5V, so it cannot be used for next-generation large-scale displays or flexible displays.

From Table 1, the thin film transistors of Examples 1-4 have high carrier mobility and a small threshold voltage shift. On the other hand, since the thin film transistor of Comparative Example 1 has a small number of In atoms relative to the total number of In, Zn and Fe atoms of the oxide semiconductor thin film, it is considered that the carrier mobility is low, and the switching operation is inferior. Moreover, since the oxide semiconductor thin film does not contain Fe, the thin film transistor of Comparative Examples 2 and 3 is considered to have a large threshold voltage shift, and is inferior to light stress resistance. Since the thin film transistor of Comparative Example 4 has a small number of Fe atoms relative to the total number of In, Zn, and Fe atoms of the oxide semiconductor thin film, it is thought that the threshold voltage shift is large, and the light stress resistance is inferior. Since the thin film transistor of Comparative Example 5 has many Fe atoms, it is considered that the carrier mobility is low, and the switching operation is inferior.

From the above, with respect to the total number of atoms of In, Zn and Fe of the oxide semiconductor thin film, the number of atoms of In is 58 atm% or more and 80 atm% or less, the number of atoms of Zn is 19 atm% or more and 41 atm% or less, and the number of atoms of Fe is 0.6 atm % or more and 3 atm% or less, it turns out that carrier mobility and light stress resistance can be improved.

As described above, the thin film transistor using the oxide semiconductor thin film has a relatively low manufacturing cost and high carrier mobility and light stress resistance. Therefore, the said thin film transistor can be used suitably for the large-size display of the next generation, for example in which high speed is calculated|required. Moreover, by using the said sputtering target, manufacturing cost is comparatively low, and the oxide semiconductor thin film with high carrier mobility and light stress resistance can be formed.

1 gate electrode
2 gate insulating film
3 Oxide semiconductor thin film
4 ESL Shield
5 Source and drain electrodes
5a source electrode
5b drain electrode
6 passivation insulating film
7 conductive film
8 contact hole
X board

Claims (6)

As an oxide semiconductor thin film containing a metal element,
The metal element consists of In, Zn, Fe and unavoidable impurities,
For the total number of atoms of In, Zn and Fe,
The number of atoms of In is 58atm% or more and 80atm% or less,
The number of atoms of Zn is 19atm% or more and 41atm% or less;
The number of Fe atoms is 0.6 atm% or more and 1.5 atm% or less
and an oxide semiconductor thin film used in a display device. A thin film transistor comprising the oxide semiconductor thin film according to claim 1 . 3. The method of claim 2,
A thin film transistor whose threshold voltage shift by light irradiation is 5 V or less. 4. The method of claim 2 or 3,
Thin film transistors with carrier mobility of 32 cm ² /Vs or higher. A sputtering target containing a metal element and used for forming an oxide semiconductor thin film used in a display device, the sputtering target comprising:
The metal element consists of In, Zn, Fe and unavoidable impurities,
For the total number of atoms of In, Zn and Fe,
The number of atoms of In is 58atm% or more and 80atm% or less,
The number of atoms of Zn is 19atm% or more and 41atm% or less;
The number of Fe atoms is 0.6 atm% or more and 1.5 atm% or less
In sputtering target. delete

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