TWI834014B - Oxide semiconductor films, thin film transistors and sputtering targets - Google Patents

Abstract

The present invention obtains a thin film transistor which has excellent field effect mobility and stress tolerance, and has excellent wet etching processability relative to the wet etching liquid used when processing an oxide semiconductor layer, and The oxide semiconductor layer has excellent wet etching resistance with respect to the wet etching liquid used when patterning the source/drain electrodes. The oxide semiconductor thin film contains In, Ga, Zn, Sn, and O, and the atomic ratio of each metal element satisfies 0.070≦In/(In+Ga+ with respect to the total atomic ratio of In, Ga, Zn, and Sn Zn+Sn)≦0.200, 0.250≦Ga/(In+Ga+Zn+Sn)≦0.600, 0.180≦Zn/(In+Ga+Zn+Sn)≦0.550, 0.030≦Sn/(In+Ga+Zn+ Sn)≦0.150, and satisfy 0.10≦Sn/Zn≦0.25 and (Sn×In)/Ga≧0.009.

Description

Oxide semiconductor films, thin film transistors and sputtering targets

The present invention relates to an oxide semiconductor thin film suitably used in a display device such as a liquid crystal display or an organic electroluminescence (EL) display, and a thin film electronic device including an oxide semiconductor layer including the oxide semiconductor thin film. Crystal (Thin Film Transistor, TFT). In addition, the present invention relates to a sputtering target for forming an oxide semiconductor layer including the oxide semiconductor thin film.

As an amorphous oxide semiconductor, as shown in Patent Document 1, an In-Ga-Zn-based oxide containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) is known Semiconductor (Indium Gallium Zinc Oxide, IGZO). [Prior art documents] [Patent Document]

[Patent Document 1] Japanese Patent Application Laid-Open No. 2010-219538

[Problem to be solved by the invention] Oxide semiconductors can be used in channel layers of thin film transistors constituting electronic circuits such as display devices that require high resolution and high-speed driving. Thin film transistors using an oxide semiconductor thin film are required to have excellent resistance (stress resistance) against stress such as light irradiation or voltage application. If the stress tolerance is low, the threshold voltage of the transistor shifts or deviates, resulting in reduced reliability of the display device itself.

Furthermore, when fabricating a thin film transistor including a source/drain electrode on an oxide semiconductor film, the oxide semiconductor film is also required to have high characteristics with respect to a chemical solution such as a wet etching solution ( Wet etching resistance). Specifically, the following two characteristics are required.

(i) The oxide semiconductor thin film has excellent solubility in the wet etching liquid for oxide semiconductor processing (excellent wet etching processability) That is, it is required that the oxide semiconductor thin film be etched at an appropriate speed by an organic acid-based or inorganic acid-based wet etching solution such as oxalic acid used when processing the oxide semiconductor thin film without residue. Patterning. (ii) The oxide semiconductor thin film is insoluble in the source/drain electrode wet etching liquid (excellent in wet etching resistance)

An object of the present invention is to provide an oxide semiconductor transistor, which has excellent field-effect mobility and stress tolerance, and is superior to a wet etching solution used when processing an oxide semiconductor layer. An oxide semiconductor of a thin film transistor that has wet etching processability and an oxide semiconductor layer that has excellent wet etching resistance with respect to the wet etching liquid used when patterning the source/drain electrodes. A thin film, a thin film transistor including the oxide semiconductor layer, and a sputtering target used to form the oxide semiconductor layer.

[Means to solve the problem] The inventors of the present invention have conducted diligent research and found that by using an oxide semiconductor thin film containing In, Ga, Zn, Sn, and O as metal elements and appropriately controlling the composition of each metal element, it is possible to This invention was completed by solving the said subject.

That is, the object of the present invention can be achieved by the following structure [1] regarding the oxide semiconductor thin film. [1] An oxide semiconductor thin film containing In, Ga, Zn and Sn as metal elements, and O, and With respect to the total number of atoms of In, Ga, Zn, and Sn, the atomic number ratio of each metal element satisfies 0.070≦In/（In+Ga+Zn+Sn）≦0.200 0.250≦Ga/（In+Ga+Zn+Sn）≦0.600 0.180≦Zn/(In+Ga+Zn+Sn)≦0.550 0.030≦Sn/(In+Ga+Zn+Sn)≦0.150, and Relative to the atomic number ratio of Zn, the atomic number ratio of Sn satisfies 0.10≦Sn/Zn≦0.25, and The atomic number ratio of Sn, In and Ga satisfies (Sn×In)/Ga≧0.009.

In addition, the above object of the present invention can be achieved by the following structure [2] related to the thin film transistor. [2] A thin film transistor having a gate electrode, a gate insulating film, a second oxide semiconductor layer, a first oxide semiconductor layer, a source/drain electrode and a protective film in order on a substrate, and Among the above-mentioned thin film transistors, The first oxide semiconductor layer contains In, Ga, Zn and Sn as metal elements, and O, and With respect to the total number of atoms of In, Ga, Zn, and Sn, the atomic number ratio of each metal element satisfies 0.070≦In/（In+Ga+Zn+Sn）≦0.200 0.250≦Ga/（In+Ga+Zn+Sn）≦0.600 0.180≦Zn/(In+Ga+Zn+Sn)≦0.550 0.030≦Sn/(In+Ga+Zn+Sn)≦0.150, and Relative to the atomic number ratio of Zn, the atomic number ratio of Sn satisfies 0.10≦Sn/Zn≦0.25, and The atomic number ratio of Sn, In and Ga satisfies (Sn×In)/Ga≧0.009.

In addition, preferred embodiments of the present invention related to thin film transistors are as follows [3]. [3] The thin film transistor according to [2], wherein the source/drain electrode is directly connected to the first oxide semiconductor layer, and the source/drain electrode contains Cu or Cu alloy.

In addition, the above object of the present invention can be achieved by the following structure [4] related to the sputtering target. [4] A sputtering target used to form the first oxide semiconductor layer in the thin film transistor according to [2] or [3], and The sputtering target contains In, Ga, Zn and Sn as metal elements, and O, and With respect to the total number of atoms of In, Ga, Zn, and Sn, the atomic number ratio of each metal element satisfies 0.070≦In/（In+Ga+Zn+Sn）≦0.200 0.250≦Ga/(In+Ga+Zn+Sn)≦0.600 0.180≦Zn/（In+Ga+Zn+Sn）≦0.550 0.030≦Sn/(In+Ga+Zn+Sn)≦0.150, and Relative to the atomic number ratio of Zn, the atomic number ratio of Sn satisfies 0.10≦Sn/Zn≦0.25, and The atomic number ratio of Sn, In and Ga satisfies (Sn×In)/Ga≧0.009.

[Effects of the invention] According to the present invention, it is possible to provide an oxide semiconductor transistor that is excellent in field-effect mobility and stress tolerance, and has excellent properties compared to a wet etching liquid used when processing an oxide semiconductor layer. An oxide semiconductor of a thin film transistor that has wet etching processability and an oxide semiconductor layer that has excellent wet etching resistance with respect to the wet etching liquid used when patterning the source/drain electrodes. Thin films, thin film transistors and sputtering targets.

Hereinafter, the oxide semiconductor thin film and the thin film transistor according to the embodiment of the present invention will be described.

The oxide semiconductor thin film of this embodiment contains In, Ga, Zn and Sn as metal elements, and O, and With respect to the total number of atoms of In, Ga, Zn, and Sn, the atomic number ratio of each metal element satisfies 0.070≦In/（In+Ga+Zn+Sn）≦0.200 0.250≦Ga/（In+Ga+Zn+Sn）≦0.600 0.180≦Zn/(In+Ga+Zn+Sn)≦0.550 0.030≦Sn/(In+Ga+Zn+Sn)≦0.150, and Relative to the atomic number ratio of Zn, the atomic number ratio of Sn satisfies 0.10≦Sn/Zn≦0.25, and The atomic number ratio of Sn, In and Ga satisfies (Sn×In)/Ga≧0.009.

In addition, the thin film transistor of this embodiment has a gate electrode, a gate insulating film, a second oxide semiconductor layer, a first oxide semiconductor layer, a source/drain electrode and a protective film in order on the substrate, and the Among the above-mentioned thin film transistors, The first oxide semiconductor layer contains In, Ga, Zn and Sn as metal elements, and O, and With respect to the total number of atoms of In, Ga, Zn, and Sn, the atomic number ratio of each metal element satisfies 0.070≦In/（In+Ga+Zn+Sn）≦0.200 0.250≦Ga/(In+Ga+Zn+Sn)≦0.600 0.180≦Zn/（In+Ga+Zn+Sn）≦0.550 0.030≦Sn/(In+Ga+Zn+Sn)≦0.150, and Relative to the atomic number ratio of Zn, the atomic number ratio of Sn satisfies 0.10≦Sn/Zn≦0.25, and The atomic number ratio of Sn, In and Ga satisfies (Sn×In)/Ga≧0.009.

In addition, in this embodiment, the oxide containing In, Ga, Zn, Sn, and O may be called "IGZTO". In addition, the contents (atomic number ratios) of In, Ga, Zn, and Sn relative to the total number of atoms of all metal elements (In, Ga, Zn, and Sn) except O are sometimes referred to as "In atoms." "Number ratio", "Ga atomic number ratio", "Zn atomic number ratio" and "Sn atomic number ratio".

＜Oxide semiconductor thin film＞ Hereinafter, the oxide semiconductor thin film of this embodiment (or the first oxide semiconductor layer in the thin film transistor described below) will be described.

[0.070≦In/(In+Ga+Zn+Sn)≦0.200] In is an element that contributes to improving electrical conductivity. The greater the In atomic number ratio, that is, the greater the amount of In in all metal elements, the more conductive the oxide semiconductor layer is, so the field effect mobility is increased.

In order to effectively exert the above effect, the In atomic number ratio needs to be 0.070 or more. The In atomic number ratio is preferably 0.080 or more, more preferably 0.100 or more. However, if the In atomic number ratio is too large, there are problems such as an excessive increase in carrier density and a decrease in the threshold voltage. Therefore, the In atomic number ratio is set to 0.200 or less. The In atomic number ratio is preferably 0.150 or less, more preferably 0.130 or less.

[0.250≦Ga/(In+Ga+Zn+Sn)≦0.600] Ga is an element that helps reduce oxygen vacancies and control carrier density. The greater the Ga atomic ratio, that is, the greater the amount of Ga in all metal elements, the more the electrical stability of the oxide semiconductor layer is improved and the effect of suppressing excessive generation of carriers is exerted. In addition, Ga is also an element that inhibits etching using a hydrogen peroxide-based Cu etching solution. Therefore, the greater the Ga atomic ratio, the greater the selectivity with respect to the hydrogen peroxide-based etching liquid used in the etching process of the Cu electrode serving as the source/drain electrode, and the less likely it is to be damaged.

In order to effectively exert the above effects, the Ga atomic number ratio needs to be 0.250 or more. The Ga atomic number ratio is preferably 0.300 or more, more preferably 0.410 or more. However, if the Ga atomic ratio is too large, the conductivity of the oxide semiconductor layer decreases and the field-effect mobility tends to decrease. In addition, the electrical conductivity of the sputtering target used to form the oxide semiconductor layer decreases, and it is difficult to stably continue direct current discharge. Therefore, the Ga atomic number ratio is set to 0.600 or less. The Ga atomic number ratio is preferably 0.500 or less, more preferably 0.450 or less.

[0.180≦Zn/(In+Ga+Zn+Sn)≦0.550] Zn is not as sensitive to the characteristics of thin film transistors as other metal elements. However, the greater the Zn atomic ratio, that is, the greater the amount of Zn in all metal elements, the easier it is to amorphize, so it is easily amorphized by organic acids or Etching with inorganic acid etching solution.

In order to effectively exert the above effects, the Zn atomic number ratio needs to be 0.180 or more. The Zn atomic number ratio is preferably 0.300 or more, more preferably 0.350 or more. However, if the Zn atomic ratio is too large, the solubility of the oxide semiconductor layer in the source/drain electrode etching liquid becomes high, and as a result, the wet etching resistance may easily deteriorate, or the relative decrease in In may occur. The field effect mobility is reduced, or the electrical stability of the oxide semiconductor layer is easily reduced due to the relative reduction of Ga. Therefore, the Zn atomic number ratio is set to 0.550 or less. The Zn atomic number ratio is preferably 0.500 or less, more preferably 0.400 or less.

[0.030≦Sn/(In+Ga+Zn+Sn)≦0.150] Sn is an element that inhibits etching using an acid-based chemical solution. Therefore, the greater the Sn atomic number ratio, that is, the greater the amount of Sn in all metal elements, the more difficult it is to etch the oxide semiconductor layer using an organic acid or inorganic acid etching solution used for patterning. . On the other hand, an oxide semiconductor to which Sn is added exhibits an increase in carrier density due to hydrogen diffusion, resulting in an increase in field-effect mobility. In addition, if the Sn addition amount is appropriate, the reliability of the thin film transistor against light stress will be reduced. sexual enhancement.

In order to effectively exert the above effect, the Sn atomic number ratio needs to be 0.030 or more. The number of Sn atoms is preferably 0.060 or more, more preferably 0.070 or more. On the other hand, if the Sn atomic number ratio is too large, the resistance of the oxide semiconductor layer to the etching liquid of organic acid or inorganic acid increases beyond necessity, making it difficult to process the oxide semiconductor layer itself. In addition, there is a risk that the reliability against light stress may be reduced because it is strongly affected by hydrogen diffusion. Therefore, the Sn atomic number ratio is set to 0.150 or less. The number of Sn atoms is preferably 0.110 or less, more preferably 0.080 or less.

[0.10≦Sn/Zn≦0.25] The etching resistance of the oxide semiconductor layer with respect to the organic acid or inorganic acid etching liquid used for patterning changes depending on the In/Ga atomic ratio. Even if the In/Ga atomic ratio is At any value, etching resistance can also be improved by increasing the amount of Sn added. In addition, by increasing the amount of Sn added, it is possible to prevent Zn from being detached from the oxide semiconductor layer when the heat treatment of the oxide semiconductor layer is increased to a high temperature when manufacturing a thin film transistor.

The detachment of Zn occurs because hydrogen in the oxide semiconductor layer is detached due to the increase in temperature during the heat treatment, and the bonding force between Zn and O is weakened accordingly. As described above, when the metal atoms (Zn) on the surface of the oxide semiconductor layer are detached, the composition in the oxide semiconductor layer and on the surface of the layer changes. In particular, the surface of the oxide semiconductor layer becomes a Zn-vacant state. Therefore, it is easily assumed that the Zn-vacant site becomes a Cu diffusion source from the Cu electrode formed on the oxide semiconductor layer.

The change in the amount of Zn in the oxide semiconductor film affects the etching resistance of the oxide semiconductor layer to the etching solution of organic acid or inorganic acid and the detachment of metal atoms (Zn) along with the amount of Sn added. different. The diffusion of Cu is caused by both the etching resistance of the cap layer and the detachment of metal atoms, so it is determined by adjusting the Zn amount and the Sn/Zn atomic ratio of the oxide semiconductor film. With proper adjustment, excellent TFT characteristics can be obtained.

In order to prevent the diffusion of Cu as described above, it is necessary to satisfy Sn/Zn≧0.10. In addition, it is preferable to satisfy Sn/Zn≧0.18. On the other hand, if the Sn/Zn value exceeds 0.25, the etching rate of the oxide semiconductor thin film itself (using a mixed acid: a mixture of phosphoric acid, nitric acid, acetic acid, and water) decreases. Therefore, it is necessary to satisfy Sn/Zn≦0.25, preferably Sn/Zn≦0.22.

If the added amount of Ga is increased, the carrier density decreases and the conductivity decreases, and the field effect mobility of the thin film transistor is likely to decrease. However, on the other hand, the wet etching resistance with respect to the hydrogen peroxide aqueous etching solution is improved. . In addition, if the amount of Sn added is excessively increased, the influence of hydrogen diffusion from the protective film becomes significant, and the carrier density or conductivity tends to decrease due to hydrogen diffusion. In addition, when the amount of In added is attempted to be increased in order to suppress the decrease in field-effect mobility, which is a disadvantage of increasing the amount of Ga added, or the decrease in the conductivity of the sputtering target, there is a risk that light stress will occur in the thin film transistor. The reliability may be reduced, or the threshold voltage may shift to the negative voltage side.

On the other hand, when the amount of Sn added instead of In is increased, the decrease in field effect mobility is suppressed, and the conductivity of the sputtering target can be improved. In addition, when the amount of Sn added is increased, the threshold voltage also tends to stabilize near 0 V. Therefore, when increasing the amount of Ga added, it is considered effective to increase the amount of Sn added instead of increasing the amount of In. However, the addition amount of Sn has a moderate addition range, and if it exceeds this addition range, the photo-stress resistance of the thin film transistor may significantly deteriorate. Therefore, by adding Ga in a well-balanced manner so as to satisfy the relationship between the amounts of Ga and Sn added, a highly reliable oxide semiconductor can be obtained.

[(Sn×In)/Ga≧0.009] IGZTO-based oxide semiconductors exhibit characteristics such as electrical conductivity and thermally induced detachability that are affected by the chemical bonding force between atoms depending on the balance of the constituent elements. However, by adding Sn, which has the effect of suppressing the detachment/vacancy of Zn, The desired mobility and stress tolerance can be achieved by multiplying the atomic number ratio of In and Ga (In/Ga), which affects electrical conductivity. Furthermore, in order to obtain the above-mentioned effect, it is necessary to satisfy (Sn×In)/Ga≧0.009. In order to obtain a higher effect, it is preferable to satisfy (Sn×In)/Ga≧0.018, and more preferably (Sn×In) )/Ga≧0.028.

Furthermore, the thickness of the oxide semiconductor layer is not particularly limited, but it is preferably 10 nm or more because selectivity during etching of the source/drain electrodes is excellent, and 15 nm or more is more preferred. In addition, in terms of maintaining a high field-effect mobility, for example, it is preferably 40 nm or less.

＜Thin film transistor＞ Next, the thin film transistor of this embodiment will be described in further detail. However, these are only examples of preferred embodiments, and the present invention is not limited to these embodiments.

As shown in FIG. 1 , a gate electrode 2 and a gate insulating film 3 are formed on a substrate 1 , and a second oxide semiconductor layer (channel forming layer) 4B and a first oxide semiconductor layer are sequentially formed thereon. (Back channel layer) 4A. In addition, the source/drain electrode 5 is formed on the first oxide semiconductor layer 4A, and the protective film (insulating film) 6 is formed thereon. Furthermore, a transparent conductive film 8 electrically connected to the source/drain electrode 5 via a contact hole 7 formed in the protective film 6 is formed.

Furthermore, since the first oxide semiconductor layer 4A represents the oxide semiconductor thin film, the atomic number of the metal element in the first oxide semiconductor layer 4A is as described for the oxide semiconductor thin film.

Regarding the manufacturing method of the thin film transistor configured as described above, except for the compositions of the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B, for example, it is the same as that shown in FIG. 2 of Japanese Patent Application Laid-Open No. 2020-136302. The manufacturing method of the thin film transistor is the same, so the description is omitted here.

In the thin film transistor of this embodiment, the composition of the second oxide semiconductor layer 4B is not particularly limited. For example, IGZTO can be used in the same manner as the first oxide semiconductor layer 4A. In this case, the metal element ratio in the second oxide semiconductor layer 4B may be different from the IGZTO used in the first oxide semiconductor layer 4A. More specifically, the atomic number ratios of In, Ga, and Sn in the first oxide semiconductor layer 4A relative to the total number of Sn, In, Ga, and Zn are respectively [In1], [Ga1], and [Sn1]. , when the atomic number ratios of In, Ga, and Sn in the second oxide semiconductor layer 4B relative to the total number of Sn, In, Ga, and Zn are respectively [In2], [Ga2], and [Sn2], it is preferable that satisfy [In1]≦[In2]、 [Ga1]≧[Ga2]、 [Sn1]≦[Sn2].

In addition, in the thin film transistor of this embodiment, the source/drain electrode 5 is directly connected to the first oxide semiconductor layer 4A, and the first oxide semiconductor layer 4A is directly exposed to the etching liquid for processing the source/drain electrode. . However, the oxide semiconductor layer of this embodiment has excellent wet etching resistance and causes little damage to the surface of the oxide semiconductor layer during processing of the source/drain electrodes, so that good thin film transistor characteristics can be obtained. In addition, the first oxide semiconductor layer 4A having the above composition can obtain high reliability against photo stress.

Furthermore, in this embodiment, even when the Sn/Zn value is appropriately adjusted and a high-temperature heat treatment is performed, Zn can be prevented from being detached (vacancies) in the surface of the first oxide semiconductor layer 4A. Therefore, even in a structure in which the source/drain electrode 5 containing Cu or a Cu alloy is directly connected to the first oxide semiconductor layer 4A, diffusion of Cu can be prevented, and excellent TFT characteristics can be obtained.

Furthermore, if the atomic number ratio of In, Ga, and Sn in the second oxide semiconductor layer 4B satisfies the above-mentioned relationship with respect to the atomic number ratio of the first oxide semiconductor layer 4A, high field-effect mobility can be obtained. In addition, by forming the second oxide semiconductor layer 4B under the first oxide semiconductor layer 4A, the field effect mobility of the entire oxide semiconductor layer can be maintained high and excellent wet etching resistance can be obtained. .

Furthermore, in the second oxide semiconductor layer 4B, if the atomic number ratio of each metal element relative to the total of In, Ga, Zn, and Sn satisfies, for example, 0.20≦In/（In+Ga+Zn+Sn）≦0.60 0.05≦Ga/(In+Ga+Zn+Sn)≦0.25 0.15≦Zn/（In+Ga+Zn+Sn）≦0.60 0.01≦Sn/(In+Ga+Zn+Sn)≦0.20, Then, the oxide semiconductor layer as a whole can achieve higher field effect mobility, which is preferable.

Generally speaking, if the oxide semiconductor layer has a multilayer structure, when forming a wiring pattern, the amount of side etching in the first layer and the second layer may be different depending on the type or content of the metal. Problems such as being unable to pattern into the desired shape. However, as shown in this embodiment, if the second oxide semiconductor layer 4B contains Sn, In, Ga, and Zn similarly to the first oxide semiconductor layer 4A, even if the ratio of each metal element is different, The etching rates of the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B may be set to the same level. As a result, it becomes soluble in the wet etching liquid for oxide processing, and the laminated structure can be etched integrally.

In addition, if the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B have the same composition system, the compositional disorder in the lamination interface will be reduced, and the depth distribution of each metal element can be prevented from suddenly changing. It can also prevent peeling, segregation, abnormal grain growth, etc. of the film when it undergoes thermal history during the manufacturing process.

＜Sputtering target＞ This embodiment also relates to a sputtering target used to form the first oxide semiconductor layer 4A in the thin film transistor. As a sputtering target, it is preferable to use a sputtering target that contains the above elements and has the same composition as the desired oxide semiconductor layer. This allows the formation of an oxide semiconductor layer with the desired composition with little difference in composition.

Specifically, the sputtering target of this embodiment contains In, Ga, Zn and Sn as metal elements, and O, With respect to the total number of atoms of In, Ga, Zn, and Sn, the atomic number ratio of each metal element satisfies 0.070≦In/（In+Ga+Zn+Sn）≦0.200 0.250≦Ga/（In+Ga+Zn+Sn）≦0.600 0.180≦Zn/(In+Ga+Zn+Sn)≦0.550 0.030≦Sn/(In+Ga+Zn+Sn)≦0.150, and Relative to the atomic number ratio of Zn, the atomic number ratio of Sn satisfies 0.10≦Sn/Zn≦0.25, and The atomic number ratio of Sn, In and Ga satisfies (Sn×In)/Ga≧0.009.

In addition, the preferable numerical ranges of In, Ga, Zn, and Sn in the sputtering target of this embodiment and the reasons for their limitation are the same as those explained for the oxide semiconductor layer. [Example]

Hereinafter, regarding the thin film transistor of this embodiment, the present invention will be further explained in detail with reference to Examples and Comparative Examples, but the present invention is not limited to these Examples.

[Manufacturing of thin film transistors] A thin film transistor having the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B is produced by the following procedure. As shown in Figure 1, first, on a glass substrate 1 (Eagle XG: manufactured by Corning Corporation) with a diameter of 100 nm and a thickness of 0.7 mm, sputtering was performed using a Mo sputtering target. Method to form a Mo film with a film thickness of 100 nm. Then, the Mo film is patterned by photolithography, thereby forming the gate electrode 2 . Then, a SiOx film as the gate insulating film 3 is formed on the entire surface of the glass substrate 1 and the gate electrode 2 using a plasma chemical vapor deposition (Chemical Vapor Deposition, CVD) method with a film thickness of 250 nm. The film formation conditions of the gate electrode 2 and the gate insulating film 3 are shown below.

(Film formation conditions of Mo thin film) Film formation temperature: Room temperature Film formation power: 300 W Carrier gas: Ar Gas pressure: 2 mTorr (Film formation conditions of SiOx film) Carrier gas: Mixed gas of SiH ₄ and N ₂ O Film power: 300 W Film forming temperature: 320℃

Next, the second oxide semiconductor layer 4B having the composition of In:Ga:Zn:Sn=4:1:4:1 is formed on the gate insulating film 3 with a film thickness of 40 nm. Then, the first oxide semiconductor layer 4A having various compositions described in Table 1 below was formed on the second oxide semiconductor layer 4B to a film thickness of 40 nm. The first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B are both formed by a sputtering method using a sputtering target having the same metal element ratio as the composition of the target oxide semiconductor layer. The device used for sputtering is "CS-200" manufactured by ULVAC Co., Ltd., and the sputtering conditions for forming the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B are as follows. .

(Sputtering conditions for forming the first oxide semiconductor layer and the second oxide semiconductor layer) Substrate temperature: room temperature Film formation power: direct current (DC) 200 W Gas pressure: 1 mTorr Oxygen partial pressure: 100 ×O ₂ /(Ar+O ₂ )=4%

After the second oxide semiconductor layer 4B and the first oxide semiconductor layer 4A are formed in the above manner, patterning is performed by photolithography and wet etching. As the wet etching liquid, an etching liquid containing oxalic acid (ITO-07N: manufactured by Kanto Chemical Co., Ltd.) was used, and the liquid temperature was set to room temperature.

Then, in order to improve the film quality of the second oxide semiconductor layer 4B and the first oxide semiconductor layer 4A, a pre-annealing process is performed. The pre-annealing treatment is performed in an atmospheric environment at 400°C for 1 hour.

Then, the source/drain electrode 5 is formed. Specifically, a MoNb film with a thickness of 35 nm and a Cu film with a thickness of 300 nm are continuously formed, and patterned by photolithography and wet etching to form the source/drain of a multilayer structure. Electrode 5. During patterning, an inorganic etching solution containing hydrogen peroxide (H ₂ O ₂ ) was used to set the channel length of the TFT to 10 μm and the channel width to 200 μm.

After the source/drain electrode 5 is formed in the above manner, a SiOx film is formed with a film thickness of 200 nm by the plasma CVD method using "PD-220NL" manufactured by SAMCO Co., Ltd., and further, The SiN film was formed with a film thickness of 150 nm, thereby forming the protective film 6 including the SiOx film and the SiN film. The film formation conditions of the SiOx film and the SiN film are shown below.

(Film formation conditions of SiOx film) Carrier gas: Mixed gas of SiH ₄ and N ₂ O Film formation power: 100 W Film formation temperature: 230°C (Film formation conditions of SiN film) Carrier gas: NH ₃ , N ₂ and N ₂ O mixed gas film forming power: 100 W Film forming temperature: 150℃

Furthermore, the protective film 6 was annealed in the air at 300° C. for 1 hour, and a photocurable resin (manufactured by KANEKA Co., Ltd.: resin film Type A2) was coated with a 600 nm film using a spin coater. A thick film is formed on the protective film 6 , and then a through-hole pattern is formed by photolithography, and a reactive ion etching (RIE) plasma etching device is used to form a contact hole 7 in the protective film 6 . Then, a post-annealing process was performed at 250° C. for 30 minutes in a nitrogen atmosphere.

Then, an indium tin oxide film (ITO film) is formed inside the protective film 6 and the contact hole 7, and the resulting film is patterned by photolithography and etching, thereby forming a connection with the source/drain via the contact hole 7. The transparent conductive film 8 is electrically connected to the electrode 5 . The thin film transistor of the embodiment is manufactured through the above procedures.

[Evaluation of thin film transistors] For each thin film transistor, field-effect mobility, stress resistance, and wet etching characteristics, which are indicators of thin film transistor characteristics, were evaluated under the following conditions.

[Measurement of transistor characteristics] The transistor characteristics (drain current (Id)-gate voltage (Vg) characteristics) were measured using a semiconductor parameter analyzer (HP4156C) manufactured by Agilent Technologies. Detailed measurement conditions are as follows.

(Measurement conditions for Id-Vg characteristics) Source voltage: 0 V Drain voltage: 10 V Gate voltage: -30 V ~ 30 V (measurement interval: 0.25 V) Substrate temperature: room temperature

<Field effect mobility μ _FE > The field effect mobility μ _FE is derived in the saturation region of Vg>Vd-Vth based on the transistor characteristics. The field effect mobility μ _FE can be derived from the following equation. Furthermore, in the following formula, Vg represents the gate voltage, Vd represents the drain voltage, Id represents the drain current, L and W represent the channel length and channel width of the TFT element respectively, and Ci represents the electrostatic capacitance of the gate insulating film. .

[Formula 1]

Furthermore, the field effect mobility μ _FE is derived based on the slope of the drain current-gate voltage characteristic (Id-Vg characteristic) near the gate voltage that satisfies the linear region. In this example, a field effect mobility of 18.0 cm ² /Vs or more is judged to be a high field effect mobility.

<Threshold voltage>

The so-called threshold voltage (Vth) is the value of the gate voltage when the transistor transitions from the off state (the state where the drain current is low) to the on state (the state where the drain current is high). In this embodiment, the gate voltage when the drain current of the thin film transistor reaches 10 ^-9 A is defined as the threshold voltage, and the threshold voltage (V) of each thin film transistor is measured.

<S value (sub-threshold swing)>

The S value is the minimum value of the change in gate voltage required to increase the drain current by one level, and the S value can be measured to evaluate the switch off scale of the TFT. In this example, an S value of 0.5 (V/decade) or less is judged to have good transistor characteristics.

[Evaluation of stress tolerance]

<Negative Bias Temperature Illumination Stress (NBTIS) test>

For each transistor, the environment (stress) when driving an actual liquid crystal panel was simulated, and a stress application test (NBTIS test) was performed in which the transistor was irradiated with light (white light) and a negative bias voltage was continuously applied to the gate electrode. ), and the variation value of the threshold voltage (Vth) before and after the stress application test (threshold voltage offset: ΔVth) is set as an index of the light stress resistance in the TFT characteristics. Photostress resistance is an important characteristic in driving liquid crystal displays. The measurement conditions of the NBTIS test are as follows.

(Measurement conditions of NBTIS test) Gate voltage: -20 V Source/Drain voltage: 10 V Substrate temperature: 60℃ Stress application time: 2 hours Light intensity during light stress: 25000 nit Light source during light stress: White Light Emitting Diode (LED)

In this example, those with a shift amount (ΔVth) of the threshold voltage (Vth) before and after the NBTIS test of 3.30 V or less were judged to have excellent stress tolerance.

＜Positive Bias Temperature Stress (PBTS) test＞ For each transistor, a stress application test (PBTS test) in which forward bias voltage is continuously applied to the gate electrode was performed, and the variation value of the threshold voltage (Vth) before and after the stress application test (threshold voltage offset amount: △Vth) is an index of stress tolerance among TFT characteristics. The measurement conditions of the PBTS test are as follows.

(Measurement conditions of PBTS test) Gate voltage: +20 V Source/Drain voltage: 0.1 V Substrate temperature: 60℃ Stress application time: 2 hours Light stress: none

In this example, those with a shift amount (ΔVth) of the threshold voltage (Vth) before and after the PBTS test of 3.30 V or less were judged to have excellent stress tolerance. The composition of the first oxide semiconductor layer in the thin film transistors of Examples 1 to 5 and Comparative Examples 1 to 4 is shown in Table 1 below, and the evaluation results are shown in Table 2 below. Furthermore, the composition of the oxide semiconductor layer is measured by inductively coupled plasma (ICP) luminescence spectrometry.

[Table 1] Table 1 Test material No. first oxide semiconductor layer Composition of each element (ICP): The atomic number ratio of each element relative to the total number of all metal elements Sn/Zn (Sn×In)/Ga In Ga Zn Sn Example 1 0.086 0.270 0.544 0.100 0.184 0.032 Example 2 0.125 0.419 0.377 0.078 0.207 0.023 Example 3 0.151 0.532 0.284 0.034 0.120 0.010 Example 4 0.196 0.569 0.192 0.043 0.224 0.015 Example 5 0.188 0.428 0.342 0.042 0.121 0.018 Comparative example 1 0.133 0.405 0.433 0.029 0.066 0.009 Comparative example 2 0.138 0.435 0.427 0 0 0 Comparative example 3 0.101 0.306 0.542 0.051 0.094 0.017 Comparative example 4 0.417 0.125 0.373 0.085 0.229 0.284

[Table 2] Table 2 Test material No. Transistor characteristics Stress tolerance Field effect mobility μ _FE (cm ² /Vs) Threshold voltage Vth (V) S value (V/decade) Offset of threshold voltage △Vth (V) NBTIS trial PBTS test Example 1 27.8 -0.5 0.27 0.75 1.00 Example 2 20.6 1.5 0.22 1.50 1.75 Example 3 24.7 3.0 0.17 2.25 3.25 Example 4 22.3 2.8 0.14 1.75 2.00 Example 5 18.6 2.8 0.16 1.75 1.50 Comparative example 1 22.4 3.0 0.16 2.25 4.25 Comparative example 2 20.5 3.5 1.18 2.50 4.50 Comparative example 3 26.7 -6.8 1.47 N/D* N/D* Comparative example 4 24.2 2.8 0.92 1.50 2.00 *N/D: Unable to measure

As shown in Table 1 and Table 2, in Examples 1 to 5, the compositions of each metal element in the oxide semiconductor layer used in the thin film transistor, (Sn/Zn) and (Sn×In)/Ga It is within the range specified by the present invention, so the field effect mobility satisfies 18.0 cm ² /Vs or more, the S value is 0.5 (V/decade) or less, and the threshold value voltage before and after the stress application test in the NBTIS test and PBTS test ( Vth) offset (△Vth) satisfies 3.30 V or less, and has excellent transistor characteristics and stress tolerance.

On the other hand, in Comparative Example 1, the atomic number ratio of In, Ga, and Zn is within the range of the present invention, but the Sn atomic number ratio and the value of (Sn/Zn) do not satisfy the range of the present invention. Therefore, the stress tolerance is The evaluation results are poor. In Comparative Example 2, the atomic ratio of In, Ga, and Zn is within the range of the present invention, but since Sn is not contained, the evaluation results of S value and stress resistance are poor. In Comparative Example 3, the atomic number ratios of the metal elements are all within the range of the present invention, but since the value of (Sn/Zn) is not within the range of the present invention, the S value and stress tolerance are poor, especially regarding stress tolerance. Properties, in any test, cannot be measured without switching at 60°C (N/D). In Comparative Example 4, the atomic number ratio of Zn, the atomic number ratio of Sn, the value of (Sn/Zn) and the value of (Sn×In)/Ga are within the range of the present invention. However, due to the atomic number ratio of In and Ga atoms, The numerical ratio does not satisfy the range of the present invention, so the evaluation result of the S value is poor.

Next, regarding the oxide semiconductor thin film of the present invention, the present invention will be further described in detail with reference to Examples and Comparative Examples.

[Formation of Oxide Semiconductor Thin Film] On the glass substrate, oxide semiconductor thin films of various compositions shown as the first oxide semiconductor layer in Table 1 were formed by sputtering, and used as samples for each evaluation shown below. In addition, the glass substrate used is the same as the glass substrate used when manufacturing the thin film transistor, and the oxide semiconductor thin film is formed using the same method and conditions as the first oxide semiconductor layer 4A.

[Evaluation of Oxide Semiconductor Thin Films] For each oxide semiconductor thin film, the wet etching resistance and wet etching resistance were measured using the following method, and the accompanying temperature was measured by the temperature rise desorption gas analysis method (Thermal Desorption Spectroscopy (TDS)) Rising amount of Zn detachment.

[Measurement of wet etching resistance] Each sample was immersed in a wet etching liquid for source/drain electrode processing (an inorganic etching liquid containing hydrogen peroxide (H ₂ O ₂ )). etching. Then, the film thickness change (amount of reduction) of the oxide semiconductor thin film before and after etching is measured, and the etching rate (nm/min) is calculated based on the relationship with the etching time. In this example, an etching speed of 16 nm/min or less was judged to have excellent wet etching resistance.

[Measurement of wet etching properties] Each sample was immersed in a wet etching liquid for oxide semiconductor thin film processing (oxalic acid wet etching liquid "ITO-07N": manufactured by Kanto Chemical Co., Ltd.) and etched. Then, the film thickness change (amount of reduction) of the oxide semiconductor thin film before and after etching is measured, and the etching rate (nm/min) is calculated based on the relationship with the etching time. In this example, an etching rate of 5 nm/min or more and 130 nm/min or less was judged to have excellent wet etching properties.

In addition, in order to evaluate the wet etching properties compared to other wet etching liquids, "PAN etching liquid" (a mixed liquid of phosphoric acid, nitric acid, and acetic acid) was used as the wet etching liquid for oxide semiconductor thin film processing, and the The etching rate (nm/min) was calculated similarly to the measurement of the wet etching property described above.

[Measurement of Zn desorption amount by TDS analysis] Each sample (Example 1 to Example 2 and Comparative Example 1 to Comparative Example 3) for the evaluation of the oxide semiconductor thin film was analyzed by temperature elevated desorption gas analysis (TDS). In TDS analysis, the amount of desorption of a component corresponding to a mass-to-charge ratio (M/z) of Zn of 64 was measured. In addition, as a sample for TDS analysis, a sample in which each oxide semiconductor thin film with a film thickness of 40 nm was formed on a glass substrate by the sputtering method in the same manner as described above was separately prepared.

The evaluation results of the wet etching resistance and wet etching properties of the second oxide semiconductor layer in Examples 1 to 5 and Comparative Examples 1 to 4 are shown in Table 3 below. The TDS analysis results related to the second oxide semiconductor layer of Examples 1 to 2 and Comparative Examples 1 to 3 are shown in FIG. 2 .

[Table 3] Table 3 Test material No. Wet etching resistance Wet etchability Etching rate (nm/min) relative to an inorganic etching solution containing hydrogen peroxide (H ₂ O ₂ ) Etching speed relative to ITO-07N (nm/min) Etching speed relative to PAN etching solution (nm/min) Example 1 15.03 66.48 32.73 Example 2 3.68 25.60 35.04 Example 3 0.88 12.51 66.46 Example 4 0.85 9.01 42.43 Example 5 1.65 23.04 128.51 Comparative example 1 5.15 31.17 150.00 Comparative example 2 9.31 95.13 545.00 Comparative example 3 19.80 123.50 384.80 Comparative example 4 5.24 37.87 7.89

As shown in Table 3, in Examples 1 to 5, since the composition of each metal element and Sn/Zn in the oxide semiconductor layer were within the range specified by the present invention, the wet etching resistance and wet etching resistance were improved. Excellent etching properties. On the other hand, in Comparative Examples 1 to 3, either or both of the Sn atomic number ratio and the Sn/Zn ratio of the oxide semiconductor layer deviate from the scope of the present invention, so the evaluation differs depending on the type of wet etching liquid. for a good etching speed range. In addition, in Comparative Example 4, like Examples 1 to 5, the composition of each metal element and Sn/Zn in the oxide semiconductor layer are within the range specified by the present invention, so the wet etching resistance and wet etching resistance are Excellent performance.

Next, in FIG. 2 , the horizontal axis represents the heating temperature of the substrate (°C), and the vertical axis represents the current intensity (A) proportional to the amount of detachment when the mass-to-charge ratio M/z=64. As shown in FIG. 2 , it was found that within the range of the heat treatment temperature (300° C. to 400° C.) usually performed when manufacturing thin film transistors, the amount of Zn detachment was reduced by increasing the Sn atomic number ratio. From this, it is considered that the improvement in ΔVth due to an increase in the amount of Sn added is affected by a decrease in the amount of Zn detached from the oxide semiconductor film. Furthermore, when manufacturing a thin film transistor, the film reduction amount is set to about 5 nm. Therefore, if the etching rate is high, it becomes difficult to control the film reduction amount. In addition, as shown in Tables 1 to 3 and Figure 2, in Comparative Example 1 and Comparative Example 2, the etching rate relative to ITO-07N is good, so the film reduction amount can be controlled to be small. However, since in normal The amount of Zn desorption increases at the heat treatment temperature, so the vacancies of Zn become Cu diffusion sources from the Cu electrode, and the transistor characteristics decrease.

Various embodiments have been described above with reference to the drawings, but the present invention is of course not limited to the examples. It is obvious to those skilled in the art that various modifications or corrections can be conceivable within the scope described in the patent application, and it should be understood that these naturally fall within the technical scope of the present invention. In addition, the constituent elements of the above-described embodiments may be combined arbitrarily within the scope that does not deviate from the gist of the invention.

Furthermore, this application is based on a Japanese patent application filed on December 16, 2019 (Japanese Patent Application No. 2019-226091) and a Japanese patent application filed on November 9, 2020 (Japanese Patent Application No. 2020-186821) , the contents of which are incorporated into this application as a reference.

1:Substrate 2: Gate electrode 3: Gate insulation film 4A: First oxide semiconductor layer 4B: Second oxide semiconductor layer 5: Source/drain electrode 6: Protective film 7:Contact hole 8:Transparent conductive film

FIG. 1 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention. FIG. 2 is a graph showing the amount of Zn desorption in the oxide semiconductor thin film as the temperature increases, when the horizontal axis represents temperature (° C.) and the vertical axis represents current intensity (A) of detected ions.

1:Substrate

2: Gate electrode

3: Gate insulation film

4A: First oxide semiconductor layer

4B: Second oxide semiconductor layer

5: Source/drain electrode

6: Protective film

7:Contact hole

8:Transparent conductive film

Claims (4)

An oxide semiconductor film containing In, Ga, Zn, Sn, and O as metal elements, and the ratio of the atomic number of each metal element to the total number of atoms of In, Ga, Zn, and Sn satisfies 0.070≦ In/(In+Ga+Zn+Sn)≦0.200 0.410≦Ga/(In+Ga+Zn+Sn)≦0.600 0.180≦Zn/(In+Ga+Zn+Sn)≦0.550 0.030≦Sn/(In+ Ga+Zn+Sn)≦0.150, and with respect to the atomic number ratio of Zn, the atomic number ratio of Sn satisfies 0.10≦Sn/Zn≦0.25, and the atomic number ratios of Sn, In and Ga satisfy ( Sn×In)/Ga≧0.009. A thin film transistor, which has a gate electrode, a gate insulating film, a second oxide semiconductor layer, a first oxide semiconductor layer, a source/drain electrode and a protective film in order on a substrate, and the thin film transistor In the crystal, the first oxide semiconductor layer contains In, Ga, Zn, Sn, and O as metal elements, and the atoms of each metal element are smaller than the total number of atoms of In, Ga, Zn, and Sn. The number ratio satisfies 0.070≦In/(In+Ga+Zn+Sn)≦0.200 0.410≦Ga/(In+Ga+Zn+Sn)≦0.600 0.180≦Zn/(In+Ga+Zn+Sn)≦0.550 0.030≦Sn/(In+Ga+Zn+Sn)≦0.150, and relative to the atomic number ratio of Zn, the atomic number ratio of Sn satisfies 0.10≦Sn/Zn≦0.25, and the atomic number ratio of Sn, In and Ga satisfies (Sn×In)/Ga≧0.009. The thin film transistor according to claim 2, wherein the source/drain electrode is directly connected to the first oxide semiconductor layer, and the source/drain electrode contains Cu or a Cu alloy. A sputtering target used to form the first oxide semiconductor layer in the thin film transistor according to claim 2 or claim 3, and the sputtering target contains In, Ga, and Zn as metal elements and Sn, and O, and relative to the total number of atoms of In, Ga, Zn and Sn, the atomic number ratio of each metal element satisfies 0.070≦In/(In+Ga+Zn+Sn)≦0.200 0.410≦Ga /(In+Ga+Zn+Sn)≦0.600 0.180≦Zn/(In+Ga+Zn+Sn)≦0.550 0.030≦Sn/(In+Ga+Zn+Sn)≦0.150, and relative to the Zn Atomic number ratio, the atomic number ratio of Sn satisfies 0.10≦Sn/Zn≦0.25, and the atomic number ratio of Sn, In and Ga satisfies (Sn×In)/Ga≧0.009.