TW202124741A - Oxide semiconductor thin film, thin film transistor, and sputtering target - Google Patents

Abstract

In the present invention, a thin film transistor is obtained which has excellent electron field-effect mobility and stress tolerance, has excellent wet etching processability with respect to a wet etching liquid used when processing an oxide semiconductor layer, and has an oxide semiconductor layer having excellent wet etching resistance against a wet etching liquid used when patterning source and drain electrodes. This oxide semiconductor thin film contains In, Ga, Zn, Sn, and O, wherein the ratio of the number of atoms of each metal element to the total number of atoms of In, Ga, Zn, and Sn satisfies 0.070 ≤ In/(In+Ga+Zn+Sn) ≤ 0.200, 0.250 ≤ Ga/(In+Ga+Zn+Sn) ≤ 0.600, 0.180 ≤ Zn/(In+Ga+Zn+Sn) ≤ 0.550, and 0.030 ≤ Sn/(In+Ga+Zn+Sn) ≤ 0.150, and also satisfies 0.10 ≤ Sn/Zn ≤ 0.25 and (Sn*In)/Ga ≥ 0.009.

Description

Oxide semiconductor thin film, thin film transistor and sputtering target

The present invention relates to an oxide semiconductor film that can be suitably used in display devices such as liquid crystal displays or organic electroluminescence (Electroluminescence, EL) displays, and a thin film electrical device including an oxide semiconductor layer containing the oxide semiconductor film. Crystal (Thin Film Transistor, TFT). In addition, the present invention relates to a sputtering target for forming an oxide semiconductor layer including the oxide semiconductor thin film.

As an amorphous oxide semiconductor, as shown in Patent Document 1, an In-Ga-Zn-based oxide containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) is known Semiconductor (Indium Gallium Zinc Oxide, IGZO). [Prior Art Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. 2010-219538

[The problem to be solved by the invention] The oxide semiconductor can be applied to the channel layer of thin film transistors that constitute electronic circuits such as display devices that require high resolution and high-speed driving. Thin-film transistors using an oxide semiconductor thin film are required to have excellent resistance to stress (stress resistance) such as light irradiation or voltage application. If the stress tolerance is low, the threshold voltage of the transistor shifts, or deviation occurs, which reduces the reliability of the display device itself.

Furthermore, when fabricating a thin film transistor including source/drain electrodes on an oxide semiconductor film, the oxide semiconductor film is also required to have high characteristics compared to chemical solutions such as wet etching solutions ( Resistance to wet etching). Specifically, the following two characteristics are required.

(I) The oxide semiconductor thin film has excellent solubility in wet etching solutions for oxide semiconductor processing (excellent wet etching processability) That is, it is required that the oxide semiconductor thin film is etched at an appropriate speed by using an organic acid-based or inorganic acid-based wet etching solution such as oxalic acid used when processing the oxide semiconductor thin film. Perform patterning. (Ii) The oxide semiconductor thin film is insoluble in wet etching solutions for source/drain electrodes (excellent wet etching resistance)

The object of the present invention is to provide an oxide semiconductor transistor that has excellent field-effect mobility and stress tolerance, and is superior to wet etching solutions used when processing oxide semiconductor layers. Wet etching processability, and the oxide semiconductor layer has excellent wet etching resistance compared to the wet etching solution used when patterning the source/drain electrodes. A thin film, a thin film transistor including the oxide semiconductor layer, and a sputtering target for forming the oxide semiconductor layer.

[Means to solve the problem] The inventors of the present invention have conducted diligent studies and found that by using an oxide semiconductor film containing In, Ga, Zn, Sn, and O as metal elements, and appropriately controlling the composition of each metal element, it is possible to The above-mentioned problems are solved, and the present invention has been completed.

That is, the above-mentioned object of the present invention can be achieved by the following structure [1] related to an oxide semiconductor thin film. [1] An oxide semiconductor thin film containing In, Ga, Zn, Sn, and O as metal elements, and With respect to the total number of atoms of In, Ga, Zn, and Sn, the atomic number ratio of each metal element satisfies 0.070≦In/(In+Ga+Zn+Sn)≦0.200 0.250≦Ga/(In+Ga+Zn+Sn)≦0.600 0.180≦Zn/(In+Ga+Zn+Sn)≦0.550 0.030≦Sn/(In+Ga+Zn+Sn)≦0.150, and Relative to the atomic ratio of Zn, the atomic ratio of Sn satisfies 0.10≦Sn/Zn≦0.25, and The atomic ratio of Sn, In and Ga satisfies (Sn×In)/Ga≧0.009.

In addition, the objective of the present invention can be achieved by the following structure [2] related to thin film transistors. [2] A thin film transistor having a gate electrode, a gate insulating film, a second oxide semiconductor layer, a first oxide semiconductor layer, a source/drain electrode, and a protective film in sequence on a substrate, and In the thin film transistor, The first oxide semiconductor layer contains In, Ga, Zn, and Sn, and O as metal elements, and With respect to the total number of atoms of In, Ga, Zn, and Sn, the atomic number ratio of each metal element satisfies 0.070≦In/(In+Ga+Zn+Sn)≦0.200 0.250≦Ga/(In+Ga+Zn+Sn)≦0.600 0.180≦Zn/(In+Ga+Zn+Sn)≦0.550 0.030≦Sn/(In+Ga+Zn+Sn)≦0.150, and Relative to the atomic ratio of Zn, the atomic ratio of Sn satisfies 0.10≦Sn/Zn≦0.25, and The atomic ratio of Sn, In and Ga satisfies (Sn×In)/Ga≧0.009.

In addition, the preferred embodiment of the present invention related to the thin film transistor is related to the following [3]. [3] The thin film transistor according to [2], wherein the source/drain electrode is directly bonded to the first oxide semiconductor layer, and the source/drain electrode includes Cu or Cu alloy.

In addition, the object of the present invention can be achieved by the structure of the following [4] related to the sputtering target. [4] A sputtering target for forming the first oxide semiconductor layer in the thin film transistor described in [2] or [3], and The sputtering target includes In, Ga, Zn, Sn, and O as metallic elements, and With respect to the total number of atoms of In, Ga, Zn, and Sn, the atomic number ratio of each metal element satisfies 0.070≦In/(In+Ga+Zn+Sn)≦0.200 0.250≦Ga/(In+Ga+Zn+Sn)≦0.600 0.180≦Zn/(In+Ga+Zn+Sn)≦0.550 0.030≦Sn/(In+Ga+Zn+Sn)≦0.150, and Relative to the atomic ratio of Zn, the atomic ratio of Sn satisfies 0.10≦Sn/Zn≦0.25, and The atomic ratio of Sn, In and Ga satisfies (Sn×In)/Ga≧0.009.

[Effects of the invention] According to the present invention, it is possible to provide an oxide semiconductor transistor that is excellent in field-effect mobility and stress tolerance, and is excellent in comparison with the wet etching solution used when processing the oxide semiconductor layer. Wet etching processability, and the oxide semiconductor layer has excellent wet etching resistance compared to the wet etching solution used when patterning the source/drain electrodes. Thin film, thin film transistor and sputtering target.

Hereinafter, the oxide semiconductor thin film and the thin film transistor according to the embodiment of the present invention will be described.

The oxide semiconductor thin film of this embodiment contains In, Ga, Zn, Sn, and O as metal elements, and With respect to the total number of atoms of In, Ga, Zn, and Sn, the atomic number ratio of each metal element satisfies 0.070≦In/(In+Ga+Zn+Sn)≦0.200 0.250≦Ga/(In+Ga+Zn+Sn)≦0.600 0.180≦Zn/(In+Ga+Zn+Sn)≦0.550 0.030≦Sn/(In+Ga+Zn+Sn)≦0.150, and Relative to the atomic ratio of Zn, the atomic ratio of Sn satisfies 0.10≦Sn/Zn≦0.25, and The atomic ratio of Sn, In and Ga satisfies (Sn×In)/Ga≧0.009.

In addition, the thin film transistor of this embodiment sequentially has a gate electrode, a gate insulating film, a second oxide semiconductor layer, a first oxide semiconductor layer, a source/drain electrode, and a protective film on the substrate. In the thin film transistor, The first oxide semiconductor layer contains In, Ga, Zn, and Sn, and O as metal elements, and With respect to the total number of atoms of In, Ga, Zn, and Sn, the atomic number ratio of each metal element satisfies 0.070≦In/(In+Ga+Zn+Sn)≦0.200 0.250≦Ga/(In+Ga+Zn+Sn)≦0.600 0.180≦Zn/(In+Ga+Zn+Sn)≦0.550 0.030≦Sn/(In+Ga+Zn+Sn)≦0.150, and Relative to the atomic ratio of Zn, the atomic ratio of Sn satisfies 0.10≦Sn/Zn≦0.25, and The atomic ratio of Sn, In and Ga satisfies (Sn×In)/Ga≧0.009.

In addition, in this embodiment, an oxide containing In, Ga, Zn, Sn, and O may be referred to as "IGZTO". In addition, the contents (atomic ratio) of In, Ga, Zn, and Sn relative to the total atomic number of all metal elements (In, Ga, Zn, and Sn) other than O are sometimes referred to as "In atom "Number ratio", "Ga atomic number ratio", "Zn atomic number ratio" and "Sn atomic number ratio".

＜Oxide semiconductor thin film＞ Hereinafter, the oxide semiconductor thin film of this embodiment (or the first oxide semiconductor layer in the thin film transistor described later) will be described.

〔0.070≦In/(In+Ga+Zn+Sn)≦0.200〕 In is an element that contributes to the improvement of electrical conductivity. The greater the In atomic ratio, that is, the greater the amount of In in all metal elements, the more the conductivity of the oxide semiconductor layer is improved, and therefore the field-effect mobility increases.

In order to effectively exert the effect, it is necessary to set the In atomic ratio to 0.070 or more. The number of In atoms is preferably 0.080 or more, more preferably 0.100 or more. However, if the In atomic ratio is too large, there are problems such as an excessive increase in the carrier density and a decrease in the threshold voltage. Therefore, the In atomic ratio is set to 0.200 or less. The number of In atoms is preferably 0.150 or less, more preferably 0.130 or less.

〔0.250≦Ga/(In+Ga+Zn+Sn)≦0.600〕 Ga is an element that helps reduce oxygen vacancies and control carrier density. The greater the Ga atomic ratio, that is, the greater the amount of Ga in all metal elements, the more improved the electrical stability of the oxide semiconductor layer, and the effect of suppressing excessive generation of carriers is exerted. In addition, Ga is also an element that inhibits etching with a hydrogen peroxide-based Cu etching solution. Therefore, the larger the Ga atomic ratio, the larger the selection ratio with respect to the hydrogen peroxide-based etchant used in the etching process of the Cu electrode as the source/drain electrode, and the less likely it is to be damaged.

In order to effectively exert the effect, the Ga atomic ratio must be 0.250 or more. The number of Ga atoms is preferably 0.300 or more, more preferably 0.410 or more. However, if the Ga atomic ratio is too large, the conductivity of the oxide semiconductor layer decreases and the field-effect mobility tends to decrease. In addition, the conductivity of the sputtering target used to form the oxide semiconductor layer is reduced, and it is difficult to stably continue DC discharge. Therefore, the Ga atomic ratio is set to 0.600 or less. The number of Ga atoms is preferably 0.500 or less, more preferably 0.450 or less.

〔0.180≦Zn/(In+Ga+Zn+Sn)≦0.550〕 Zn is not as sensitive to the characteristics of thin film transistors as other metal elements, but the larger the atomic ratio of Zn, that is, the greater the amount of Zn in all metal elements, the easier it is to amorphize, so it is easily affected by organic acids or Etching with inorganic acid etching solution.

In order to effectively exert the effect, the atomic ratio of Zn needs to be 0.180 or more. The number of Zn atoms is preferably 0.300 or more, more preferably 0.350 or more. However, if the Zn atomic ratio is too large, the solubility of the oxide semiconductor layer with respect to the source/drain electrode etching solution becomes high. As a result, there are cases where the wet etching resistance tends to deteriorate, or In is relatively reduced. However, the field-effect mobility is reduced, or the electrical stability of the oxide semiconductor layer is easily reduced due to the relative reduction of Ga. Therefore, the atomic ratio of Zn is set to 0.550 or less. The number of Zn atoms is preferably 0.500 or less, more preferably 0.400 or less.

〔0.030≦Sn/(In+Ga+Zn+Sn)≦0.150〕 Sn is an element that inhibits etching with an acid-based chemical solution. Therefore, the larger the Sn atomic ratio, that is, the larger the amount of Sn in all metal elements, the more difficult the etching process of the oxide semiconductor layer using the organic acid or inorganic acid etching solution used in the patterning. . On the other hand, oxide semiconductors doped with Sn exhibit an increase in carrier density through hydrogen diffusion, thereby increasing field-effect mobility. In addition, if the amount of Sn added is appropriate, the thin film transistors are more reliable with respect to optical stress. Sexual improvement.

In order to effectively exert the effect, the Sn atomic number ratio needs to be 0.030 or more. The number of Sn atoms is preferably 0.060 or more, more preferably 0.070 or more. On the other hand, if the Sn atomic ratio is too large, the resistance of the oxide semiconductor layer with respect to an organic acid or an inorganic acid etching solution is increased to a necessary level or more, and the processing of the oxide semiconductor layer itself becomes difficult. In addition, the reliability with respect to optical stress may decrease due to the strong influence of hydrogen diffusion. Therefore, the Sn atomic number ratio is set to 0.150 or less. The number of Sn atoms is preferably 0.110 or less, more preferably 0.080 or less.

〔0.10≦Sn/Zn≦0.25〕 Regarding the etching resistance of the oxide semiconductor layer with respect to the organic acid or inorganic acid etching solution used for patterning, although the In/Ga atomic number ratio changes, even if the In/Ga atomic number ratio is For any value, the etching resistance can also be improved by increasing the amount of Sn added. In addition, by increasing the addition amount of Sn, when the heat treatment of the oxide semiconductor layer is increased in temperature during the manufacture of thin film transistors, it is possible to prevent Zn from detaching from the oxide semiconductor layer.

The detachment of Zn is caused by the detachment of hydrogen in the oxide semiconductor layer due to the high temperature increase of the heat treatment, and with this, the bonding force between Zn and O becomes weak. As described above, when the metal atoms (Zn) on the surface of the oxide semiconductor layer are detached, the composition of the oxide semiconductor layer and the layer surface changes, and in particular, the surface of the oxide semiconductor layer becomes Zn-vacant. Therefore, it can be easily assumed that the part where Zn is vacant becomes a Cu diffusion source from the Cu electrode formed on the oxide semiconductor layer.

The change in the amount of Zn in the oxide semiconductor thin film affects the etching resistance of the oxide semiconductor layer with respect to the organic acid or inorganic acid etchant and the detachment of metal atoms (Zn) with the addition of Sn different. The Cu diffusion is caused by both the etching resistance of the cap layer and the separation of metal atoms. Therefore, the amount of Zn and the ratio of Sn/Zn atoms in the oxide semiconductor film are determined. Proper adjustment can obtain excellent TFT characteristics.

In order to prevent the diffusion of Cu as described above, it is necessary to satisfy Sn/Zn≧0.10. In addition, it is preferable to satisfy Sn/Zn≧0.18. On the other hand, if the value of Sn/Zn exceeds 0.25, the etching rate of the oxide semiconductor film itself (using a mixed acid: a mixture of phosphoric acid, nitric acid, acetic acid, and water) decreases. Therefore, it is necessary to satisfy Sn/Zn≦0.25, preferably Sn/Zn≦0.22.

If the amount of Ga added is increased, the carrier density is reduced and the conductivity is reduced, and the field effect mobility of the thin film transistor is easily reduced, but on the other hand, the wet etching resistance relative to the hydrogen peroxide aqueous etching solution is improved . In addition, if the addition amount of Sn is excessively increased, the influence of hydrogen diffusion from the protective film becomes significant, and the carrier density or conductivity tends to decrease due to hydrogen diffusion. In addition, in order to suppress the decrease in field-effect mobility or decrease in the conductivity of the sputtering target material, which is a disadvantage of increasing the amount of Ga addition, when it is desired to increase the amount of In addition, the thin film transistors may be exposed to light stress. The reliability of the device is reduced, or the threshold voltage shifts to the negative voltage side.

In contrast, when the addition amount of Sn is increased instead of In, the decrease in field-effect mobility is suppressed, and the conductivity of the sputtering target can be improved. In addition, when the amount of Sn added is increased, the threshold voltage tends to be stable around 0 V. Therefore, it is considered that in the case of increasing the addition amount of Ga, it is effective to increase the addition amount of Sn instead of increasing the addition amount of In. However, the addition amount of Sn has a moderate addition range, and if it exceeds this addition range, the deterioration of the optical stress resistance of the thin film transistor may become significant. Therefore, by adding Ga in a well-balanced manner to satisfy the relationship between the addition amounts of Ga and Sn, a highly reliable oxide semiconductor can be obtained.

〔(Sn×In)/Ga≧0.009〕 In IGZTO-based oxide semiconductors, depending on the balance of constituent elements, they exhibit characteristics such as electrical conductivity and thermally excited detachability that are affected by the chemical bonding force between atoms. Multiplying the atomic number ratio of In/Ga by the atomic number ratio of In and Ga (In/Ga), which affects electrical conductivity, can achieve the desired mobility and stress tolerance. Furthermore, in order to obtain the effect, it is necessary to satisfy (Sn×In)/Ga≧0.009. In order to obtain a higher effect, it is preferable to satisfy (Sn×In)/Ga≧0.018, and it is more preferable to satisfy (Sn×In)/Ga≧0.018. )/Ga≧0.028.

In addition, the thickness of the oxide semiconductor layer is not particularly limited, but if it is 10 nm or more, the selectivity during the etching process of the source/drain electrode is excellent, so it is preferable, and 15 nm or more is more preferable. In addition, in terms of maintaining high field-effect mobility, for example, it is preferably 40 nm or less.

＜Thin Film Transistor＞ Next, the thin film transistor of this embodiment will be described in further detail. However, these are only examples of preferred embodiments, and the present invention is not limited to these embodiments.

As shown in FIG. 1, a gate electrode 2 and a gate insulating film 3 are formed on a substrate 1, and a second oxide semiconductor layer (channel forming layer) 4B and a first oxide semiconductor layer are sequentially formed thereon (Back channel layer) 4A. In addition, a source/drain electrode 5 is formed on the first oxide semiconductor layer 4A, and a protective film (insulating film) 6 is formed thereon. Furthermore, a transparent conductive film 8 electrically connected to the source/drain electrode 5 via a contact hole 7 formed in the protective film 6 is formed.

Furthermore, the first oxide semiconductor layer 4A represents the oxide semiconductor thin film, so the number of atoms of the metal element in the first oxide semiconductor layer 4A is as described in the oxide semiconductor thin film.

Regarding the manufacturing method of the thin film transistor structured in the above manner, in addition to the composition of the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B, for example, it is shown in FIG. 2 of Japanese Patent Laid-Open No. 2020-136302 The manufacturing method of the thin film transistor is the same, therefore, the description is omitted here.

In the thin film transistor of this embodiment, the composition of the second oxide semiconductor layer 4B is not particularly limited. For example, IGZTO can be used similarly to the first oxide semiconductor layer 4A. In this case, the metal element ratio in the second oxide semiconductor layer 4B may be different from the IGZTO used in the first oxide semiconductor layer 4A. More specifically, let the atomic ratios of In, Ga, and Sn in the first oxide semiconductor layer 4A to the total of Sn, In, Ga, and Zn be [In1], [Ga1], [Sn1], respectively When the atomic ratios of In, Ga, and Sn to the total of Sn, In, Ga, and Zn in the second oxide semiconductor layer 4B are respectively [In2], [Ga2], and [Sn2], it is preferably Satisfy [In1]≦[In2], [Ga1]≧[Ga2], [Sn1]≦[Sn2].

In addition, in the thin film transistor of this embodiment, the source/drain electrode 5 is directly joined to the first oxide semiconductor layer 4A, and the first oxide semiconductor layer 4A is directly exposed to the source/drain electrode processing etching solution . However, the oxide semiconductor layer of this embodiment is excellent in wet etching resistance, and the surface of the oxide semiconductor layer is less damaged during the processing of the source/drain electrodes, and therefore, good thin film transistor characteristics can be obtained. In addition, the first oxide semiconductor layer 4A having the above composition can obtain high reliability with respect to optical stress.

Furthermore, in this embodiment, even when the value of Sn/Zn is appropriately adjusted and high-temperature heat treatment is performed, it is possible to prevent the detachment (vacancy) of Zn on the surface of the first oxide semiconductor layer 4A. Therefore, even if the source/drain electrode 5 containing Cu or a Cu alloy is directly bonded to the first oxide semiconductor layer 4A, the diffusion of Cu can be prevented, and excellent TFT characteristics can be obtained.

Furthermore, if the atomic ratio of In, Ga, Sn in the second oxide semiconductor layer 4B to the atomic ratio of the first oxide semiconductor layer 4A satisfies the above relationship, a high field-effect mobility can be obtained. In addition, by forming the second oxide semiconductor layer 4B under the first oxide semiconductor layer 4A, the field-effect mobility of the entire oxide semiconductor layer can be maintained high, and excellent wet etching resistance can be obtained. .

Furthermore, if in the second oxide semiconductor layer 4B, the atomic ratio of each metal element to the total of In, Ga, Zn, and Sn satisfies, for example, 0.20≦In/(In+Ga+Zn+Sn)≦0.60 0.05≦Ga/(In+Ga+Zn+Sn)≦0.25 0.15≦Zn/(In+Ga+Zn+Sn)≦0.60 0.01≦Sn/(In+Ga+Zn+Sn)≦0.20, As the entire oxide semiconductor layer can achieve higher field-effect mobility, it is preferable.

Generally speaking, if the oxide semiconductor layer is set as a build-up structure, when the wiring pattern is formed, the amount of side etching in the first layer and the second layer may be different due to the difference in the type or content of the metal. Unable to pattern into the desired shape and other problems. However, as shown in this embodiment, if the second oxide semiconductor layer 4B contains Sn, In, Ga, and Zn in the same way as the first oxide semiconductor layer 4A, even if the ratio of each metal element is different, The etching rates of the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B may be set to the same level. As a result, it is soluble with respect to the wet etching liquid for oxide processing, and the said laminated structure can be etched integrally.

In addition, if the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B are made of the same composition system, the disorder of the composition at the interface of the build-up layer is reduced, and the rapid change of the depth distribution of each metal element can be prevented. It can also prevent peeling or segregation of the film, abnormal grain growth, etc. when undergoing a thermal history in the manufacturing process.

＜Sputtering target＞ This embodiment also relates to a sputtering target for forming the first oxide semiconductor layer 4A in the thin film transistor. As the sputtering target, it is preferable to use a sputtering target containing the above-mentioned elements and having the same composition as the desired oxide semiconductor layer. This reduces the difference in composition and can form an oxide semiconductor layer of the desired composition.

Specifically, the sputtering target of this embodiment contains In, Ga, Zn, Sn, and O as metallic elements, With respect to the total number of atoms of In, Ga, Zn, and Sn, the atomic number ratio of each metal element satisfies 0.070≦In/(In+Ga+Zn+Sn)≦0.200 0.250≦Ga/(In+Ga+Zn+Sn)≦0.600 0.180≦Zn/(In+Ga+Zn+Sn)≦0.550 0.030≦Sn/(In+Ga+Zn+Sn)≦0.150, and Relative to the atomic ratio of Zn, the atomic ratio of Sn satisfies 0.10≦Sn/Zn≦0.25, and The atomic ratio of Sn, In and Ga satisfies (Sn×In)/Ga≧0.009.

In addition, the preferable numerical ranges of In, Ga, Zn, and Sn in the sputtering target of this embodiment and the reason for limitation are the same as those described in the oxide semiconductor layer. [Example]

Hereinafter, regarding the thin film transistor of the present embodiment, examples and comparative examples are given to further specifically describe the present invention, but the present invention is not limited to these examples.

[Manufacturing of thin film transistors] The thin film transistor having the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B is produced by the following procedure. As shown in Figure 1, first, on a glass substrate 1 (Eagle XG: Corning) with a diameter of 100 nm and a thickness of 0.7 mm, sputtering by using a Mo sputtering target Method to form a Mo thin film with a thickness of 100 nm. Then, the Mo thin film is patterned by photolithography, thereby forming the gate electrode 2. Then, on the entire surfaces of the glass substrate 1 and the gate electrode 2, a SiOx film as the gate insulating film 3 was formed using a plasma chemical vapor deposition (Chemical Vapor Deposition, CVD) method with a film thickness of 250 nm. The film forming conditions of the gate electrode 2 and the gate insulating film 3 are shown below.

(Film-forming conditions of Mo thin film) Film-forming temperature: Room temperature Film-forming power: 300 W Carrier gas: Ar Gas pressure: 2 mTorr (Film-forming conditions of SiOx film) Carrier gas: SiH ₄ and N ₂ O mixed gas Film power: 300 W Film forming temperature: 320℃

Then, a second oxide semiconductor layer 4B having a composition of In:Ga:Zn:Sn=4:1:4:1 is formed on the gate insulating film 3 with a film thickness of 40 nm. Then, the first oxide semiconductor layer 4A having various compositions described in Table 1 below was formed on the second oxide semiconductor layer 4B with a thickness of 40 nm. Both the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B are formed by a sputtering method using a sputtering target having the same metal element ratio as the composition of the target oxide semiconductor layer. The device used in sputtering is "CS-200" manufactured by ULVAC (stock). The sputtering conditions for forming the first oxide semiconductor layer 4A and the second oxide semiconductor layer 4B are as follows .

(The sputtering conditions for forming the first oxide semiconductor layer and the second oxide semiconductor layer) Substrate temperature: room temperature Film forming power: direct current (DC) 200 W Gas pressure: 1 mTorr Oxygen partial pressure: 100 ×O ₂ /(Ar+O ₂ )=4%

After the second oxide semiconductor layer 4B and the first oxide semiconductor layer 4A are formed in the manner described above, they are patterned by photolithography and wet etching. As the wet etching liquid, an etching liquid containing oxalic acid (ITO-07N: manufactured by Kanto Chemical Co., Ltd.) was used, and the liquid temperature was set to room temperature.

Then, in order to improve the film quality of the second oxide semiconductor layer 4B and the first oxide semiconductor layer 4A, pre-annealing treatment is performed. The pre-annealing treatment is carried out at 400°C for 1 hour in an atmospheric environment.

Then, source/drain electrodes 5 are formed. Specifically, a MoNb film with a thickness of 35 nm and a Cu film with a thickness of 300 nm are continuously formed, and patterned by photolithography and wet etching, thereby forming a source/drain of a multilayer structure Electrode 5. During patterning, an inorganic etching solution containing hydrogen peroxide water (H ₂ O ₂ ) is used, and the channel length of the TFT is set to 10 μm and the channel width is set to 200 μm.

After the source/drain electrodes 5 are formed in the manner described above, a SiOx film is formed with a thickness of 200 nm by the plasma CVD method using "PD-220NL" manufactured by SAMCO (stock), and further, The SiN film was formed with a film thickness of 150 nm, thereby forming a protective film 6 including an SiOx film and a SiN film. The film formation conditions of the SiOx film and the SiN film are shown below.

(Film formation conditions of SiOx film) Carrier gas: SiH ₄ and N ₂ O mixed gas Film formation power: 100 W Film formation temperature: 230°C (Film formation conditions of SiN film) Carrier gas: NH ₃ , N ₂ and N ₂ O mixed gas film forming power: 100 W Film forming temperature: 150℃

Furthermore, the protective film 6 was annealed in the atmosphere at 300°C for 1 hour, and the photocurable resin (KANEKA (Stock) Manufacturing: Resin Film TypeA2) was made into a 600 nm film using a spin coater. A thick film is formed on the protective film 6, and then a through hole pattern is formed by photolithography, and a reactive ion etching (RIE) plasma etching device is used to form a contact hole 7 in the protective film 6. Then, a post-annealing treatment was performed at 250°C for 30 minutes in a nitrogen atmosphere.

Then, an indium tin oxide film (ITO film) is formed inside the protective film 6 and the contact hole 7, and the resultant film is patterned by photolithography and etching, thereby forming the contact hole 7 and the source/drain The polar electrode 5 is electrically connected to the transparent conductive film 8. The thin film transistor of the embodiment is manufactured by the above procedure.

[Evaluation of thin film transistors] For each thin-film transistor, field-effect mobility, stress tolerance, and wet etching characteristics, which are indicators of the characteristics of the thin-film transistor, were evaluated under the following conditions.

[Measurement of Transistor Characteristics] Transistor characteristics (drain current (Id)-gate voltage (Vg) characteristics) were measured using the "HP4156C" semiconductor parameter analyzer manufactured by Agilent Technologies. The detailed measurement conditions are as follows.

(Measurement conditions of Id-Vg characteristics) Source voltage: 0 V Drain voltage: 10 V Gate voltage: -30 V～30 V (measurement interval: 0.25 V) Substrate temperature: room temperature

<Field-effect mobility μ _FE > The field-effect mobility μ _FE is derived in the saturation region of Vg>Vd-Vth based on the characteristics of the transistor. The field-effect mobility μ _FE can be derived from the following equation. Furthermore, in the following formula, Vg represents the gate voltage, Vd represents the drain voltage, Id represents the drain current, L and W represent the channel length and channel width of the TFT element, respectively, and Ci represents the electrostatic capacitance of the gate insulating film .

[Numerical formula 1]

In addition, the field-effect mobility μ _FE is derived from the slope that satisfies the drain current-gate voltage characteristic (Id-Vg characteristic) near the gate voltage of the linear region. In this embodiment, a field-effect mobility of 18.0 cm ² /Vs or more is judged to be a high field-effect mobility.

<Threshold voltage> The so-called threshold voltage (Vth) is the value of the gate voltage when the transistor moves from the off state (the state where the drain current is low) to the on state (the state where the drain current is high). In this embodiment, the gate voltage when the drain current of the thin film transistor becomes 10 ^-9 A is defined as the threshold voltage, and the threshold voltage (V) of each thin film transistor is measured.

<S value (second threshold swing)> The S value is the minimum value of the change in the gate voltage required to increase the drain current by one bit, and the TFT switch off scale can be evaluated by measuring the S value. In this embodiment, the S value is determined to be less than 0.5 (V/decade) as good transistor characteristics.

[Evaluation of stress tolerance] ＜Negative Bias Temperature Illumination Stress (NBTIS) test＞ In each transistor, the environment (stress) when the actual liquid crystal panel is driven is simulated, and a stress application test (NBTIS test) is performed in which light (white light) is irradiated to the transistor and a negative bias is continuously applied to the gate electrode. ), the variation value of the threshold voltage (Vth) before and after the stress application test (the threshold voltage deviation: ΔVth) is used as an index of the optical stress tolerance in the TFT characteristics. Light stress resistance is an important characteristic in driving liquid crystal displays. The measurement conditions of the NBTIS test are as follows.

(Measurement conditions of NBTIS test) Gate voltage: -20 V Source/drain voltage: 10 V Substrate temperature: 60℃ Stress application time: 2 hours Light intensity under light stress: 25000 nit Light source under light stress: white light emitting diode (Light Emitting Diode, LED)

In the present example, the deviation (ΔVth) of the threshold voltage (Vth) before and after the NBTIS test is determined to be 3.30 V or less as having excellent stress tolerance.

＜Positive Bias Temperature Stress (PBTS) test＞ In each transistor, a stress application test (PBTS test) that continuously applies a positive bias voltage to the gate electrode is implemented, and the threshold voltage (Vth) variation value before and after the stress application test (the threshold voltage offset: ΔVth) is used as an index of stress tolerance in TFT characteristics. The measurement conditions of the PBTS test are as follows.

(Measurement conditions of PBTS test) Gate voltage: +20 V Source/drain voltage: 0.1 V Substrate temperature: 60℃ Stress application time: 2 hours Light stress: none

In this example, the deviation (ΔVth) of the threshold voltage (Vth) before and after the PBTS test was determined to be 3.30 V or less as having excellent stress tolerance. The composition of the first oxide semiconductor layer in the thin film transistors of Example 1 to Example 5 and Comparative Example 1 to Comparative Example 4 is shown in Table 1 below, and each evaluation result is shown in Table 2 below. Furthermore, the composition of the oxide semiconductor layer is measured by inductively coupled plasma (ICP) emission spectrometry.

[Table 1] Table 1 Test material No. First oxide semiconductor layer Composition of each element (ICP): The atomic ratio of each element to the total of all metal elements Sn/Zn (Sn×In)/Ga In Ga Zn Sn Example 1 0.086 0.270 0.544 0.100 0.184 0.032 Example 2 0.125 0.419 0.377 0.078 0.207 0.023 Example 3 0.151 0.532 0.284 0.034 0.120 0.010 Example 4 0.196 0.569 0.192 0.043 0.224 0.015 Example 5 0.188 0.428 0.342 0.042 0.121 0.018 Comparative example 1 0.133 0.405 0.433 0.029 0.066 0.009 Comparative example 2 0.138 0.435 0.427 0 0 0 Comparative example 3 0.101 0.306 0.542 0.051 0.094 0.017 Comparative example 4 0.417 0.125 0.373 0.085 0.229 0.284

[Table 2] Table 2 Test material No. Transistor characteristics Stress tolerance Field effect mobility μ _FE (cm ² /Vs) Threshold voltage Vth (V) S value (V/decade) Offset of threshold voltage △Vth (V) NBTIS test PBTS test Example 1 27.8 -0.5 0.27 0.75 1.00 Example 2 20.6 1.5 0.22 1.50 1.75 Example 3 24.7 3.0 0.17 2.25 3.25 Example 4 22.3 2.8 0.14 1.75 2.00 Example 5 18.6 2.8 0.16 1.75 1.50 Comparative example 1 22.4 3.0 0.16 2.25 4.25 Comparative example 2 20.5 3.5 1.18 2.50 4.50 Comparative example 3 26.7 -6.8 1.47 N/D* N/D* Comparative example 4 24.2 2.8 0.92 1.50 2.00 *N/D: Cannot be measured

As shown in Table 1 and Table 2, in Examples 1 to 5, the composition of each metal element in the oxide semiconductor layer used in the thin film transistor, (Sn/Zn) and (Sn×In)/Ga It is within the range specified by the present invention, so the field-effect mobility satisfies 18.0 cm ² /Vs or more, the S value is 0.5 (V/decade) or less, and the threshold voltage before and after the stress application test in the NBTIS test and PBTS test ( Vth) offset (△Vth) meets 3.30 V or less, and the transistor characteristics and stress tolerance are both excellent.

On the other hand, in Comparative Example 1, the atomic ratio of In, Ga, and Zn is within the range of the present invention, but since the Sn atomic ratio and the value of (Sn/Zn) do not satisfy the range of the present invention, the stress tolerance The evaluation result is poor. In Comparative Example 2, the atomic ratios of In, Ga, and Zn are within the range of the present invention, but since Sn is not contained, the evaluation results of the S value and stress tolerance are poor. In Comparative Example 3, the atomic ratios of the metal elements are all within the range of the present invention, but since the value of (Sn/Zn) is not within the range of the present invention, the S value and stress resistance are poor, especially with regard to stress resistance In any test, it cannot be measured without switching at 60°C (N/D). In Comparative Example 4, the atomic number ratio of Zn, the atomic number ratio of Sn, the value of (Sn/Zn), and the value of (Sn×In)/Ga are within the scope of the present invention, but due to the atomic ratio of In and Ga atoms The number ratio does not satisfy the range of the present invention, so the evaluation result of the S value is poor.

Next, regarding the oxide semiconductor thin film of the present invention, examples and comparative examples are given to further specifically describe the present invention.

[Formation of oxide semiconductor thin film] On a glass substrate, oxide semiconductor thin films of various compositions shown as the first oxide semiconductor layer in Table 1 were formed by sputtering, and were used as samples for each evaluation shown below. In addition, the same glass substrate as that used when manufacturing the thin film transistor is used as the glass substrate, and the oxide semiconductor thin film is formed by the same method and conditions as the first oxide semiconductor layer 4A.

[Evaluation of oxide semiconductor thin film] For each oxide semiconductor thin film, the wet etching resistance and wet etching resistance are measured by the following methods, and the accompanying temperature is measured by the temperature rise desorption gas analysis method (Thermal Desorption Spectroscopy (TDS)) Increased Zn desorption amount.

[Measurement of wet etching resistance] The samples were immersed in a wet etching solution for source/drain electrode processing (an inorganic etching solution _{containing hydrogen peroxide (H 2} O _{2 )).} Etching. Then, the film thickness change (reduction amount) of the oxide semiconductor thin film before and after the etching was measured, and the etching rate (nm/min) was calculated based on the relationship with the etching time. In this example, it is judged that an etching rate of 16 nm/min or less is excellent in wet etching resistance.

〔Measurement of wet etching properties〕 Each of the samples was immersed in a wet etching solution for processing an oxide semiconductor thin film (oxalic acid wet etching solution "ITO-07N": manufactured by Kanto Chemical Co., Ltd.) to perform etching. Then, the film thickness change (reduction amount) of the oxide semiconductor thin film before and after the etching was measured, and the etching rate (nm/min) was calculated based on the relationship with the etching time. In this example, it is judged that an etching rate of 5 nm/min or more and 130 nm/min or less is excellent in wet etching properties.

In addition, in order to evaluate the wet etching properties relative to other wet etching solutions, "PAN etching solution" (a mixture of phosphoric acid, nitric acid, and acetic acid) was used as the wet etching solution for oxide semiconductor thin film processing. The etching rate (nm/min) was calculated in the same manner as in the measurement of the wet etching property.

[Measurement of the amount of Zn released by TDS analysis] The samples (Example 1 to Example 2 and Comparative Example 1 to Comparative Example 3) for the evaluation of the oxide semiconductor thin film were analyzed by the temperature-rising degassing analysis method (TDS). In the TDS analysis, the amount of detachment of the component corresponding to the mass-to-charge ratio (M/z) of Zn of 64 was measured. In addition, as a sample for TDS analysis, a sample was separately prepared in which each oxide semiconductor thin film having a thickness of 40 nm was formed on a glass substrate by a sputtering method in the same manner as described above.

The evaluation results of wet etching resistance and wet etching resistance related to the second oxide semiconductor layers of Example 1 to Example 5 and Comparative Example 1 to Comparative Example 4 are shown in Table 3 below. The results of TDS analysis on the second oxide semiconductor layer of Example 1 to Example 2 and Comparative Example 1 to Comparative Example 3 are shown in FIG. 2.

[Table 3] Table 3 Test material No. Wet etching resistance Wet etching Etching rate (nm/min) relative to inorganic etching solution containing hydrogen peroxide water (H ₂ O ₂₎ Relative to ITO-07N etching speed (nm/min) Relative to the etching rate of PAN etching solution (nm/min) Example 1 15.03 66.48 32.73 Example 2 3.68 25.60 35.04 Example 3 0.88 12.51 66.46 Example 4 0.85 9.01 42.43 Example 5 1.65 23.04 128.51 Comparative example 1 5.15 31.17 150.00 Comparative example 2 9.31 95.13 545.00 Comparative example 3 19.80 123.50 384.80 Comparative example 4 5.24 37.87 7.89

As shown in Table 3, in Examples 1 to 5, since the composition of each metal element in the oxide semiconductor layer and Sn/Zn are within the range specified in the present invention, the wet etching resistance and wet etching resistance are Excellent etching properties. On the other hand, in Comparative Example 1 to Comparative Example 3, either or both of the Sn atomic ratio and the Sn/Zn ratio of the oxide semiconductor layer are out of the scope of the present invention, so the evaluation is deviated according to the type of wet etching solution. It is a good etching speed range. In addition, in Comparative Example 4, similar to Examples 1 to 5, the composition of each metal element in the oxide semiconductor layer and Sn/Zn are within the range specified in the present invention, so the wet etching resistance and wet etching resistance are The sex is excellent.

Next, in FIG. 2, the horizontal axis is the heating temperature (° C.) of the substrate, and the vertical axis is the current intensity (A) proportional to the amount of detachment at the mass-to-charge ratio M/z=64. As shown in Fig. 2, it is read that in the range of the heat treatment temperature (300° C. to 400° C.) that is usually performed in the manufacture of thin film transistors, the amount of Zn desorption is reduced by increasing the Sn atomic ratio. From this, it can be considered that the improvement of ΔVth based on the increase in the addition amount of Sn is affected by the decrease in the amount of Zn detached from the oxide semiconductor film. Furthermore, since the film reduction amount is set to about 5 nm when manufacturing the thin film transistor, if the etching rate is high, it becomes difficult to control the film reduction amount. In addition, as shown in Table 1 to Table 3 and Fig. 2, in Comparative Example 1 and Comparative Example 2, since the etching rate relative to ITO-07N is good, the film reduction can be controlled to be small, but due to normal The amount of Zn detachment increases at the heat treatment temperature of, so the vacancy part of Zn becomes the Cu diffusion source from the Cu electrode, and the transistor characteristics are reduced.

In the foregoing, various embodiments have been described with reference to the drawings, but the present invention is of course not limited to the above-mentioned examples. It is clear to those skilled in the art that various modifications or amendments are conceivable within the scope described in the scope of patent application, and it should be understood that these naturally also belong to the technical scope of the present invention. In addition, the constituent elements of the above-mentioned embodiment can be combined arbitrarily within a range that does not deviate from the gist of the invention.

Furthermore, this application is based on a Japanese patent application filed on December 16, 2019 (Japanese Patent Application No. 2019-226091) and a Japanese patent application filed on November 9, 2020 (Japanese Patent Application No. 2020-186821) , The content is cited as a reference in this application.

1: substrate 2: Gate electrode 3: Gate insulating film 4A: First oxide semiconductor layer 4B: second oxide semiconductor layer 5: source/drain electrode 6: Protective film 7: Contact hole 8: Transparent conductive film

Fig. 1 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention. FIG. 2 is a graph showing the amount of Zn desorption in the oxide semiconductor thin film accompanying temperature rise when the horizontal axis is temperature (° C.) and the vertical axis is current intensity (A) of detection ions.

1: substrate

2: Gate electrode

3: Gate insulating film

4A: First oxide semiconductor layer

4B: second oxide semiconductor layer

5: source/drain electrode

6: Protective film

7: Contact hole

8: Transparent conductive film

Claims (4)

An oxide semiconductor thin film containing In, Ga, Zn, Sn, and O as metal elements, and With respect to the total number of atoms of In, Ga, Zn, and Sn, the atomic number ratio of each metal element satisfies 0.070≦In/(In+Ga+Zn+Sn)≦0.200 0.250≦Ga/(In+Ga+Zn+Sn)≦0.600 0.180≦Zn/(In+Ga+Zn+Sn)≦0.550 0.030≦Sn/(In+Ga+Zn+Sn)≦0.150, and Relative to the atomic ratio of Zn, the atomic ratio of Sn satisfies 0.10≦Sn/Zn≦0.25, and The atomic ratio of Sn, In and Ga satisfies (Sn×In)/Ga≧0.009. A thin film transistor, which sequentially has a gate electrode, a gate insulating film, a second oxide semiconductor layer, a first oxide semiconductor layer, a source/drain electrode, and a protective film on a substrate, and the thin film transistor In the crystal, The first oxide semiconductor layer contains In, Ga, Zn, and Sn, and O as metal elements, and With respect to the total number of atoms of In, Ga, Zn, and Sn, the atomic number ratio of each metal element satisfies 0.070≦In/(In+Ga+Zn+Sn)≦0.200 0.250≦Ga/(In+Ga+Zn+Sn)≦0.600 0.180≦Zn/(In+Ga+Zn+Sn)≦0.550 0.030≦Sn/(In+Ga+Zn+Sn)≦0.150, and Relative to the atomic ratio of Zn, the atomic ratio of Sn satisfies 0.10≦Sn/Zn≦0.25, and The atomic ratio of Sn, In and Ga satisfies (Sn×In)/Ga≧0.009. The thin film transistor according to claim 2, wherein the source/drain electrode is directly bonded to the first oxide semiconductor layer, and the source/drain electrode includes Cu or Cu alloy. A sputtering target for forming the first oxide semiconductor layer in the thin film transistor according to claim 2 or claim 3, and The sputtering target includes In, Ga, Zn, Sn, and O as metallic elements, and With respect to the total number of atoms of In, Ga, Zn, and Sn, the atomic number ratio of each metal element satisfies 0.070≦In/(In+Ga+Zn+Sn)≦0.200 0.250≦Ga/(In+Ga+Zn+Sn)≦0.600 0.180≦Zn/(In+Ga+Zn+Sn)≦0.550 0.030≦Sn/(In+Ga+Zn+Sn)≦0.150, and Relative to the atomic ratio of Zn, the atomic ratio of Sn satisfies 0.10≦Sn/Zn≦0.25, and The atomic ratio of Sn, In and Ga satisfies (Sn×In)/Ga≧0.009.

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