JP2014082424A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has high field effect mobility, high reliability and stable semiconductor characteristics, and provide a semiconductor device manufacturing method.SOLUTION: In a semiconductor device manufacturing method including on a substrate, at least a gate electrode, a gate insulation film, a semiconductor film, a source and drain electrode and a protective film, the semiconductor film contains In (indium), Zn (zinc), Sn (tin) and O (oxygen), and a pressure in a deposition device before deposition when depositing the protective film after deposition of the semiconductor film, is set at not less than 5×10Pa and not more than 5×10Pa.

Description

  The present invention relates to a method for manufacturing a semiconductor device, a semiconductor device, and an electronic apparatus using the same.

  Field effect transistors such as thin film transistors (TFTs) are widely used as unit electronic elements, high frequency signal amplifying elements, liquid crystal driving elements, etc. for semiconductor memory integrated circuits, and are currently the most widely used electronic devices. . In particular, with the remarkable development of display devices in recent years, in various display devices such as liquid crystal display devices (LCD), electroluminescence display devices (EL), and field emission displays (FED), a driving voltage is applied to the display elements. TFTs are often used as switching elements for driving display devices.

  As a material for a semiconductor layer (channel layer) which is a main member of a field effect transistor, a silicon semiconductor compound is most widely used. In general, a silicon single crystal is used for a high-frequency amplifying element or an integrated circuit element that requires high-speed operation.

  On the other hand, an amorphous silicon semiconductor (amorphous silicon) is used for a liquid crystal driving element or the like because of a demand for a large area. Although an amorphous silicon thin film can be formed at a relatively low temperature, its switching speed is slower than that of a crystalline one, so when used as a switching element to drive a display device, it may not be able to follow the display of high-speed movies. is there.

Specifically, the LCD TV resolution of full high-definition, but mobility amorphous silicon 0.5 to 1 cm ² / Vs were available, the resolution is further becomes 8k4k 4k2k, ^{2cm 2} / Vs The above mobility is required. Further, when the driving frequency is increased in order to improve the image quality, higher mobility is required.

  Although crystalline silicon-based thin films have high mobility, laser annealing using a high temperature of, for example, 800 ° C. or higher and expensive equipment is required for crystallization, and a large amount of energy and number of processes are required for manufacturing. In addition, there is a problem that it is difficult to increase the area. In addition, since the crystalline silicon-based thin film is normally limited to the top gate configuration of the TFT, the cost reduction such as reduction of the number of masks is difficult.

In order to solve such a problem, a new semiconductor material that replaces a silicon-based semiconductor is required, which is composed of an n-type semiconductor material containing indium oxide and zinc oxide, indium oxide, zinc oxide, and gallium oxide. Methods for manufacturing an amorphous oxide semiconductor film having an electron carrier concentration of less than 10 ¹⁸ / cm ³ and driving a field effect transistor have been studied (Patent Documents 1 to 4).

  However, although the field effect transistor described above is superior to amorphous silicon in characteristics such as mobility, it does not reach that of crystalline silicon, and is a switching element that drives current in peripheral circuits such as SOG (system on glass) and organic EL displays. Therefore, further improvements in characteristics such as mobility and ΔVth have been demanded. Note that Vth means a threshold voltage, and ΔVth means a change amount (shift amount) of Vth when bias stress is applied.

  For this reason, studies have been made by changing the composition ratio of indium oxide, zinc oxide, and gallium oxide, but sufficient results have not been obtained (Patent Documents 3 and 4 and Non-Patent Document 1). For example, when the content of indium oxide is increased, the mobility is improved, but the threshold voltage is greatly negative and becomes normally on (Patent Document 3). On the other hand, when the content of gallium oxide is reduced, the mobility is improved, but the reliability is lowered (Patent Documents 3 and 4).

  The inventors of the present invention designed a material mainly composed of indium oxide, tin oxide and zinc oxide as an oxide semiconductor having a new composition, and proposed a transistor having both high mobility and normally-off (Patent Document 5). . However, it has been difficult to obtain a highly reliable TFT using a combination of indium oxide, tin oxide, and zinc oxide.

JP 2006-114928 A International Publication No. 2005/088726 Pamphlet JP 2007-281409 A International Publication No. 2007/120010 Pamphlet Japanese Patent Application Laid-Open No. 2008-243928

Tatsuya Iwasaki et al. , Appl. Phys. Lett. 90,242114 (2007)

  An object of the present invention is to provide a semiconductor device having high field effect mobility and reliability and stable semiconductor characteristics, and a method for manufacturing the same.

As a result of intensive studies to achieve the above object, the present inventors have found that the reliability of TFT depends on the interface trap density of the semiconductor layer, that is, the process related to the interface is important. Was completed.
According to the present invention, the following manufacturing method and the like are provided.
1. A manufacturing method of a semiconductor device including at least a gate electrode, a gate insulating film, a semiconductor film, a source and drain electrode, and a protective film on a substrate, wherein the semiconductor film is made of In (indium), Zn (zinc), Sn ( It includes tin) and O (oxygen), the rear formation of the semiconductor film, the pressure in the film forming apparatus before the formation during the formation of the protective film, 5 × 10 -6 ^Pa or more 5 × 10 ^- The manufacturing method of the semiconductor device made into ³ Pa or less.
2. 2. The method of manufacturing a semiconductor device according to 1, wherein a pressure in the film formation apparatus before film formation when forming the gate insulating film is 5 × 10 ⁻⁶ Pa or more and 5 × 10 ⁻³ Pa or less.
3. 3. The method for manufacturing a semiconductor device according to 1 or 2, wherein the semiconductor film contains In, Zn, and Sn in the following atomic ratio.
0.2 ≦ In / (In + Sn + Zn) ≦ 0.8
0.1 <Zn / (In + Sn + Zn) ≦ 0.6
0.001 ≦ Sn / (In + Sn + Zn) ≦ 0.5
4). A semiconductor device including at least a gate electrode, a gate insulating film, a semiconductor film, a source and drain electrode, and a protective film on a substrate, wherein the semiconductor film includes In (indium), Zn (zinc), Sn (tin), and The interface state density at the interface between the gate insulating film or the protective film and the semiconductor film containing O (oxygen) is 1 × 10 ¹⁰ cm under 0.5 eV from the conduction band of the semiconductor film. ⁻² eV ⁻¹ or more and less than 1 × 10 ¹² cm ⁻² eV ⁻¹ .
5. 5. The semiconductor device according to 4, wherein the semiconductor film contains In, Zn, and Sn in the following atomic ratio.
0.2 ≦ In / (In + Sn + Zn) ≦ 0.8
0.1 <Zn / (In + Sn + Zn) ≦ 0.6
0.001 ≦ Sn / (In + Sn + Zn) ≦ 0.5
An electronic apparatus using the semiconductor device according to 6.4 or 5.

  According to the present invention, it is possible to provide a semiconductor device having high field-effect mobility and reliability and stable semiconductor characteristics, and a method for manufacturing the same.

2 is a schematic cross-sectional view of a TFT manufactured in Example 1. FIG. FIG. 3 is a diagram used for obtaining an interface trap density in Example 1.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including at least a gate electrode, a gate insulating film, a semiconductor film, a source and drain electrode, and a protective film on a substrate. The pressure in the film formation apparatus before film formation when forming the protective film as a body is set to 5 × 10 ⁻⁶ Pa or more and 5 × 10 ⁻³ Pa or less.
The semiconductor film contains In (indium), Zn (zinc), Sn (tin), and O (oxygen).

  By setting the pre-deposition pressure (degree of vacuum before film formation) of the protective film (semiconductor film protective film), which is a dielectric in contact with part or all of the semiconductor film surface, as described above, the interface with the semiconductor film A trap density can be reduced, and a TFT having excellent reliability (small ΔVth) can be manufactured.

The pre-deposition pressure of the protective film greatly affects the trap level at the semiconductor interface of the protective film. The atmosphere before forming the protective film is preferably as high as possible.
The pressure before forming the protective film is 5 × 10 ⁻⁶ Pa or more and 5 × 10 ⁻³ Pa or less, preferably 1 × 10 ⁻⁵ Pa or more and 1 × 10 ⁻³ Pa or less, more preferably 7 ×. 10 ⁻⁵ Pa to 7 × 10 ⁻⁴ Pa, more preferably 1 × 10 ⁻⁴ Pa to 5 × 10 ⁻⁴ Pa.

When the degree of vacuum is 5 × 10 ⁻⁶ Pa or more, a long time is not required for evacuation, which is practical in production.
When the degree of vacuum is 5 × 10 ⁻³ Pa or less, for example, when the film forming gas is decomposed by plasma CVD, it is easy to prevent moisture and carbon components from being simultaneously decomposed and taken into the dielectric. In addition, it is easy to prevent the obtained transistor from forming a large amount of levels at the interface with the channel layer, thereby reducing mobility and S value.

In the present invention, the protective film (semiconductor film protective film) is a film that is in direct contact with the surface of the oxide thin film, and is any one of an etch stop layer, an interlayer insulating film, and a passivation film described later. is there.
In the present invention, an interlayer insulating film may or may not be provided. Therefore, when the interlayer insulating film is provided, the interlayer insulating film is a protective film, and when the interlayer insulating film is not provided, the passivation film is the protective film.

Moreover, it is preferable that the pressure in the film formation apparatus before forming the gate insulating film is 5 × 10 ⁻⁶ Pa or more and 5 × 10 ⁻³ Pa or less.
By setting the pre-deposition pressure of the gate insulating film, which is a dielectric that is in contact with the other interface of the semiconductor, as described above, a TFT having excellent reliability (small ΔVth) is manufactured, similar to the protective film. be able to.
The pre-deposition pressure of the gate insulating film is preferably 1 × 10 ⁻⁵ Pa or more and 1 × 10 ⁻³ Pa or less, more preferably 7 × 10 ⁻⁵ Pa or more and 7 × 10 ⁻⁴ Pa or less, Preferably, it is 1 × 10 ⁻⁴ Pa or more and 5 × 10 ⁻⁴ Pa or less.

The material constituting the dielectric film is not particularly limited, and any material generally used can be selected as long as the effects of the present invention are not lost. For _{example, SiO 2, SiNx, Al 2} O 3, Ta 2 O 5, TiO 2, MgO, ZrO 2, CeO 2, K 2 O, Li 2 O, Na 2 O, Rb 2 O, Sc 2 O 3, Y An oxide or nitride such as ₂ O ₃ , Hf ₂ O ₃ , CaHfO ₃ , PbTi ₃ , BaTa ₂ O ₆ , SrTiO _3, or AlN can be used.
It should be noted that, as items required for the gate insulating film, it is important that the film thickness non-uniformity is small and that there is no pinhole that causes leakage. As a general gate insulating film, SiO ₂ , SiNx, Al ₂ O ₃ or the like is used.

When a silicon oxide film is used as the dielectric film, the oxygen number of the silicon oxide does not necessarily match the stoichiometric ratio (for example, it may be SiO ₂ or SiOx). The dielectric film may have a structure in which two or more different insulating films are stacked.

  Dielectric film (protective film, gate insulating film) can be formed by various methods such as plasma CVD, hot wire CVD, atomic layer CVD, photo CVD, TEOS-CVD, etc., CVD (chemical vapor deposition), sputtering, etc. The method is mentioned.

As a film forming method, plasma CVD is preferable in consideration of a large area, productivity, and the like. Plasma CVD can be performed as follows, for example. That is, a substrate is set in a chamber, SiH ₄ , N ₂ O, N ₂ is introduced when the dielectric film is SiO ₂ , SiH ₄ , NH ₃ , N ₂ is introduced when SiNx is used, and gas is generated by plasma. And a desired dielectric film is deposited on the substrate by reacting at a temperature of about 150 ° C. to 400 ° C.
The pressure at this time is theoretically possible as long as the plasma discharge is stable, but considering the cleanliness, it is preferably performed in a reduced pressure atmosphere of 10 Pa to 500 Pa.

The thickness of the protective film is usually 50 to 300 nm.
The thickness of the gate insulating film is usually 50 to 300 nm.
The film thickness can be measured with a stylus type surface shape measuring instrument (for example, Dektak 150 (manufactured by ULVAC, Inc.)).

  The semiconductor film (oxide thin film, channel layer) contains In, Zn, Sn, and O (oxygen). When In is included, high mobility can be expected. In addition, when Zn is contained, a stable amorphous film can be obtained, and it can be expected that a large-area and uniform field-effect transistor is obtained.

The semiconductor film more preferably contains In, Zn, and Sn in the following atomic ratio.
0.2 ≦ In / (In + Sn + Zn) ≦ 0.8
0.1 <Zn / (In + Sn + Zn) ≦ 0.6
0.001 ≦ Sn / (In + Sn + Zn) ≦ 0.5

When In / (In + Sn + Zn) is 0.2 or more, high TFT mobility can be expected, and when it is 0.8 or less, a threshold value (Vth) having a small absolute value can be expected.
When Zn / (In + Sn + Zn) is more than 0.1, the ITZO film (oxide thin film containing In, Zn, Sn and O) can be held in a stable amorphous structure. In this case, resistance to etching of the source / drain electrodes and film formation conditions of the protective film can be imparted.
When Sn / (In + Sn + Zn) is 0.001 or more, it is possible to impart resistance to etching conditions of the source / drain electrodes and the protective film, and when it is 0.5 or less, etching with oxalic acid is possible. It becomes.

  The In ratio (atomic ratio) is preferably 0.30 ≦ In / (In + Sn + Zn) ≦ 0.65, and more preferably 0.35 ≦ In / (In + Sn + Zn) ≦ 0.50.

  The proportion (atomic ratio) of Zn is preferably 0.30 ≦ Zn / (In + Sn + Zn) ≦ 0.55, and more preferably 0.35 ≦ Zn / (In + Sn + Zn) ≦ 0.50.

  The ratio (atomic ratio) of Sn is preferably 0.20 ≦ Sn / (In + Sn + Zn) ≦ 0.50, and more preferably 0.30 ≦ Sn / (In + Sn + Zn) ≦ 0.49.

  Each atomic ratio in the thin film can be determined by quantitatively analyzing the contained elements with an inductively coupled plasma emission spectrometer (ICP-AES).

The semiconductor film is preferably an amorphous (amorphous) oxide. The amorphous oxide is excellent in uniformity over a large area and is suitable for a peripheral circuit such as a system on glass (SOG) or a switching element for driving a current of an organic EL display. In addition, adhesion with the protective film and the gate insulating film can be improved.
Amorphous oxide refers to an oxide whose clear peak cannot be confirmed by X-ray diffraction.

Further, the semiconductor film may contain a metal element other than the metal elements In, Zn, and Sn, and may contain substantially only In, Zn, and Sn, or only In, Zn, and Sn. .
Examples of metal elements that may be contained in addition to In, Zn, and Sn include Ga, Al, Hf, Zr, Ge, Si, and Ti. By containing these, the reliability of the semiconductor film can be increased. A preferred metal element is Al.

In the present invention, “substantially” means that 95% by weight to 100% by weight (preferably 98% by weight to 100% by weight) of the metal element of the semiconductor film is In, Zn, and Sn.
Further, the metal element contained in the semiconductor film is composed only of In, Zn, and Sn, and may contain other inevitable impurities as long as the effects of the present invention are not impaired.

When the metal elements contained are the above three types, the trap density in the channel can be further reduced. Specifically, the density of states below 0.5 eV from the conduction band of the channel can be suppressed to 10 ¹² cm ⁻² eV ⁻¹ or less.

The reason why the trap density of the oxide semiconductor composed of In, Sn, and Zn is low is that Sn levels are formed in the band gap of In ₂ O ₃ . In an oxide semiconductor composed of In, Sn, and Zn, a 5s orbital of In in In ₂ O ₃ forms a conductive path, and conductivity is determined by the presence of appropriate oxygen vacancies. When this conductivity is electrically changed as a semiconductor, it is important to appropriately manage the amount of oxygen vacancies. The energy level formed by the oxygen vacancies is distributed between 15 meV and 150 meV below the conduction band formed by the In5s orbital (Non-Patent Document J. Electrochem. Soc., 123, 299C-310C (1976)). However, when SnO ₂ is added here, the level formed by Sn5s is almost the same as the level formed by oxygen vacancies, so that it is possible to absorb changes in electrical characteristics due to some variation in the amount of oxygen vacancies. It is done.
On the other hand, when Ga, such as IGZO, is added, no level is formed in the band gap, so the amount of oxygen deficiency directly affects the carrier concentration of the channel, that is, the transistor characteristics.

  As described above, an oxide semiconductor composed of In, Sn, and Zn is a material excellent in principle to obtain a transistor with excellent operation reliability that is hardly affected by some change in oxygen deficiency. Impurities that may form levels other than oxygen vacancies should be avoided as much as possible. Further, the presence of impurities in the semiconductor interface in addition to the semiconductor bulk causes deterioration of reliability such as Vth shift.

  For this reason, in the transistor formed of an oxide semiconductor composed of In, Sn, and Zn, the quality of the insulating film and the protective film in contact with the semiconductor interface is more important than other semiconductor materials such as IGZO.

  The channel length (L) of the semiconductor film is preferably 1 to 50 μm, more preferably 3 to 40 μm, and particularly preferably 5 to 25 μm. If it is 50 μm or less, the size of the transistor does not become too large, and the degree of integration is difficult to decrease. When it is 1 μm or more, high accuracy is not required for photolithography, and it can be adopted without any problem even in a large-area display or the like.

  The channel width (W) is preferably 1 to 500 μm, more preferably 3 to 100 μm, and particularly preferably 5 to 50 μm. If it is 500 μm or less, the transistor does not become too large, and the degree of integration is difficult to decrease. Also, it is difficult for abnormal operation due to insufficient heat dissipation. When the thickness is 1 μm or more, high accuracy is required for photolithography, which may make it difficult to employ in a large area display or the like.

  The film thickness of the semiconductor film is preferably 15 to 100 nm.

The semiconductor film can be formed by DC, AC, or RF sputtering using a target made of a predetermined material.
Further, it is preferable to heat-treat at 70 to 450 ° C. in an oxygen atmosphere and / or an inert gas atmosphere after forming a channel layer and its protective film on the substrate.

  When it is 70 ° C. or higher, the thermal stability and heat resistance of the obtained transistor are unlikely to decrease. Also, it is difficult for mobility to decrease, S value to increase, and threshold voltage to increase. On the other hand, when the temperature is lower than 450 ° C., a substrate having no heat resistance can be used. Also, the equipment cost for heat treatment is not too large.

Furthermore, since the threshold value and the hump may be improved by irradiating the semiconductor film with O ₂ plasma or N ₂ O plasma before and after the formation of the protective film, it can be performed as necessary.

  There is no restriction | limiting in particular about the material of a board | substrate, A well-known thing can be used in this technical field. For example, glass substrates such as alkali silicate glass, non-alkali glass and quartz glass, silicon substrates, resin substrates such as acrylic, polycarbonate and polyethylene naphthalate (PEN), polymer film bases such as polyethylene terephthalate (PET) and polyamide Materials can be used.

There are no particular limitations on the material for forming each of the gate electrode, the source electrode, and the drain electrode, and any material generally used can be selected as long as the effects of the present invention are not lost. For example, transparent electrodes such as indium tin oxide (ITO), indium zinc oxide, ZnO, SnO ₂ , metal electrodes such as Al, Ag, Cr, Ni, Mo, Au, Ti, Ta, Cu, or these An alloy metal electrode can be used.

Each component (layer) of the semiconductor device can be formed by a technique known in this technical field.
Specifically, as a film formation method, a chemical film formation method such as a spray method, a dip method, or a CVD method, or a physical film formation method such as a sputtering method, a vacuum evaporation method, an ion plating method, or a pulse laser deposition method. The method can be used. It is preferable to use a physical film forming method because the carrier density is easily controlled and the film quality can be easily improved, and among these, it is more preferable to use a sputtering method because of high productivity.
The formed film can be patterned by various etching methods.

The semiconductor device of the present invention includes at least a gate electrode, a gate insulating film, a semiconductor film, a source and drain electrode, and a protective film on a substrate. The semiconductor film contains In (indium), Zn (zinc), Sn (tin), and O (oxygen).
In addition, the interface state density (interface trap density) existing at the interface between the gate insulating film or protective film, which is a dielectric, and the semiconductor film is 1 × 10 ¹⁰ cm below 0.5 eV from the conduction band of the semiconductor film. ⁻² eV ⁻¹ or more and less than 1 × 10 ¹² cm ⁻² eV ⁻¹ .

The interface state density is preferably 1 × 10 ¹⁰ cm ⁻² eV ⁻¹ or more and less than 5 × 10 ¹¹ cm ⁻² eV ⁻¹ . The interface state density can be measured by the method described in IEEE transactions on electron devices, vol. 58, No. 9, 2011, specifically by the method described in the examples.

  By setting the interface state density at the interface between the gate insulating film or the protective film and the semiconductor film as described above, a TFT with high mobility and high reliability (ΔVth is small) can be obtained.

The semiconductor device of the present invention can be manufactured by the above manufacturing method.
In addition, constituent members and the like in the semiconductor device of the present invention are the same as those described in the above manufacturing method.

  The semiconductor device of the present invention can be used for various integrated circuits such as a field effect transistor, a logic circuit, a memory circuit, and a differential amplifier circuit.

Example 1
A field effect transistor 1 having a bottom gate structure shown in FIG. 1 was produced.
A non-alkali glass substrate 10 having a diameter of 4 inches was prepared, a Cr film having a thickness of 50 nm was formed by a sputtering method, and then patterned into a gate wiring shape by a photolithography method to form a gate electrode 20. Next, this substrate was set in a PE-CVD apparatus, and was first evacuated so that the degree of vacuum in the system was 1 × 10 ⁻⁵ Pa. Next, SiH ₄ , N ₂ O, and N ₂ were introduced to obtain a gate insulating film 30 (SiO ₂ film) having a thickness of 150 nm at 350 ° C.

Next, this glass substrate with a gate insulating film was mounted on a sputtering apparatus, and ITZO was deposited under the following conditions to form a 45 nm channel layer (semiconductor film). Next, it was processed into the shape of a semiconductor region by photolithography to form a channel layer 40 (semiconductor film).
Ultimate vacuum: 5 × 10 ⁻⁴ Pa
Sputtering pressure: 0.5Pa
Sputtering gas: O ₂ / Ar = 15/15 sccm
Sputtering power: DC100W

The substrate was set again in the PE-CVD apparatus, and first, the system was evacuated so that the degree of vacuum in the system was 1 × 10 ⁻⁵ Pa. Next, SiH ₄ , N ₂ O, and N ₂ were introduced, and an interlayer insulating film 50 (semiconductor layer protective film, etch stop layer: SiO ₂ ) having a thickness of 200 nm was stacked at 170 ° C. Next, this substrate was set in a dry etching apparatus, and contact holes for gate electrodes and source / drain electrodes were formed. Then, this laminated body was set in a sputtering apparatus, and after ITO was formed into a film, patterning was again performed by a photolithography method to form a source electrode 60 and a drain electrode 62.

Subsequently, this substrate was set in a PECVD apparatus, SiH ₄ , N ₂ O, and N ₂ were introduced, and a passivation film 70 (SiO ₂ ) having a thickness of 200 nm was formed at 170 ° C. Then, contact holes for source / drain / gate electrodes were formed again by photolithography. Finally, this substrate was annealed in nitrogen at 350 ° C. for 1 hour to obtain a field effect transistor 1.

The obtained field effect transistor 1 was evaluated as follows. The results are shown in Table 1.
(1) Field-effect mobility (μ), off-current Using a semiconductor parameter analyzer (Caseley 4200), the TFT at the center of a 4-inch glass was measured in a dry nitrogen atmosphere at atmospheric pressure at room temperature and in a light-shielding environment. The off-current was measured with a gate-source voltage (Vgs) of −5V.

(2) Threshold voltage shift amount (ΔVth: stress test, reliability, performance evaluation)
The stress condition was that a voltage of +20 V was applied to the gate electrode for 10,000 seconds at 50 ° C. in air. The threshold voltage shift amount (ΔVth) was measured by comparing Vth before and after applying stress. As a result, ΔVth = 0.1V was favorable.
Further, the measured ΔVth was evaluated as follows. That is, 0.2 or less was “◯”, 0.2 to 0.7 or less was “Δ”, and 0.7 or more was “x”.

(3) Interface trap density The interface trap density of the oxide semiconductor was calculated as follows. The source / drain electrodes were short-circuited, and a voltage represented by V = Vg + V0sin ωt was applied between the gate and the source at Vg = −5 V to 10 V and a frequency of 1 Hz, and plotted against the obtained current value (FIG. 2). The capacitance-gate voltage characteristics obtained in this manner reflect the distribution of interface traps. By simulating this according to the method of non-patent literature (IEEE transactions on electron devices, vol. 58, No. 9, 2011), the trap density at the semiconductor interface can be obtained as a function of energy from the conduction band. As a result, the trap density at 0.5 eV below the conduction band was 9 × 10 ¹⁰ cm ⁻² eV ⁻¹ .

Examples 2-6
The TFT was fabricated in the same manner as in Example 1 except that the ultimate vacuum when the gate insulating film and the etch stopper film were formed by CVD, the material composition of the target, and the annealing temperature after TFT fabrication were changed as shown in Table 1. Prepared and evaluated. The results are shown in Table 1.

Comparative Example 1
A TFT was fabricated and evaluated in the same manner as in Example 1 except that the ultimate vacuum when the gate insulating film and the etch stopper film were formed by CVD was changed as shown in Table 1. The results are shown in Table 1.

Comparative Example 2
A TFT was fabricated and evaluated in the same manner as in Example 3 except that the composition of the target was IGZO (In: Ga: Zn = 1: 1: 1). The results are shown in Table 1.

In Examples 1 to 6, TFTs were fabricated with the ultimate vacuum of the CVD apparatus during film formation of the gate insulating film and the etch stopper film being set to 1 × 10 ⁻⁵ Pa to 1 × 10 ⁻³ Pa. Showed sex. This is also indicated by the fact that the interface trap density is 15 × 10 ¹⁰ cm ⁻² eV ⁻¹ or less.

In Comparative Example 1, since the ultimate vacuum was 1 × 10 ⁻² Pa, the interface trap density was extremely high, and ΔVth was also increased to 0.8V.

  In Comparative Example 2, IGZO was used as a target. Although the ultimate vacuum of CVD was appropriately set, the oxide semiconductor material of Comparative Example 2 did not contain tin, so that the interface trap density was increased. Further, although the reliability is not bad, ΔVth was 0.5V.

  The semiconductor device of the present invention can be used for various integrated circuits such as a field effect transistor, a logic circuit, a memory circuit, and a differential amplifier circuit.

1 Field Effect Transistor 10 Substrate 20 Gate Electrode 30 Gate Insulating Film 40 Semiconductor Film 50 Protective Film 60 Source Electrode 62 Drain Electrode 70 Passivation Film

Claims (6)

A manufacturing method of a semiconductor device including at least a gate electrode, a gate insulating film, a semiconductor film, a source and drain electrode, and a protective film on a substrate, wherein the semiconductor film is made of In (indium), Zn (zinc), Sn ( It includes tin) and O (oxygen), the rear formation of the semiconductor film, the pressure in the film forming apparatus before the formation during the formation of the protective film, 5 × 10 -6 ^Pa or more 5 × 10 ^- The manufacturing method of the semiconductor device made into ³ Pa or less. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the pressure in the film formation apparatus before film formation when forming the gate insulating film is set to 5 × 10 ⁻⁶ Pa or more and 5 × 10 ⁻³ Pa or less. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor film contains In, Zn, and Sn in the following atomic ratio.
0.2 ≦ In / (In + Sn + Zn) ≦ 0.8
0.1 <Zn / (In + Sn + Zn) ≦ 0.6
0.001 ≦ Sn / (In + Sn + Zn) ≦ 0.5 A semiconductor device including at least a gate electrode, a gate insulating film, a semiconductor film, a source and drain electrode, and a protective film on a substrate, wherein the semiconductor film includes In (indium), Zn (zinc), Sn (tin), and The interface state density at the interface between the gate insulating film or the protective film and the semiconductor film containing O (oxygen) is 1 × 10 ¹⁰ cm under 0.5 eV from the conduction band of the semiconductor film. ⁻² eV ⁻¹ or more and less than 1 × 10 ¹² cm ⁻² eV ⁻¹ . The semiconductor device according to claim 4, wherein the semiconductor film contains In, Zn, and Sn in the following atomic ratio.
0.2 ≦ In / (In + Sn + Zn) ≦ 0.8
0.1 <Zn / (In + Sn + Zn) ≦ 0.6
0.001 ≦ Sn / (In + Sn + Zn) ≦ 0.5   An electronic apparatus using the semiconductor device according to claim 4.

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