JP2013207100A - Thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin-film transistor including an oxide semiconductor layer that has excellent switching characteristics and excellent stress resistance, especially has a small threshold-voltage change value before and after application of stress and excellent stability.SOLUTION: A thin-film transistor includes, on a substrate, at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source-drain electrode, and a protective film. The oxide semiconductor layer is a stack having a first oxide semiconductor layer composed of at least one kind of element selected from a group consisting of In, Zn, and Sn, and a second oxide semiconductor layer containing at least one element selected from a group consisting of In, Zn and Sn and at least one kind of element selected from Hf, Ge, and Nb. The second oxide semiconductor layer is formed between the first oxide semiconductor layer and the gate insulating film and/or between the first oxide semiconductor layer and the protective film.

Description

  The present invention relates to a thin film transistor (TFT) used in a display device such as a liquid crystal display or an organic EL display.

  Amorphous (amorphous) oxide semiconductors have higher carrier mobility (also referred to as field-effect mobility, hereinafter sometimes referred to simply as “mobility”) compared to general-purpose amorphous silicon (a-Si). In addition, since it has a large optical band gap and can be formed at a low temperature, it is expected to be applied to next-generation displays that require large size, high resolution, and high-speed driving, and resin substrates with low heat resistance.

  Among oxide semiconductors, amorphous oxide semiconductors composed of indium, gallium, zinc, and oxygen (In-Ga-Zn-O, hereinafter sometimes referred to as "IGZO"), indium, zinc, tin, and An amorphous oxide semiconductor made of oxygen (In—Zn—Sn—O, hereinafter sometimes referred to as “IZTO”) has a very high carrier mobility, and thus is preferably used. For example, in Non-Patent Documents 1 and 2, an oxide semiconductor thin film of In: Ga: Zn = 1.1: 1.1: 0.9 (atomic% ratio) is used as a semiconductor layer (active layer) of a thin film transistor (TFT). What was used is disclosed. Patent Document 1 includes an element such as In, Zn, Sn, and Ga, and Mo, and the atomic composition ratio of Mo with respect to the total number of metal atoms in the amorphous oxide is 0.1 to 5 atomic%. An amorphous oxide is disclosed, and an example discloses a TFT using an active layer in which Mo is added to IGZO.

  In the case of using an oxide semiconductor as a semiconductor layer of a thin film transistor, not only has a high carrier concentration (mobility) but also excellent switching characteristics (transistor characteristics and TFT characteristics) of the TFT are required. Specifically, (1) the on-current (the maximum drain current when a positive voltage is applied to the gate electrode and the drain electrode) is high, and (2) the off-current (a negative voltage is applied to the gate electrode and a positive voltage is applied to the drain voltage). (3) S value (Subthreshold Swing, subthreshold swing, gate voltage required to increase the drain current by one digit) is low, and (4) threshold value (on drain electrode) When a positive voltage is applied and a positive or negative voltage is applied to the gate voltage, the drain current begins to flow, also called the threshold voltage, and is stable over time (uniform across the substrate) And (5) high mobility is required.

  Further, a TFT using the oxide semiconductor layer is required to have excellent resistance to stress (stress resistance) such as voltage application or light irradiation. For example, when a voltage is continuously applied to the gate electrode or a blue band where light absorption starts is continued, a charge is trapped at the interface between the gate insulating film and the semiconductor layer of the thin film transistor, and the threshold voltage is shifted. It has been pointed out that the switching characteristics change. In addition, when the liquid crystal panel is driven or when the pixel is turned on by applying a negative bias to the gate electrode, light leaked from the liquid crystal cell is irradiated to the TFT. This light stresses the TFT and causes deterioration of characteristics. It becomes. When a thin film transistor is actually used, if the switching characteristics change due to stress due to voltage application, the reliability of the display device itself such as a liquid crystal display or an organic EL display is lowered. For example, in the case of an organic EL display, when the switching characteristics change, it is necessary to pass a current of several μA or more to cause the organic EL element to emit light. Therefore, improvement of stress tolerance (the amount of change before and after stress application is small) is eagerly desired.

  For example, in an organic EL display, a positive voltage continues to be applied to the gate electrode of the driving TFT while the organic EL element emits light. However, charges are trapped at the interface between the gate insulating film and the semiconductor layer by the voltage application, and the threshold value The problem is that the voltage changes. Further, it is necessary to pass a current of several μA or more in order to cause the organic EL element to emit light, and a transistor element having high mobility and high stability is required.

The deterioration of TFT characteristics due to stress such as voltage application or light irradiation is caused by defects formed at the semiconductor itself or at the interface between the semiconductor and the gate insulating film during stress application. Insulators such as SiO ₂ , Al ₂ O ₃ , and HfO ₂ are generally used as the gate insulating film, but the interface between the semiconductor layer and the insulating film is where different materials are in contact, and defects are particularly formed. It is considered easy. In order to improve stress resistance, it is considered that handling of the interface between the oxide semiconductor layer and the insulating film is particularly important.

  In order to solve the above problem, for example, Patent Document 2 discloses that the gate insulating film includes In-M-Zn (including at least one of M = Ga, Al, Fe, Sn, Mg, Cu, Ge, and Si). There is disclosed a method for improving stability by suppressing defects due to grain boundaries by using an amorphous oxide. However, when the method according to this document is used, since the gate insulating film contains In which easily forms oxygen defects, defects at the interface between the gate insulating film and the semiconductor layer increase, and stability may be lowered.

A similar problem is also observed in a protective film formed to protect the source-drain electrodes. That is, since the insulator such as SiO ₂ is generally used for the protective film, the interface between the semiconductor layer and the protective film is liable to form defects due to the contact of different materials, and the interface is the same as the insulating film. There is a possibility that the stability associated with the increase in defects will decrease.

JP 2009-164393 A JP 2007-73701 A

Solid Physics, VOL44, P621 (2009) Nature, VOL432, P488 (2004)

  The present invention has been made in view of the above circumstances, and an object of the present invention is to have good switching characteristics and stress resistance of a thin film transistor including an oxide semiconductor layer, and in particular, a threshold voltage change amount before and after stress application is small. An object of the present invention is to provide a thin film transistor having excellent stability.

  A thin film transistor according to the present invention that can solve the above-described problems has a gate electrode, a gate insulating film, and an oxide semiconductor layer, a source-drain electrode, and a protective film for protecting the source-drain electrode on a substrate. The oxide semiconductor layer includes a first oxide semiconductor layer composed of at least one element (Z group element) selected from the group consisting of In, Zn, and Sn; and In, Zn, and Sn. A second oxide semiconductor layer containing at least one element selected from the group consisting of (X group element) and at least one element selected from the group consisting of Hf, Ge and Nb (Y group element); And the second oxide semiconductor layer is between the first oxide semiconductor layer and the gate insulating film, and / or It includes the features that are formed between the protective film and the first oxide semiconductor layer.

  In carrying out the present invention, the oxide semiconductor layer has a two-layer structure of the first oxide semiconductor layer and the second oxide semiconductor layer, and the second oxide semiconductor layer includes: The oxide semiconductor layer is in contact with the gate insulating film, and the oxide semiconductor layer has a two-layer structure of the first oxide semiconductor layer and the second oxide semiconductor layer. The oxide semiconductor layer is in contact with the protective film, or the oxide semiconductor layer has three layers including the second oxide semiconductor layer formed on both surfaces of the first oxide semiconductor layer. In the structure, one of the second oxide semiconductor layers is in contact with the gate insulating film, and the other of the second oxide semiconductor layers is in contact with the protective film. This is a preferred embodiment.

  In practicing the present invention, the thickness of the second oxide semiconductor layer is preferably 0.5 to 10 nm.

  The present invention also includes a display device including the thin film transistor.

  Since the thin film transistor of the present invention is excellent in switching characteristics and stress resistance, and particularly has a small threshold voltage change before and after stress application, a thin film transistor excellent in TFT characteristics and stress resistance can be provided. Therefore, the display device including the thin film transistor of the present invention is excellent in electrical stability.

FIG. 1 is a schematic cross-sectional view for explaining a thin film transistor including a stacked body (lower side) of a first oxide semiconductor layer (upper side) and a second oxide semiconductor layer as an oxide semiconductor layer used in the present invention. FIG. FIG. 2 is a schematic cross-sectional view for explaining a thin film transistor including a stacked body (upper side) of a first oxide semiconductor layer (lower side) and a second oxide semiconductor layer as an oxide semiconductor layer used in the present invention. FIG. FIG. 3 shows a first oxide semiconductor layer (center), a stack of second oxide semiconductor layers (upper side), and a second oxide semiconductor layer (lower side) as oxide semiconductor layers used in the present invention. It is a schematic sectional drawing for demonstrating the thin-film transistor provided with (etching stopper layer is not provided). FIG. 4 illustrates a first oxide semiconductor layer (center), a stack of second oxide semiconductor layers (upper side), and a second oxide semiconductor layer (lower side) as oxide semiconductor layers used in the present invention. 1 is a schematic cross-sectional view (with an etching stopper layer 9) for explaining a thin film transistor including 5 shows a conventional example No. 1 using IZTO as an oxide semiconductor layer. 2 is a diagram showing changes in stress application time and threshold voltage (Vth) in FIG. 6 shows an example No. 1 using a stacked structure of a first oxide semiconductor layer (IZTO: upper side) and a second oxide semiconductor layer (IZTO + Nb: lower side) as an oxide semiconductor layer. 2 is a diagram showing changes in stress application time and threshold voltage (Vth) in FIG. FIG. 7 shows an example in which a stacked structure of a first oxide semiconductor layer (IZTO: upper side) and a second oxide semiconductor layer (IZTO + Nb: lower side) is used as the oxide semiconductor layer. 3 is a diagram showing changes in stress application time and threshold voltage (Vth) in FIG. FIG. 8 shows an example in which a stacked structure of a first oxide semiconductor layer (IZTO: lower side) and a second oxide semiconductor layer (IZTO + Nb: upper side) is used as the oxide semiconductor layer. 4 is a diagram showing changes in stress application time and threshold voltage (Vth) in FIG. FIG. 9 illustrates a stack of a first oxide semiconductor layer (IZTO: center), a second oxide semiconductor layer (IZTO + Nb: upper side), and a second oxide semiconductor layer (IZTO + Nb: lower side) as oxide semiconductor layers. Example No. using the structure 5 is a diagram showing changes in stress application time and threshold voltage (Vth) in FIG. FIG. 10 shows an example in which a stacked structure of a first oxide semiconductor layer (IZTO: upper side) and a second oxide semiconductor layer (IZTO + Ge: lower side) is used as the oxide semiconductor layer. 6 is a diagram showing changes in stress application time and threshold voltage (Vth) in FIG. FIG. 11 shows an example in which a stacked structure of a first oxide semiconductor layer (IZTO: upper side) and a second oxide semiconductor layer (IZTO + Hf: lower side) is used as the oxide semiconductor layer. 7 is a diagram showing changes in stress application time and threshold voltage (Vth) in FIG.

  The present inventors represent an oxide (hereinafter referred to as “IZTO”) containing at least one element selected from the group consisting of In, Zn, and Sn (hereinafter sometimes referred to as “Z group element”). In order to improve TFT characteristics and stress resistance when a TFT active layer (first oxide semiconductor layer) is used, various studies have been made. As a result, a protective film that protects the first oxide semiconductor layer and the gate insulating film and / or the first oxide semiconductor layer and the source-drain electrode (hereinafter, referred to as “protective film” in some cases). And at least one element selected from the group consisting of In, Zn and Sn (hereinafter sometimes referred to as “X group element”) and a group consisting of Hf, Ge and Nb. The intended purpose is achieved by interposing an oxide semiconductor layer (second oxide semiconductor layer) containing at least one kind of element (hereinafter sometimes referred to as “Y group element”). The present invention has been completed.

  A second oxide semiconductor layer containing an X group element and a Y group element is provided between the gate insulating film and the first oxide semiconductor layer and / or between the protective film and the first oxide semiconductor layer. It has been found that the TFT is superior in TFT characteristics and stress resistance as compared with the case where Mo described in Patent Document 1 or an element other than the Y group element is used.

  The first oxide semiconductor layer used in the present invention is not particularly limited as long as it is an oxide semiconductor layer used in a display device, and a known one can be used. In the present invention, the second oxide semiconductor layer is interposed between the first oxide semiconductor layer and the gate insulating film and / or the protective film, and the composition of the second oxide semiconductor layer is specified. There is a feature.

  First, the metal (Z group element: In, Zn, Sn) which is a base material component constituting the first oxide semiconductor layer of the present invention will be described.

  Among oxide semiconductors, an amorphous oxide semiconductor composed of at least one selected from the group consisting of In, Zn, and Sn has higher carrier mobility than general-purpose amorphous silicon (a-Si). The optical band gap is large, and the film can be formed at a low temperature. A Z group element may be added independently and may use 2 or more types together.

  The oxide semiconductor containing the metal (In, Zn, Sn) is not particularly limited as long as it is used for a display device. ZnO, Al-doped ZnO, In—Zn—O (IZO), In—Sn— An oxide semiconductor such as O (ITO), Zn—Sn—O (ZTO), or In—Zn—Sn—O (IZTO) is used.

  About the said metal (In, Zn, Sn), the ratio between each metal will not be specifically limited if the oxide containing these metals has an amorphous phase, and is a range which shows a semiconductor characteristic.

  Specifically, with respect to Zn, the proportion of Zn in all metals is preferably 80 atomic% or less. When the Zn ratio exceeds 80 atomic%, the oxide semiconductor film is crystallized and a grain boundary trap level is generated, so that carrier mobility is reduced and processing by wet etching becomes difficult, which causes adverse effects on transistor fabrication. Arise. More preferably, the Zn ratio is 70 atomic% or less. The lower limit of Zn is preferably 20 atomic% or more, more preferably 30 atomic% or more, considering that an amorphous structure is taken into consideration.

  The metals other than Zn (In, Sn) may be appropriately controlled so that Zn is controlled within the above range and the ratio of each metal element (atomic% ratio) satisfies the range described later. Specifically, In is an element that enhances mobility, and in order to exhibit an effective effect, the ratio of In to all metals is preferably 10 atomic% or more, more preferably 25 atomic% or more. On the other hand, if the In ratio becomes too high, stress resistance is lowered and it becomes easy to make a conductor (a state in which switching is not performed). In addition, Sn increases in mobility as the Sn ratio in all metals increases, but the S value and Vth value increase to reduce TFT characteristics and stress resistance. The ratio of Sn is preferably 50 atomic% or less.

  Next, the second oxide semiconductor layer is described. As described above, in the present invention, the second group containing the X group element and the Y group element useful for improving TFT characteristics and stress between the gate insulating film and / or the protective film and the first oxide semiconductor layer. The greatest feature is that an oxide semiconductor layer is used.

  The second oxide semiconductor layer in the present invention includes at least one element selected from the group consisting of In, Zn and Sn (group X element) and at least one selected from the group consisting of Hf, Ge and Nb. It contains an element (Y group element). X group element may be added independently and may use 2 or more types together. Moreover, a Y group element may also be added independently and may use 2 or more types together.

  The X group element constituting the second oxide semiconductor layer also has a high carrier mobility, a large optical band gap, and can be formed at a low temperature, like the first oxide semiconductor layer. The X group element that is a main element constituting the second oxide semiconductor layer is at least one element selected from the group consisting of In, Zn, and Sn. Further, the ratio of each metal element (X group element: In, Zn, Sn) which is a base material component constituting the second oxide semiconductor layer of the present invention is also the first oxide semiconductor layer (Z group element). As long as the oxide containing these metals has an amorphous phase and exhibits semiconductor characteristics, it is not particularly limited, and can be appropriately set within the same range as the Z group element.

  However, the oxide semiconductor layer of the present invention is a stacked body of a first oxide semiconductor layer and a second oxide semiconductor layer, and the first oxide semiconductor layer and the second oxide semiconductor layer are integrated. Since it has a semiconductor function, it is desirable from the viewpoint of ensuring reliability that the first oxide semiconductor layer and the second oxide semiconductor layer have the same carrier mobility, optical band gap, and the like. Therefore, the type of the X group element included in the second oxide semiconductor layer and the ratio between the elements are the same as the type of the Z group element included in the first oxide semiconductor layer and the ratio between the elements. Is desirable.

  In the present invention, mobility, stress resistance, and the like are improved by interposing the second oxide semiconductor layer between the first oxide semiconductor layer and the gate insulating film and / or the protective film. It is inferred that by interposing the second oxide semiconductor layer at the interface between the first oxide semiconductor layer and the gate insulating film and / or the protective film, defects at the interface are reduced and the structure is stabilized. Is done.

That is, since the Z group element (In, Zn, Sn) constituting the first oxide semiconductor layer has a weak bond with oxygen, the first oxide semiconductor layer is in direct contact with the gate insulating film or the protective film. In this case, since the gate insulating film and the protective film are made of an insulator such as SiO ₂ , the interface between the oxide semiconductor layer and the insulating film, and the interface between the oxide semiconductor layer and the protective film is caused by contact of different materials. Thus, trap levels due to oxygen defects are easily formed at the interface of the first oxide semiconductor layer. Such a trap level causes a decrease in mobility of the thin film transistor and a decrease in stability.

  Therefore, in the present invention, the second oxide semiconductor layer containing an element (Y group element) that forms a stable oxide is interposed at the interface between the first oxide semiconductor layer and the gate insulating film and / or the protective film. Thus, the defect density at the interface between the gate insulating film and / or the protective film and the first oxide semiconductor layer is reduced. However, even an element capable of forming the above stable oxide cannot use an element that lowers the bulk mobility and carrier density of the semiconductor layer or greatly deteriorates the thin film transistor characteristics.

  In the present invention, at least one element selected from the group consisting of Hf, Ge, and Nb can be used as the Y group element. These elements are elements that have lower oxide free energy of formation than In, Zn, and Sn, and are strongly bonded to oxygen to form a stable oxide, and are within the range preferably defined in the present invention (in all metal atoms). , 0.5 to 8.0 atomic%), it is an element effective in improving stability without substantially reducing mobility. The Y group element has the property that it does not diffuse in the oxide semiconductor to form hillocks at the interface, and the S orbitals become conduction electrons and do not form a localized electronic state in the oxide. These elements may be added alone or in combination of two or more. Preferably it is Ge and / or Nb, More preferably, it is Nb.

  Although the detailed mechanism of the characteristic improvement by the addition of the Y group element is unknown, the Y group element has an effect of suppressing the generation of oxygen vacancies that cause surplus electrons in the oxide semiconductor as compared with other elements. It is assumed that there is. Oxygen deficiency is reduced by the addition of the Y group element, and defects at the interface of the first oxide semiconductor layer are suppressed, so that the oxide has a stable structure and is resistant to stress such as voltage and light. It is thought to improve.

  Preferred total content of Y group element with respect to the total content of all metals (X group element and Y group element) constituting the second oxide semiconductor layer ([Y group element / (X group element + Y group element)]) May be determined in consideration of carrier density and semiconductor stability. When the total content of the Y group elements is too small, the lower limit of the ratio of the total content of the Y group elements (which is a single ratio when including alone, or the total ratio when including two or more) is too small. Since the effect of suppressing the occurrence of oxygen vacancies cannot be obtained sufficiently, it is preferably 0.5 atomic% or more. On the other hand, if the total content of the Y group elements is too large, the carrier density in the semiconductor is decreased, and the on-current is decreased. Therefore, the content is preferably 8.0 atomic% or less, more preferably 7. It is desirable that the content be 5 atomic percent or less, more preferably 5.0 atomic percent or less, and still more preferably 3.0 atomic percent or less.

  Examples of a preferable composition of the second oxide semiconductor layer include the following.

  (A) In-Zn-X group element-O: A preferable ratio (atomic% ratio) of In and Zn in metal elements (In, Zn) excluding the X group element is, for example, In: Zn = 2: 1 to 1: 1.

  (A) A preferred ratio (atomic% ratio) of Zn and Sn in the metal elements (Zn, Sn) excluding the Zn—Sn—X group element-O: X group element is, for example, Zn: Sn = 2: 1 to 1: 1.

  (C) In—Zn—Sn—X group element —O: The preferred ratio (atomic% ratio) of In, Zn, and Sn in metal elements (In, Zn, Sn) excluding the X group element is generally In: Zn: Sn = 1: 2: 1.

  The thickness of the first oxide semiconductor layer constituting the oxide semiconductor layer of the present invention is not particularly limited. However, if the thickness of the first oxide semiconductor layer is too thin, characteristics (mobility, Since TFT characteristics such as S value and Vth may vary, it is preferably 10 nm or more, more preferably 30 nm or more. On the other hand, if the thickness of the first oxide semiconductor layer is too thick, it may take time to form a film and the production cost may increase. Therefore, the thickness is preferably 200 nm or less, more preferably 80 nm or less.

  The thickness of the second oxide semiconductor layer is not particularly limited, but if the thickness of the second oxide semiconductor layer is too thin, the effect of forming the second oxide semiconductor layer may not be sufficiently exhibited. Therefore, it is preferably 0.5 nm or more, and more preferably 1 nm or more. On the other hand, if the thickness of the second oxide semiconductor layer is too large, the mobility may be lowered. Therefore, the thickness is preferably 20 nm or less, more preferably 10 nm or less.

  The oxide semiconductor layer of the present invention has a stacked structure of a first oxide semiconductor layer and a second oxide semiconductor layer, but there is no particular limitation on the structure thereof. As described above, the first oxide semiconductor layer easily forms trap levels due to oxygen vacancies at the interface with the gate insulating film and the protective film, which causes a decrease in mobility and stability. By forming the second oxide semiconductor layer between the first oxide semiconductor layer and the gate insulating film and / or the protective film, such problems can be solved and TFT characteristics and stress resistance can be improved. Can do. There is no particular limitation on the stacked structure of the first oxide semiconductor layer and the second oxide semiconductor layer, and a desired structure can be employed. Therefore, the second oxide semiconductor layer may be formed between the first oxide semiconductor layer and the gate insulating film. Specifically, as illustrated in FIG. The oxide semiconductor layer 4 and the second oxide semiconductor layer 4 ′ are stacked (two-layer structure), and the second oxide semiconductor layer 4 ′ is in contact with the gate insulating film 3. But you can. Alternatively, it may be formed between the first oxide semiconductor layer and the protective film. Specifically, as illustrated in FIG. 2, the oxide semiconductor layer includes the first oxide semiconductor layer 4 and the second oxide semiconductor layer. The second oxide semiconductor layer 4 ′ may be in contact with the protective film 6 in a stacked body (two-layer structure) with the physical semiconductor layer 4 ′. Alternatively, it may be formed between the first oxide semiconductor layer and the gate insulating film and between the first oxide semiconductor layer and the protective film. Specifically, as shown in FIG. The semiconductor layer has a three-layer structure with the second oxide semiconductor layer (4 ′, 4 ″) formed on both surfaces of the first oxide semiconductor layer 4, and one of the second oxide semiconductor layers The semiconductor layer 4 ′ ′ may be in contact with the gate insulating film 3 and the other second oxide semiconductor layer 4 ′ may be in contact with the protective film 6.

  The oxide semiconductor layer used in the present invention has been described above.

  The first oxide semiconductor layer and the second oxide semiconductor layer are preferably formed using a sputtering target (hereinafter, also referred to as “target”) by a sputtering method. According to the sputtering method, a thin film having excellent in-plane uniformity of components and film thickness can be easily formed. Alternatively, the oxide may be formed by a chemical film formation method such as a coating method.

  As a target used in the sputtering method, it is preferable to use a sputtering target containing the above-described elements and having the same composition as the desired oxide, whereby a thin film having a desired component composition can be formed with little composition deviation. . Specifically, an oxide target including at least one element selected from the group consisting of In, Zn, and Sn is used as a target for forming the first oxide semiconductor layer.

  Further, as a target for forming the second oxide semiconductor layer, at least one element selected from the group consisting of In, Zn, and Sn (X group element) and the Y group consisting of Hf, Ge, and Nb are used. An oxide target containing at least one selected element (Y group element) can be used.

  In the case where the first oxide semiconductor layer and the second oxide semiconductor layer are formed by sputtering, it is desirable that the first oxide semiconductor layer and the second oxide semiconductor layer be continuously formed while maintaining a vacuum state. When the first oxide semiconductor layer and the second oxide semiconductor layer are formed and exposed to the atmosphere, moisture and organic components in the air adhere to the surface of the thin film, causing contamination (quality defects). Because.

  For the second oxide semiconductor layer, the sputtering target used for forming the first oxide semiconductor layer can be used. That is, even if the sputtering target used for forming the first oxide semiconductor layer and the sputtering target of the Y group element are simultaneously sputtered (for example, co-sputtering by chip-on), the second oxide semiconductor layer is formed. good. As described above, by using the sputtering target used for the first oxide semiconductor layer, the type of the X group element contained in the second oxide semiconductor layer and the ratio between the elements can be changed. It can be made the same with the kind of Z group element contained in a layer, and the ratio between each element.

  The target can be manufactured by, for example, a powder sintering method.

When sputtering using the above target, it is preferable to control the substrate temperature within the range of room temperature to 200 ° C. and appropriately control the amount of oxygen added. The oxygen addition amount may be appropriately controlled according to the configuration of the sputtering apparatus, the target composition, and the like, but it is preferable to add the oxygen amount so that the semiconductor carrier concentration is approximately 10 ¹⁵ to 10 ¹⁶ cm ⁻³ . Further, it is preferable to appropriately control the gas pressure at the time of sputtering film formation, the input power to the sputtering target, the distance between TS (distance between the sputtering target and the substrate), and the like. For example, the total gas pressure at the time of film formation is preferably as low as possible so that sputtering discharge is stabilized, and is preferably controlled within a range of approximately 0.5 to 5 mTorr, and more preferably within a range of 1 to 3 mTorr. . Moreover, the higher the input power, the better, and it is recommended to set the power to approximately 2.0 W / cm ² or more at DC or RF.

  The thin film transistor (TFT) of the present invention only needs to include the above oxide semiconductor layer (a stacked structure of a first oxide semiconductor layer and a second oxide semiconductor layer), and includes other structures including a gate insulating film. Is not particularly limited. For example, the wiring structure of the present invention can be suitably used for a TFT. The TFT only needs to have at least a gate electrode, a gate insulating film, the above-described oxide semiconductor layer, a source electrode, a drain electrode, and a protective film on the substrate, and the configuration is not particularly limited as long as it is normally used. .

  Hereinafter, an embodiment of the TFT manufacturing method will be described with reference to FIG. 4 (the structure in which the etching stopper layer 9 is provided in the configuration of FIG. 3). FIG. 4 and the following manufacturing method show an example of a preferred embodiment of the present invention, and the present invention is not limited to this. FIG. 4 shows an oxide semiconductor having a three-layer structure (stacked in order of a second oxide semiconductor layer 4 ″, a first oxide semiconductor layer 4, and a second oxide semiconductor layer 4 ′ in this order from the substrate side). Although layers are shown, the present invention is not limited to this, and a two-layer structure as shown in FIGS. In addition, for example, FIGS. 1 to 4 illustrate a bottom gate type TFT, but the present invention is not limited to this. A top gate type TFT including a gate insulating film and a gate electrode on an oxide semiconductor layer in this order. Also good. In the top-gate TFT, the second oxide semiconductor layer may be interposed between the first oxide semiconductor layer and the gate insulating film and / or the protective film.

  As shown in FIG. 4, a gate electrode 2 and a gate insulating film 3 are formed on a substrate 1, and a second oxide semiconductor layer 4 '', a first oxide semiconductor layer 4, and a second oxide are formed thereon. A physical semiconductor layer 4 'is formed. A source-drain electrode 5 is formed on the second oxide semiconductor layer 4 ′, a protective film (insulating film) 6 is formed thereon, and the transparent conductive film 8 is formed on the drain electrode 5 through the contact hole 7. Electrically connected.

The method for forming the gate electrode 2 and the gate insulating film 3 on the substrate 1 is not particularly limited, and a commonly used method can be employed. Further, the types of the gate electrode 2 and the gate insulating film 3 are not particularly limited, and those commonly used can be used. For example, as the gate electrode 2, an Al or Cu metal having a low electrical resistivity or an alloy thereof can be preferably used. The gate insulating film 3 is typically exemplified by a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and the like. In addition, oxides such as Al ₂ O ₃ and Y ₂ O ₃ and those obtained by stacking these can also be used.

  Next, an oxide semiconductor layer (a second oxide semiconductor layer 4 ″, a first oxide semiconductor layer 4, and a second oxide semiconductor layer 4 ′) is formed. The second oxide semiconductor layer 4 ′ and the second oxide semiconductor layer 4 ″ are formed of a DC using a sputtering target having the same composition as the X group element and the Y group element constituting the second oxide semiconductor layer. The film may be formed by sputtering or RF sputtering, or may be formed by co-sputtering in which a Y group element chip is mounted on an X group element target.

  Similarly, the first oxide semiconductor layer 4 can also be formed by a DC sputtering method or an RF sputtering method using a sputtering target having the same composition. It is preferable that the second oxide semiconductor layer 4 ′, the first oxide semiconductor layer 4, and the second oxide semiconductor layer 4 ″ are sequentially formed sequentially in a vacuum.

  The oxide semiconductor layer is subjected to patterning after wet etching. Immediately after patterning, it is preferable to perform heat treatment (pre-annealing) to improve the film quality of the oxide semiconductor layer. This increases the on-state current and field-effect mobility of transistor characteristics, thereby improving transistor performance. . Examples of pre-annealing conditions include temperature: about 250 to 400 ° C., time: about 10 minutes to 1 hour, and the like.

After pre-annealing, an etch stopper layer 9 may be formed. The etch stopper layer 9 is generally made of an insulating film such as SiO ₂ . The source / drain electrode 5 may be formed without forming the etch stopper layer 9, but the oxide semiconductor layer may be damaged when the source / drain electrode is etched, and the transistor characteristics may be deteriorated. Therefore, in such a case, it is desirable to form the etch stopper layer 9.

  However, depending on the manufacturing method, the oxide semiconductor layer may not be damaged even if the etch stopper layer is not provided at the time of etching. Therefore, the etch stopper layer may be formed as necessary. For example, when the source-drain electrode is processed by the lift-off method, there is no damage to the semiconductor layer, and therefore no etch stopper layer is required (configuration in FIG. 3).

  The kind of the source-drain electrode 5 is not specifically limited, What is used widely can be used. For example, a metal or alloy such as Al or Cu may be used like the gate electrode, or pure Ti may be used as in the examples described later. A sputtering method is widely used for forming the electrodes.

Thereafter, a protective film 6 is formed on the source-drain electrode 5 by a CVD (Chemical Vapor Deposition) method. As the protective film 6 by the CVD method, SiO ₂ , SiN, SiON or the like is used. Moreover, you may form the protective film 6 using sputtering method. Since the surface of the oxide semiconductor layer is easily rendered conductive by plasma damage due to CVD (probably, oxygen vacancies generated on the surface of the first oxide semiconductor are assumed to be electron donors), and thus the protective film. N ₂ O plasma irradiation may be performed before film formation of 6. As the N ₂ O plasma irradiation conditions, for example, conditions described in the following documents may be adopted.

J. et al. Park et al., Appl. Phys. Lett. , 1993, 053505 (2008).
Next, based on a conventional method, the transparent conductive film 8 is electrically connected to the drain electrode 5 through the contact hole 7. The types of the transparent conductive film and the drain electrode are not particularly limited, and commonly used ones can be used. As a drain electrode, what was illustrated by the source-drain electrode mentioned above, for example can be used.

  EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples. However, the present invention is not limited by the following examples, but may be appropriately modified within a range that can meet the purpose described above and below. Of course, it is possible to implement them, and they are all included in the technical scope of the present invention.

  Based on the above-described method, a TFT having a plurality of oxide semiconductor layers having different configurations was manufactured, and the FTF characteristics before and after the formation of the protective film (insulating film) were evaluated (in this example, the etch stopper layer was not formed). ).

First, on a glass substrate 1 (Corning Eagle XG, diameter 100 mm × thickness 0.7 mm), a Mo thin film of 100 nm as a gate electrode 2 and SiO ₂ (200 nm) as a gate insulating film 3 were sequentially formed. The gate electrode 2 was formed using a pure Mo sputtering target by DC sputtering at a film forming temperature: room temperature, a film forming power: 300 W, a carrier gas: Ar, and a gas pressure: 2 mTorr. The gate insulating film 3 was formed by plasma CVD using a carrier gas: a mixed gas of SiH ₄ and N ₂ O, a film forming power: 100 W, and a film forming temperature: 300 ° C.

  Next, oxide semiconductor layers having various compositions and structures described later were formed by a sputtering method under the following conditions using an oxide sputtering target having a composition corresponding to the composition of the oxide semiconductor layer.

  Specifically, in Table 1, No. 1 (conventional example) is an amorphous IZTO oxide semiconductor layer (atomic ratio In: Zn: Sn = 20: 56.7: 23.3, film thickness: 40 nm: single layer) as a gate insulating film as the oxide semiconductor layer. 3 (the second oxide semiconductor layer 4 ′ is not formed). No. 2, no. 3, no. 6, no. 7 is an example of FIG. 1, and after the second oxide semiconductor layer 4 ′ (IZTO containing Nb, Hf, or Ge) is formed on the gate insulating film 3, the first oxide semiconductor layer 4 (IZTO ) Was formed. No. 4 is an example of FIG. 2, after the first oxide semiconductor layer 4 (IZTO) is formed, the second oxide semiconductor layer 4 ′ (IZTO containing Nb) is formed. No. FIG. 5 shows an example of FIG. 3. After forming the second oxide semiconductor layer 4 ″ (IZTO containing Nb), the first oxide semiconductor layer 4 (IZTO) is formed, and then A second oxide semiconductor layer 4 ′ (IZTO containing Nb) was deposited to form a three-layer stack (FIG. 3).

  Note that for the first oxide semiconductor layer 4, a sputtering target having an In: Zn: Sn ratio (atomic% ratio) of 20: 56.7: 23.3 was used. The X group element of the second oxide semiconductor layer 4 ′ (4 ″) has the same ratio of In: Zn: Sn as the first oxide semiconductor layer, and Nb, Hf, or Ge as the Y group element. (Y group element is the total content of all metals (X group element + Y group element) constituting the second oxide semiconductor layer 4 ′ excluding oxygen (Y group element / (X group element + Y group element)). A target containing 2 atomic%) was used.

  The first oxide semiconductor layer 4 and the second oxide semiconductor layer (4 ′ and 4 ″) are formed continuously (No. 2 to 7) without the chamber being opened to the atmosphere. went. In addition, each content of the metal element in the oxide semiconductor layer thus obtained was analyzed by an XPS (X-ray Photoelectron Spectroscopy) method.

The first oxide semiconductor layer and the second oxide semiconductor layer were both formed by DC sputtering. The apparatus used for sputtering is "CS-200" manufactured by ULVAC, Inc., and the sputtering conditions are as follows.
Substrate temperature: room temperature Gas pressure: 1 mTorr
Oxygen partial pressure: O ₂ / (Ar + O ₂ ) × 100 = 4%

  After forming the oxide semiconductor layer as described above, patterning was performed by photolithography and wet etching. As the wet etchant solution, “ITO-07N” manufactured by Kanto Chemical Co., Inc. was used. In this example, it was confirmed that there was no residue due to wet etching and that etching was appropriately performed for all the oxide semiconductor layers tested.

  After patterning the oxide semiconductor layer, a pre-annealing process was performed to improve the film quality. Pre-annealing was performed at 350 ° C. for 30 minutes in an air atmosphere.

  Next, pure Mo was used, and the source-drain electrode 5 was formed by the lift-off method. Specifically, after patterning using a photoresist, a Mo thin film was formed by DC sputtering (film thickness was 100 nm). The method for forming the Mo thin film for the source-drain electrode is the same as that for the gate electrode 2 described above. Next, unnecessary photoresist was removed by applying an ultrasonic cleaner in an acetone solution, so that the channel length of the TFT was 10 μm and the channel width was 25 μm.

After forming the source-drain electrode 5 in this way, a protective film 6 was formed thereon. As the protective film 6, a laminated film (total film thickness 250 nm) of SiO ₂ (film thickness 100 nm) and SiN (film thickness 150 nm) was used. The formation of the SiO ₂ and SiN was performed using “PD-220NL” manufactured by Samco and using the plasma CVD method. In this example, after the plasma treatment was performed with N ₂ O gas, the SiO ₂ film and the SiN film were sequentially formed. A mixed gas of N ₂ O and SiH ₄ was used for forming the SiO ₂ film, and a mixed gas of SiH ₄ , N ₂ , and NH ₃ was used for forming the SiN film. In any case, the film formation power was 100 W and the film formation temperature was 150 ° C.

  Next, contact holes 7 for probing for transistor characteristic evaluation were formed in the protective film 6 by photolithography and dry etching. Next, an ITO film (film thickness: 80 nm) was formed as the transparent conductive film 8 using a DC sputtering method with a carrier gas: a mixed gas of argon and oxygen gas, a film formation power: 200 W, and a gas pressure: 5 mTorr. 1 TFT was produced.

  Each TFT thus obtained was evaluated for stress resistance as follows.

Evaluation of stress tolerance (light irradiation + negative bias applied as stress)
In this example, an environment (stress) at the time of actual panel driving was simulated, and a stress application test was performed in which light was irradiated while applying a negative bias to the gate electrode. The stress application conditions are as follows. The wavelength of light was selected to be about 400 nm, which is close to the band gap of an oxide semiconductor and whose transistor characteristics tend to fluctuate.
Gate voltage: -20V
Substrate temperature: 60 ° C
Light stress wavelength: 400nm
Illuminance (intensity of light irradiated to TFT): 0.1 μW / cm ²
Light source: LED manufactured by OPTOSUPPLY (Adjust light quantity with ND filter)
Stress application time: 2 hours

  Specifically, the threshold voltage (Vth) before and after the stress application was measured based on the above method, and the difference (ΔVth) was measured. In the present invention, ΔVth (absolute value) is No. in Table 1. A value of 1 or less (4.0 V) was regarded as acceptable.

  Here, the threshold voltage is roughly a value of a gate voltage when the transistor shifts from an off state (a state where the drain current is low) to an on state (a state where the drain current is high). In this embodiment, the voltage when the drain current is in the vicinity of 1 nA between the on-current and off-current is defined as the threshold voltage, and the amount of change (shift amount) of the threshold voltage before and after stress application is measured. did.

Carrier mobility (field effect mobility)
Carrier mobility was calculated in the saturation region using the following equation. In this example, the saturation mobility obtained in this way is No. 1 in Table 1. One having a value of 1 (13.85 cm ² / Vs) of 70% or more (9.7 cm ² / Vs) was regarded as acceptable.

S value The S value (SS value) is the minimum value of the gate voltage required to increase the drain current by one digit. In this embodiment, the S value is No. A value of 1 or less (0.43 V / dec) or less was regarded as acceptable.

  5 to 11 show the relationship between the change amount ΔVth of the threshold voltage of the TFT and the stress application time. FIG. The transistor characteristics of TFT No. 1 are shown. It can be seen that when the gate voltage is increased from −30 V to 30 V, the drain current starts to increase around 0 V, indicating the switching characteristics. However, the threshold voltage Vth shifted to the negative side with the start of stress application, and the change amount ΔVth of the threshold voltage after 2 hours was 4.0V. This is probably because the threshold voltage has shifted because holes generated by light irradiation are accumulated at the interface between the gate insulating film and the oxide semiconductor layer by bias application.

  On the other hand, no. 2-No. 7, the threshold voltage change amount ΔVth of the TFT is No. 7. Compared with 1, the change was small, and the stress application time was 2 hours to 1.25 to 3.50 (FIGS. 6 to 11). From these results, it is possible to apply light and negative bias stress by interposing the second oxide semiconductor layer added with the Y group element between the gate insulating film and / or the protective film and the first oxide semiconductor layer. It was confirmed that there is an effect of suppressing fluctuations in TFT characteristics due to. This is because the interface between the gate insulating film and / or the protective film and the oxide semiconductor layer is obtained by interposing the second oxide semiconductor layer to which the Y group element is added at the gate insulating film interface and / or the protective film interface. It is presumed that the defect is stabilized and defects are hardly formed.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Gate electrode 3 Gate insulating film 4 1st oxide semiconductor layer 4 ', 4''2nd oxide semiconductor layer 5 Source-drain electrode 6 Protective film (insulating film)
7 Contact hole 8 Transparent conductive film 9 Etching stopper layer

Claims (6)

A thin film transistor having a protective film protecting at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source-drain electrode, and a source-drain electrode on a substrate;
The oxide semiconductor layer is
A first oxide semiconductor layer composed of at least one element (Z group element) selected from the group consisting of In, Zn, and Sn;
Second oxidation including at least one element selected from the group consisting of In, Zn and Sn (X group element) and at least one element selected from the group consisting of Hf, Ge and Nb (Y group element) And a laminated body having a physical semiconductor layer,
The second oxide semiconductor layer is formed between the first oxide semiconductor layer and the gate insulating film and / or between the first oxide semiconductor layer and the protective film. A thin film transistor.   The oxide semiconductor layer has a two-layer structure of the first oxide semiconductor layer and the second oxide semiconductor layer, and the second oxide semiconductor layer is in contact with the gate insulating film. The thin film transistor according to claim 1.   The oxide semiconductor layer has a two-layer structure of the first oxide semiconductor layer and the second oxide semiconductor layer, and the second oxide semiconductor layer is in contact with the protective film. The thin film transistor according to claim 1.   The oxide semiconductor layer has a three-layer structure with the second oxide semiconductor layer formed on both surfaces of the first oxide semiconductor layer, and one of the second oxide semiconductor layers is The thin film transistor according to claim 1, wherein the thin film transistor is in contact with the gate insulating film and the other of the second oxide semiconductor layers is in contact with the protective film.   The thin film transistor according to claim 1, wherein the thickness of the second oxide semiconductor layer is 0.5 to 10 nm.   A display device comprising the thin film transistor according to claim 1.