KR20180061751A - Display device, and method of fabricating the same - Google Patents

Abstract

The present invention relates to a display device capable of improving reliability and a manufacturing method thereof. A thin film transistor according to the present invention includes an active layer and a buffer layer located on the lower side of a gate electrode. The deterioration of an interface characteristic between the buffer layer and the active layer can be prevented by arranging an element of a molecular weight of 134 on an interface between the buffer layer and the active layer, thereby improving the device reliability characteristic of the thin film transistor.

Description

DISPLAY APPARATUS AND METHOD OF FABRICATING THE SAME [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a manufacturing method thereof, and more particularly to a display device and a manufacturing method thereof that can improve reliability.

The image display device that realizes various information on the screen is a core technology of the information communication age and it is becoming thinner, lighter, more portable and higher performance. Accordingly, a flat panel display device capable of reducing weight and volume, which is a disadvantage of a cathode ray tube (CRT), has attracted attention.

In a flat panel display device, a thin film transistor (TFT) is used as a switching element and / or a driving element.

The thin film transistor is divided into a thin film transistor using amorphous-silicon, a thin film transistor using poly-silicon, and a thin film transistor using a metal oxide semiconductor depending on a material used as an active layer. Among these, a thin film transistor using a metal oxide semiconductor has a higher mobility than a thin film transistor using an amorphous silicon, a leakage current is significantly higher than a thin film transistor using amorphous silicon and a thin film transistor using polycrystalline silicon Low, and relatively reliable. In addition, a thin film transistor using a metal oxide semiconductor is advantageous in that the uniformity of dispersion of the threshold voltage (Vth) is secured compared to a thin film transistor using polycrystalline silicon.

An active layer of a thin film transistor using such a metal oxide semiconductor is formed on the buffer layer through a sputtering process. However, in the sputtering process, an impact is generated in the buffer layer, and the bonding structure in the buffer layer is disturbed, thereby damaging the inside of the buffer layer. When the active layer is formed on the damaged buffer layer, there is a problem that the interface characteristics between the buffer layer and the active layer are deteriorated and the characteristics and reliability of the thin film transistor are deteriorated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a display device capable of improving reliability and a manufacturing method thereof.

In order to achieve the above object, a thin film transistor according to the present invention includes an active layer and a buffer layer located under the gate electrode, and an element having a molecular weight of 134 is disposed at an interface between the active layer and the buffer layer, The deterioration of the interface characteristics of the thin film transistor can be prevented, and the device reliability characteristics of the thin film transistor can be improved.

The display device and the method for fabricating the same according to the present invention are characterized in that before the active layer is formed, the interface between the active layer and the buffer layer is treated with a plasma treatment gas containing at least one of H2, He, InF, which is an element of " Here, the fluorine ions are combined with oxygen deficiency and by-products (SiOH) in the buffer layer, thereby improving the reliability by removing the trap sites between the buffer layer and the active layer. Further, fluorine ions detected at the interface between the active layer and the buffer layer stabilize the binding of the metal-oxide in the active layer, thereby improving the density of the thin film of the active layer). Accordingly, the present invention can improve the reliability because the surface characteristics of the buffer layer and the interface characteristics between the buffer layer and the active layer are improved.

1 is a cross-sectional view showing a thin film transistor according to the present invention.
2 is a flowchart illustrating a method of manufacturing the thin film transistor shown in FIG.
3A to 3E are cross-sectional views illustrating a method of manufacturing the thin film transistor shown in FIG.
FIG. 4 shows an active layer according to an embodiment of the present invention formed on a plasma surface-treated buffer layer and an active layer according to a comparative example formed on a non-plasma surface-treated buffer layer by a transmission electron microscope (TEM) Fig.
5 is a view showing the components from the surface of the active layer to the buffer layer according to the present invention.
FIG. 6A is an analysis of the interface between the buffer layer and the active layer according to the comparative example of the present invention, and FIG. 6B is an analysis of the interface between the buffer layer and the active layer according to the embodiment of the present invention.
7 is a diagram showing an atom map of the interface between the buffer layer and the active layer of the present invention subjected to the plasma surface treatment.
8 is a diagram showing the gate voltage-drain current of the thin film transistor according to the embodiment and the comparative example of the present invention.
FIG. 9 is a view for explaining capacitance characteristics according to an embodiment of the present invention in which a buffer layer is subjected to a plasma surface treatment and a comparative example in which a plasma surface treatment is not performed.
10 is a view for explaining a liquid crystal display device to which a thin film transistor according to the present invention is applied.
11 is a flowchart for explaining a method of manufacturing the liquid crystal display device shown in FIG.
12 is a view for explaining an organic light emitting display device to which a thin film transistor according to the present invention is applied.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view showing a thin film transistor according to the present invention.

The thin film transistor shown in FIG. 1 includes a buffer layer 102, an active layer 114, a gate insulating pattern 112, a gate electrode 106, a source electrode 108 and a drain electrode 110.

The buffer layer 102 is formed on the substrate 101 formed of plastic resin or glass such as polyimide (PI) or the like, and the uppermost layer is formed of at least one layer structure of SiO2. For example, the buffer layer 102 may be formed as a one-layer structure consisting only of SiO 2 or a two-layer structure of sequentially stacking SiN x and SiO x. The buffer layer 102 serves to prevent diffusion of moisture or impurities generated in the substrate 101.

The active layer 114 is formed of a metal oxide semiconductor containing IZO on the buffer layer 102. For example, the active layer 114 may be formed of indium tin gallium zinc oxide (InSnGaZnO) -based material which is a quaternary metal oxide, indium gallium zinc oxide (InGaZnO) -based material which is a ternary metal oxide, indium tin zinc oxide (InSnZnO) , Indium aluminum zinc oxide (InAlZnO) based material, indium hafnium zinc oxide (InHfZnO), tin gallium zinc oxide (SnGaZnO) based material, aluminum gallium zinc oxide (AlGaZnO) based material, tin aluminum zinc oxide (SnZnO) based material, an aluminum zinc oxide (AlZnO) based material, a zinc magnesium oxide (ZnMgO) based material, a tin magnesium oxide (SnMgO) based material, indium zinc oxide Magnesium oxide (InMgO) -based materials, indium gallium oxide (InGaO) -based materials, indium oxide (InO) -based materials, tin oxide (SnO 2) -based materials, and zinc oxide (ZnO) -based materials. The composition ratio of each element included in each material used for forming the oxide semiconductor is not particularly limited and may be variously adjusted.

The active layer 114 overlaps the gate electrode 106 with the gate insulating pattern 112 interposed therebetween to form a channel region between the source electrode 108 and the drain electrode 110. Such a channel region may be formed in a " U " or " C " shape so as to increase the channel length between the source and drain electrodes 108 and 110, or may be formed in another form.

The gate electrode 106 is formed on the gate insulating pattern 112 in the same pattern as the gate electrode 106 and overlaps the channel region of the active layer 114 with the gate insulating pattern 112 therebetween. Since the gate electrode 106 is located above the active layer 114, the thin film transistor of the present invention is formed with a coplanar structure.

The source electrode 108 is connected to the active layer 114 through the first contact hole CH1 passing through the interlayer insulating film 116. [

The drain electrode 110 faces the source electrode 108 and is connected to the active layer 114 through a second contact hole CH2 penetrating the interlayer insulating film 116. [

The buffer layer 102 of such a thin film transistor is subjected to a plasma surface treatment through a plasma gas such as H2, He or SF6 before forming the active layer 114 as shown in FIG. An element having a molecular weight of 134 is disposed at the interface between the active layer 114 and the buffer layer 102 and at the interface between the interlayer insulating film 116 and the buffer layer 102. [ A method of manufacturing the thin film transistor having the buffer layer 102 will be described in detail with reference to FIG. 2 and FIGS. 3A to 3E.

The buffer layer 102 is formed on the substrate 101 (S11 step) and the entire upper surface of the buffer layer 102 is subjected to plasma treatment (S12 step), as shown in Figs. 2 and 3A.

Specifically, the buffer layer 102 is formed on the substrate 101 by a method such as LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition). Here, the buffer layer 102 is formed to have at least one-layer structure including SiOx.

The upper surface of the buffer layer 102 is subjected to a plasma surface treatment using at least one of He, H _2, and SF ₆ to change the interface film quality of the buffer layer 102. Specifically, the substrate 101 on which the buffer layer 102 is formed is placed in the vacuum chamber 120, and then the buffer layer 102 is subjected to a surface treatment using at least one of He, H _2, and SF ₆ do. At this time, fluorine remains in the chamber 120. The fluorine remaining in the chamber 120 is adsorbed on the surface of the buffer layer 102 by the plasma processing gas used as the carrier gas. The fluorine adsorbed to the buffer layer 102 is combined with oxygen vacancy and by-products (SiOH) in the buffer layer 102, so that trap sites between the buffer layer 102 and the active layer 114 are removed. In addition, the fluorine remaining in the chamber 120 stabilizes the bond of the metal-oxide in the active layer 114 formed on the buffer layer 102 after the plasma surface treatment process to improve the density of the thin film of the active layer 114 . Thus, the surface characteristics of the buffer layer 102 and the interface characteristics between the buffer layer 102 and the active layer 114 are stabilized.

On the other hand, fluorine remaining in the chamber 120 during the plasma surface treatment appears in the reaction gas used in the etching process. For example, fluorine, which is a reactive gas used in the etching process for forming the gate insulation pattern 112, is used in the plasma surface treatment. For this purpose, the fluorine used in the etching process of the gate insulation pattern 112 can be used in the plasma surface treatment process by using the chamber 120 used in the etching process of the gate insulation pattern 112 during the plasma surface treatment process. In addition, the surface of the buffer layer 102 may be surface-treated by containing fluorine in at least any one of He, H2, and SF6. In addition, the entire surface of the buffer layer 102 may be plasma-treated in the chamber 120 used for applying the buffer layer 102.

As shown in FIGS. 2 and 3B, the active layer 114 is formed on the plasma-treated buffer layer 102 (step S13).

Specifically, after the metal oxide semiconductor material is completely deposited on the buffer layer 102 subjected to the plasma surface treatment by a sputtering process, the metal oxide semiconductor material is patterned by the photolithography process and the etching process, thereby forming the active layer 114 .

The gate insulating pattern 112 and the gate electrode 106 are simultaneously formed on the buffer layer 102 on which the active layer 114 is formed (step S14), as shown in FIGS. 2 and 3C.

Specifically, a gate insulating material is formed on the buffer layer 102 on which the active layer 114 is formed by a CVD method, and a gate metal layer is formed thereon by a deposition method such as sputtering. As the gate insulating material, an inorganic insulating material such as SiOx, SiNx or the like is used. As the gate metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr or an alloy thereof may be used as a single layer, or may be used as a multi-layer structure by using them. Then, the gate insulating material and the gate metal layer are simultaneously patterned through the photolithography process and the etching process, so that the gate insulating pattern 112 and the gate electrode 106 of the same pattern are simultaneously formed.

At this time, the active layer 114, which is not overlapped with the gate electrode 106 during the dry etching of the gate insulating material, is exposed to the plasma, so that oxygen in the active layer 114, which is not overlapped with the gate electrode 106 by the plasma, Is removed. Accordingly, the active layer 114, which is not overlapped with the gate electrode 106, is made conductive and connected to the source and drain electrodes 108 and 110. The active layer 114 overlapped with the gate electrode 106 is not exposed to the plasma by the gate electrode 106 and the gate insulating pattern 112 and therefore maintains the semiconductor state by the oxygen in the active layer 114 And is formed as a channel region of the active layer 114.

The interlayer insulating film 116 having the first and second contact holes CH1 and CH2 is formed on the substrate 101 on which the gate electrode 106 is formed as shown in FIGS. 2 and 3 (step S15) .

Specifically, an interlayer insulating film 116 is formed on the substrate 101 on which the gate electrode 106 is formed by a method such as PECVD. Then, the interlayer insulating film 116 is patterned through the photolithography process and the etching process to form the first and second contact holes CH1 and CH2. The first and second contact holes CH1 and CH2 expose the active layer 114 through the interlayer insulating layer 116. [

The source electrode 108 and the drain electrode 110 are formed on the interlayer insulating film 116 (step S16), as shown in FIGS. 2 and 3E.

Specifically, a source / drain metal layer is formed on the interlayer insulating film 116 having the first and second contact holes CH1 and CH2 by an evaporation method such as sputtering. As the source / drain metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr or an alloy thereof may be used as a single layer, or may be used as a multi-layer structure by using them. Then, the source electrode 108 and the drain electrode 110 are formed on the interlayer insulating film 116 by patterning the source / drain metal layer through the photolithography process and the etching process.

At the interface between the active layer 114 and the buffer layer 102 formed by such a manufacturing method, nanoparticles of several nm in size are formed as shown in FIG. That is, in the comparative example in which the buffer layer 102 is not subjected to the plasma surface treatment, the upper surface of the buffer layer 102 is flat, while the embodiment of the present invention in which the buffer layer 102 is subjected to the plasma surface treatment, Nanoparticles of several nanometers in size are formed on the upper surface of the substrate. At the interface between the active layer 114 and the buffer layer 102 of the present invention, an element having a molecular weight of 134 is detected, which will be described with reference to Figs. 5, 6A, 6B and 7.

5, and # 7 are embodiments of the present invention in which the buffer layer 102 is subjected to a plasma surface treatment as shown in Table 1, and # 2, # 4, # 6 and # 102) are not subjected to the plasma surface treatment.

Deposition temperature (캜) Deposition pressure (Torr) He Plasma Treatment #One 230 One ○ #2 230 One × # 3 230 1.8 ○ #4 230 1.8 × # 5 250 One ○ # 6 250 One × # 7 250 1.8 ○ #8 250 1.8 ×

(O), silicon (Si), hydrogen (H), indium (In) and fluorine (F) are detected at the interface between the active layer 114 and the buffer layer 102 as shown in FIG. do. Particularly, in the embodiments (# 1, # 3, # 5, # 7) in which the buffer layer 102 is subjected to the plasma surface treatment, the fluorine element has a detection amount larger than that of the hydrogen element while the buffer layer 102 is not subjected to the plasma surface treatment In the comparative examples (# 2, # 4, # 6, # 8), the fluorine element has a smaller amount of detection than the hydrogen element. (# 2, # 4, # 6) in which the plasma surface treatment was not applied to the buffer layer 102 (Examples # 1, # 3, # 5 and # , # 8), the density of fluorine anions increases at the interface between the active layer 114 and the buffer layer 102 by about 10 times or more.

On the other hand, as shown in FIG. 6A, in the comparative example without the plasma treatment, only the by-product of the molecular weight 132 was detected at the interface between the buffer layer and the active layer, while the plasma surface treatment was performed as shown in FIGS. 6B and 7 In the example, by-products of molecular weight 132 are detected with an element of molecular weight molecular weight 134 sparging at the interface between buffer layer 102 and active layer 114. The element having a molecular weight of 134 was analyzed by Transmission Electron Microscopy (TEM), and it was judged that InF and an element having a molecular weight of 132 were Si ₃ O _{3 which} is a by-product.

Specifically, at the interface between the active layer 114 and the buffer layer 102, oxygen (O (molecular weight: about 16), silicon (Si: molecular weight: about 28) (Molecular weight: about 115) and fluorine (F: molecular weight: about 19) are detected. Using these elements, an element having a molecular weight of 134 is indium (In) having a molecular weight of 115; Is formed through an element of at least one of oxygen (O), hydrogen (H), and fluorine (F). Here, since the valence of indium (In) is univalent or trivalent, indium (In) and; It is possible to obtain a compound having crystallinity as represented by Chemical Formula (1) through at least one element of oxygen (O), hydrogen (H) and fluorine (F).

It can be seen that the element of molecular weight 134 detected at the interface between the buffer layer 102 of InF, InF3, InOH and In (OH) 3 described in Chemical Formula 1 and the active layer 114 is InF.

The fluorine ions detected at the interface between the active layer 114 and the buffer layer 102 are combined with the oxygen vacancy and the by-product SiOH in the buffer layer 102 to form the buffer layer 102 and the active layer 114, The reliability of the trap site is improved. The fluorine ions detected at the interface between the active layer 114 and the buffer layer 102 also stabilize the metal-oxide bond in the active layer 114 to improve the density of the thin film of the active layer 114. Thus, the surface characteristics of the buffer layer 102 and the interface characteristics between the buffer layer 102 and the active layer 114 are stabilized.

As a result, as shown in FIG. 8 and Table 2, the present invention in which the buffer layer 102 is subjected to the plasma surface treatment shifts the threshold voltage by +0.694 V from the initial value 103 hours later, whereas in the conventional method, The threshold voltage is shifted by + 1.557 V from the initial value. Accordingly, it is understood that the present invention improves the positive bias temperature stress (PBTS) characteristic because the variation of the threshold voltage of the thin film transistor is minimized.

Stress Vth (V) Vth (V)
Conventional
initial 1.843 - Stress_1hr 3.121 1.278 Stress_2hr 3.400 1.557


Invention


initial 0.019 - Stress_1.4hr -0.038 -0.057 Stress_4.1hr -0.008 -0.027 Stress_13.8hr 0.063 0.044 Stress_15.2hr 0.073 0.054 Stress_28.9hr 0.188 0.169 Stress_103hr 0.713 0.694

9, since the capacitance-voltage (CV) curve shifts to the left and the slope increases, the trap defective region (the trap-defect region) existing in the interface between the buffer layer 102 and the active layer 114 trap sites are reduced and reliability is improved.

The thin film transistor according to the present invention is applied to a display device such as a liquid crystal display device and an organic electroluminescent device, or as a switching device of a driving circuit such as a gate driver formed on a substrate.

The thin film transistor according to the present invention applied to the liquid crystal display device is connected to the liquid crystal element Clc to drive the liquid crystal element Clc as shown in FIG. The thin film transistor TFT is turned on by the gate-on voltage from the scan line SL so that the data signal of the data line DL is supplied to the pixel electrode of the liquid crystal element Clc, A voltage equal to the difference between the common voltage Vcom supplied to the common electrode facing the electrode and the data signal is applied and is turned off by the gate off voltage so that the voltage applied to the liquid crystal element Clc is maintained. The liquid crystal element Clc implements an image by controlling the light transmittance by driving the liquid crystal according to the applied voltage. Meanwhile, the thin film transistor substrate having the thin film transistor according to the present invention is formed through the manufacturing process shown in FIG. That is, the thin film transistor substrate is coated with an organic insulating material and an inorganic insulating material on the thin film transistor formed through the manufacturing process shown in FIG. 2 and then patterned to form a protective film having a pixel contact hole (Step S17) A transparent conductive film is deposited on the protective film and then patterned to form a pixel electrode (step S18).

A thin film transistor according to the present invention applied to an organic electroluminescent device is applied to a driving transistor Tr_D and a switching transistor Tr_Sw for driving the organic light emitting diode OLED as shown in FIG.

The switching transistor Tr_Sw operates so that the data signal supplied through the data line DL in response to the gate voltage supplied through the scan line SL is stored as a data voltage in the storage capacitor Cst.

The driving transistor Tr_D operates so that the driving current flows between the high voltage (VDD) supply line and the low voltage (VSS) supply line according to the data voltage stored in the storage capacitor Cst.

The organic light emitting diode OLED has a cathode connected to the driving transistor Tr_D and a cathode opposed to the anode with a light emitting layer interposed therebetween. The organic light emitting diode OLED is connected to the driving current formed by the driving transistor Tr_D And operates to emit light.

The foregoing description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed according to the following claims, and all the techniques within the scope of equivalents should be construed as being included in the scope of the present invention.

102: buffer layer 106: gate electrode
108: source electrode 110: drain electrode
114: active layer

Claims (14)

A buffer layer located on the substrate;
And a thin film transistor located on the buffer layer and having an active layer made of a metal oxide semiconductor,
And an element having a molecular weight of 134 is disposed at an interface between the active layer and the buffer layer. The method according to claim 1,
Wherein a by-product having a molecular weight of 132 is disposed at an interface between the active layer and the buffer layer together with the element having the molecular weight of 134. [ 3. The method according to claim 1 or 2,
And the element having the molecular weight of 134 is InF. The method of claim 3,
And the by-product of the molecular weight 132 is Si3O3. 5. The method of claim 4,
The buffer layer may have a single-layer structure of SiOx or a multi-layer structure of SiNx and SiOx sequentially stacked,
Wherein the active layer is made of at least one of IGZO, ITZO, and IAZO including IZO. The method according to any one of claims 1 to 3,
And an organic light emitting element connected to the thin film transistor. The method according to any one of claims 1 to 3,
And a liquid crystal element connected to the thin film transistor. Forming a buffer layer on the substrate;
And forming a thin film transistor having an active layer made of a metal oxide semiconductor on the buffer layer,
And an element having a molecular weight of 134 is disposed at an interface between the active layer and the buffer layer. 9. The method of claim 8,
The step of forming the thin film transistor
Plasma processing the upper surface of the buffer layer after forming the buffer layer;
And forming an active layer on the plasma-treated buffer layer. 10. The method of claim 9,
Wherein the plasma treatment uses at least one plasma treatment gas of SF ₆ , H ₂ , and He. 10. The method of claim 9,
Wherein the plasma treatment of the buffer layer is performed in a chamber containing fluorine in which the substrate is seated. 12. The method of claim 11,
The step of forming the thin film transistor
Forming a gate insulating pattern on the active layer;
Forming a gate electrode on the gate insulating pattern,
Wherein the fluorine is a reactive gas used in an etching process of the gate insulation pattern. 10. The method of claim 9,
The element having the molecular weight of 134 is InF,
The buffer layer may have a single-layer structure of SiOx or a multi-layer structure of SiNx and SiOx sequentially stacked,
Wherein the active layer is made of at least one of IGZO, ITZO, and IAZO including IZO. The method according to claim 9 or 13,
Wherein a byproduct having a molecular weight of 132 is disposed at an interface between the active layer and the buffer layer together with the element having the molecular weight of 134. [

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