KR20150028997A - A method for fabricating a thin film transistor - Google Patents

Abstract

A method of fabricating a bottom-gate top-contact metal oxide semiconductor thin film transistor, comprising: forming a gate electrode on a substrate; Providing a gate dielectric layer covering the gate electrode; Depositing a metal oxide semiconductor layer on the gate dielectric layer; Depositing a metal layer on the metal oxide semiconductor layer; Patterning the metal layer to form source and drain contacts, the patterning the metal layer including dry etching the metal layer; And thereafter patterning the metal oxide semiconductor layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a thin film transistor,

The present disclosure relates to a method for fabricating a metal oxide semiconductor thin film transistor, specifically, a method for fabricating a metal oxide semiconductor lower-gate upper-contact thin film transistor, and a thin film transistor obtained by such a method.

Metal oxide semiconductors are potentially applicable in thin film electronics such as large area displays and circuits because they can achieve good electrical properties at low processing temperatures. For example, a thin film transistor (TFT) using amorphous gallium-indium-zinc-oxide (a-GIZO) as an active layer has already been specified. Implemented, excellent mobility (μ) and excellent threshold voltage (V _TH ) regulation are important parameters in successfully displacing a conventional amorphous Si TFT backplane into an amorphous metal oxide semiconductor TFT backplane in a display.

In the method of fabricating the bottom-gate top-contact (BGTC) metal oxide semiconductor thin film transistor, an etch stop layer is often used to protect the metal oxide semiconductor layer from plasma defects during further processing. In this process, after providing a gate and gate dielectric layer on the substrate, a metal oxide semiconductor layer is deposited and patterned on the gate dielectric layer. Then, after the etch stop layer is deposited on the metal oxide semiconductor layer, the etch stop layer is patterned. A metal layer is then deposited and patterned by dry plasma etching to form the source and drain contacts. The etch stop layer protects the underlying metal oxide semiconductor layer from defects that may be generated by a metal etch process during patterning that defines the source and drain contacts.

In another process flow, an etch stop layer may not be used by using a wet etch process to pattern the metal layer on top of the metal oxide semiconductor layer. However, finding an etch that provides good etch selectivity between a metal layer and a metal oxide semiconductor layer is difficult and limits the combination of materials that can be used.

One aspect of the invention relates to a method of fabricating an excellent metal oxide semiconductor thin film transistor in which the patterning of the source and drain contacts is performed by dry etching on top of the metal oxide semiconductor layer, and an etch stop layer is not required.

One aspect of the invention provides a method of forming a lower-gate top-contact, comprising forming a gate electrode on a substrate, providing a gate dielectric layer covering the gate electrode, and depositing a layer of a metal oxide semiconductor on the gate dielectric layer. And a method of fabricating the metal oxide semiconductor thin film transistor. The method also includes depositing a metal layer or a metal layer stack on top of the metal oxide semiconductor layer, and patterning the metal layer or metal layer stack to form source and drain contacts of the thin film transistor, the step of patterning the metal layer or metal layer stack Etching the metal layer or the metal layer stack; And then, for example, patterning the metal oxide semiconductor layer. The method may further include additional processing steps such as depositing a passivation layer and / or an annealing step. The annealing step is preferably suitable for treating damage by the plasma process during fabrication of the device and / or for obtaining an excellent passivation.

The metal oxide semiconductor layer may be an amorphous IGZO (indium gallium zinc oxide) layer. However, the present disclosure is not limited to these, and other metal oxide semiconductor layers can be used, for example, InZnO, HfInZnO, SiInZnO, ZnO, CuO or SnO layer.

In the method according to an aspect of the invention, the step of patterning the metal oxide semiconductor layer is performed after patterning the metal layer or the metal layer stack on the metal oxide semiconductor layer, that is, after defining the source and drain contacts. During the dry etching of the metal, for example, the risk of damaging the metal oxide semiconductor layer in the channel region of the thin film transistor is reduced by patterning the metal oxide semiconductor layer before patterning the metal layer or the metal layer stack by dry (plasma) There is an advantage that it can be significantly reduced by performing the series of process steps above.

The method according to one aspect of the invention has the advantage that the number of masks required is reduced, the number of process steps is reduced, and the manufacturing cost is reduced since there is no need to provide an etch stop layer and perform patterning.

In a method according to an aspect of the invention, the transistor size, specifically the channel length, has the advantage that it can be reduced compared to the method using an etch stop layer. Although the size of the transistor depends on, for example, the substrate size and the lithography tool used, the channel length of the transistor fabricated by the method according to one aspect of the invention is on the order of about 2 microns to 5 microns, Lt; RTI ID = 0.0 > um < / RTI > to 20 um. In general, the channel length can be reduced by about three times as compared with a thin film transistor fabricated by an etch stop layer. Therefore, when a method according to one aspect of the invention is used in the manufacturing process of a display, a more compact pixel can be formed, and a display having an improved resolution can be manufactured.

Method according to one aspect of the invention, excellent field-effect mobility (e.g., about ² cm 2 / Vs to 100 cm ² / Vs), low I _OFF The advantage of enabling the fabrication of metal oxide semiconductor thin film transistors with excellent characteristics such as current (e.g., less than about 10 pA) and low sub-threshold slope (e.g., less than about 1 V / decade) have.

The method according to aspects of the invention has the advantage of being compatible with existing production lines used for mass production of amorphous silicon thin film transistors and circuits. Specifically, the fabrication steps used in accordance with aspects of the present invention can be performed in existing fabrication lines of amorphous silicon TFTs. This means that the metal oxide TFT can be produced in the production line of the conventional amorphous silicon TFT by the method of the embodiment of the present invention.

In a method according to one aspect of the invention, there is an advantage that can be used to fabricate an array of metal oxide semiconductor thin film transistors, for example, to select or drive pixels of a display.

Certain aspects of certain aspects and advantages are described above. Of these, all such objects or advantages are understood to be achieved in accordance with certain embodiments of the present disclosure. Thus, for example, those skilled in the art will recognize that, rather than necessarily achieving other objects or advantages as taught or suggested herein, one of ordinary skill in the art appreciates that it is implemented or performed in a manner that achieves or optimizes one advantage or group of teachings herein something to do. It is also understood that this summary is exemplary and is not intended to limit the scope of the present disclosure. The disclosure of the operating method and apparatus, together with its features and advantages, can be understood with reference to the detailed description together with the accompanying drawings.

Figure 1 schematically illustrates a process sequence in accordance with one embodiment of the present disclosure.
Figures 2 (a) -2 (e) illustrate a method according to one embodiment of the present disclosure.
Figure 3 shows the measured transition characteristics of a GIZO thin film transistor (DE Mo) in which source and drain contacts are deposited after GIZO is patterned and the etch stop layer is not used, patterned by dry etching, Drain contact of the GIZO thin film transistor (LO Mo) in which the drain contact is formed.
Figure 4 shows measured transitional characteristics of a GIZO thin film transistor fabricated according to an embodiment of the method of the present invention.
Figure 5 illustrates the transition characteristics of a GIZO thin film transistor measured at different locations of the array fabricated on a 6 inch substrate in accordance with an embodiment of the present invention.
Fig. 6 is a schematic view of three a-IGZO TFTs processed by standard BCE (IGZO etched S / D etch), BCE process (S / D etch before IGZO etch) and conventional lift- And the transition characteristics (V _GS -I _DS ).
Figure 7 shows a capacitance comparison of MIS (including a-IGZO) and MIM (no a-IGZO) in the region of 500 x 500 um ² showing a difference of less than 5%.
FIG. 8 is a _{graph showing the relationship} between (a) V _GS = + 12V and V _DS (W / L = 70/10 ㎛ / ㎛) with a function of the stress time at (V _GS - = + 12V, (b) V _GS = -12 V and V _DS = I _DS ), (c) V _TH shift of a-IGZO TFTs with stress time in both positive and negative directions.
Figure 9 shows (a) transition (V _GS -I _DS ) and (b) output (V _DS -I _DS ) characteristics for a driver TFT having W / L = 55/5 μm / (V _DS = 10 V) of 9 TFTs measured on the foil substrate.
In the different drawings, the same reference numbers refer to the same or similar elements.

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure and how it is carried out in a specific embodiment. However, the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, and techniques are not described in detail so as not to obscure the present disclosure. The present disclosure may be described in connection with specific embodiments with reference to specific drawings, but the present disclosure is not limited thereto. The drawings included and described are schematic and do not limit the scope of the present disclosure. In the drawings, it is noted that the size of some elements may be exaggerated and therefore not drawn to the correct scale for illustration.

Also, in the detailed description, "first, second, third," etc. are used to distinguish similar elements and do not necessarily describe the order of temporal order, spatial order, order, or any other method. It will be appreciated that such used terms may be interchanged under suitable circumstances and that the embodiments of the present disclosure described herein may operate in other orders than those described or described herein.

Also, in the detailed description, "upper", "lower", "upper", "lower" and the like are used for explanation and do not necessarily describe relative positions. It will be appreciated that such used terms may be interchanged under suitable circumstances, and that the embodiments of the present disclosure described herein operate in a different direction than those described or illustrated herein.

It should be noted that "comprising" is not to be construed as limiting the means listed thereafter, nor does exclude other elements or steps. It is not intended to exclude the presence or addition of one or more other features, symbols, steps, or components, or groups, which are to be interpreted as specifying the presence of stated features, symbols, steps, or components. Thus, the scope of "an apparatus comprising means A and B" is not limited to an apparatus consisting of only components A and B.

A particular embodiment includes a method of forming a lower-gate top-contact metal layer, including forming a gate electrode on a substrate, providing a gate dielectric layer covering the gate electrode, and depositing a metal oxide semiconductor layer on the gate dielectric layer. A method of fabricating an oxide semiconductor thin film transistor is provided. In one embodiment, the method further comprises depositing a metal layer or a metal layer stack on top of the metal oxide semiconductor layer; And patterning the metal layer to form source and drain contacts, the step of patterning the metal layer comprising a dry etching step of the metal layer; And then patterning the metal oxide semiconductor layer. The method may further include additional processing steps such as depositing a passivation layer (e.g., silicon oxide, silicon nitride and / or aluminum oxide) and / or annealing.

In the method according to one embodiment, a step of patterning the metal oxide semiconductor layer is performed after patterning the metal layer over the metal oxide semiconductor layer by dry etching, that is, after defining the source and drain contacts.

An example of a process flow for fabricating a metal oxide semiconductor thin film transistor according to one embodiment is schematically shown in Fig. 1 and is shown in Fig. After depositing a gate metal layer or metal stack, for example a Mo, Ti, Cr or Cu layer or Ti / Mo or Mo / Al / Mo stack of about 30 nm to 300 nm thickness on the electrically insulating substrate 10 Step 1), the gate metal layer or metal stack is patterned by photolithography or by wet etching or dry etching to form the gate electrode 11 (Step 2). Next, the gate dielectric layer 12 is deposited, for example, as a silicon oxide layer, a silicon nitride layer, or an aluminum oxide layer, or any other suitable dielectric layer, or a layer stack known to those skilled in the art (Step 3). The obtained structure is shown in Fig. 2 (a). The substrate can be a rigid substrate, a flexible substrate, or an extended substrate. When processed on a flexible or stretched substrate, the substrate may be provided on a (temporary) rigid carrier during the process.

Vias may be formed in the gate dielectric layer (not shown) and bonded to the gate. Next, a metal oxide semiconductor layer 13, for example, amorphous IGZO (indium gallium zinc oxide) is deposited on the gate dielectric layer 12 (FIG. 2 (b)) (step 4). However, the present disclosure is not limited to these, and other metal oxide semiconductor layers may be used. Preferred metal oxide semiconductors may be, for example, InZnO, HfInZnO, SiInZnO, ZnO, CuO or SnO. Depositing a metal oxide semiconductor layer, for example, DC or RF sputtering or evaporation. The thickness of the semiconductor layer 13 may be, for example, in the range of about 10 nm to 80 nm.

In the next step, a metal layer 14 or a metal stack is deposited on the metal oxide semiconductor layer 13 by evaporation or sputtering, for example (Fig. 2 (c)) (step 5). The metal layer or metal stack includes, for example, Mo, for example, the thickness may be about 50 nm to 300 nm. For example, a Mo / Al / Mo stack, a Mo / Au stack, a Mo / Ti stack, a Mo / Ti / Al / Mo stack or a Mo / ITO stack may be used but this disclosure is not limited thereto. To form the source contact 141 and the drain contact 142, the metal layer or metal stack is patterned by lithography and dry (plasma) etching, as shown in FIG. 2 (d) (step 6). The channel length may be, for example, from 2 m to 100 m.

After the metal layer is etched to form the source and drain contacts, the metal oxide semiconductor layer 13 is patterned by lithography and wet etching or dry etching to form the active layer 131 of the transistor (Fig. 2 (e)) Step 7).

Next, a passivation layer, such as a silicon oxide, silicon nitride, or aluminum oxide layer, having a thickness of, for example, about 50 nm to 300 nm is deposited by sputtering, ALD, or CVD (Step 8) and plasma etched or wet etched (Step 9). Finally, the structure is annealed, for example, in a nitrogen atmosphere or in air at about 50 캜 to about 175 캜 (step 10).

When manufacturing a thin film transistor circuit according to an embodiment, the capacitor formed in such a circuit includes a metal oxide semiconductor layer in addition to the dielectric layer between the metal layers.

The thin film transistor was fabricated in accordance with the process flow of FIGS. 1 and 2. On the electrically insulating substrate, a patterned Mo gate (thickness about 100 nm) was provided. Next, a SiN gate dielectric layer about 100 nm thick was deposited by CVD. In the following process, the a-IGZO layer (In: Ga: Zn = 1: 1: 1 atomic%, thickness: about 20 nm) was deposited by RF / DC sputtering in an O ₂ environment. A Mo source-drain contact (thickness of about 100 nm) was provided on top of the a-IGZO layer by DC sputtering and patterning using a dry etching process (SF ₆ + O ₂ plasma). In a later process, the active region was defined by photolithography and wet etching of the metal oxide layer (the a-IGZO layer was patterned). Finally, after the passivation layer was sputtered to about 100 nm SiO _x , the transistor was annealed at 150 ° C for about 1 hour in an N ₂ environment.

The measured transistor characteristics of a transistor having a channel length of about 10 mu m are shown in Fig. The transistors have high mobility (about 14.06 cm ² / Vs), low subthreshold slope (about 0.24 V / decade), low hysteresis, I _on / I _off of more than 10 ⁸ and V _TH .

For reference, a GIZO thin film transistor is fabricated without using an etch stop layer, but following metal oxide semiconductor patterning and etching, following metal oxide semiconductor patterning, instead of metal-oxide semiconductor patterning, was performed along the following different process flow. For reference, a transistor was fabricated in which the source and drain contacts were fabricated by a lift-off process (which is not suitable for scale expansion due to yield problems). The transistor characteristics of this reference transistor are shown in Fig. The transistor ('DE Mo' in FIG. 3) fabricated by metal oxide semiconductor etching without metal etch stop layer before metal deposition has clearly low I _ON / I _OFF rates, high subthreshold slope and large hysteresis. This may be due to the negative effect of the plasma used for source and drain etching on the GIZO layer, specifically the non-uniform distribution of the plasma on the wafer surface due to the distributed semiconductor channel region.

In the method according to the preferred embodiment, the metal oxide semiconductor layer is not yet patterned when the source and the drain are etched. Thus, the plasma is more uniformly distributed over the entire substrate resulting in a reduced local plasma non-uniformity and / or a reduced local plasma implantation effect on the metal oxide semiconductor layer.

The actuation display was fabricated to include an array of thin film GIZO transistors to select and drive the array of pixels. The GIZO transistor was about 5 탆 in channel length and was fabricated by the method according to one embodiment. The array of transistors was fabricated on a substrate of about 6 inches. Figure 5 shows the measured transient characteristics of five transistors from such an array, one transistor being located at the center of the substrate and the other four being located at the facing edges of the substrate. As a result, it exhibits excellent uniformity characteristics of the transistor on the substrate.

Another experimental result is described below. The test apparatus was implemented on a thermally grown SiO ₂ (120 nm) gate dielectric on top of a highly doped Si (general gate) substrate. A 15 nm thick a-IGZO (In: Ga: Zn = 1: 1: 1) film as an active layer was deposited by DC sputtering with 6% O ₂ under argon (Ar). Thickness and O ₂ / Ar ratio is optimized to achieve a desired TFT performance at lower processing temperatures. In addition, a 100 nm thick Mo source and drain (S / D) contact is formed by PVD and has a SF ₆ / O ₂ And was patterned by a dry etching chemical. After S / D formation, the active layer was patterned by a wet-etch process with an oxalic acid solution. On top of the active layer, a 100 nm SiO ₂ passivation layer was deposited by a reactive pulse DC PVD.

The electrical properties of industrial TFTs were measured using a parametric analyzer in an inert N ₂ environment.

By changing the order of a-IGZO patterning and S / D contact patterning in comparison with the prior art, the generation of isolated islands of a-IGZO in the method of the present invention is prevented and local accumulation of charge during plasma etching is suppressed . By varying the standard BCE process flow in this way, it represents a significant improvement in key TFT parameters, such as hysteresis, mobility, and overall subthreshold slope.

Three series of TFTs fabricated by conventional lift-off flow, standard BCE flow (S / D etch after semiconductor patterning), and BCE flow (S / D etch prior to semiconductor patterning) modified in accordance with aspects of the present invention IV features of the test are shown in Fig. All test devices were implemented on thermally grown SiO ₂ (120 nm) gate dielectrics on highly doped Si (general gate) substrates. The a-IGZO test apparatus fabricated with the modified BCE flow according to aspects of the present invention clearly showed a negligible degree of hysteresis in the transition curve between the forward gate voltage sweep and the back gate voltage sweep. Actual results are very similar to those obtained with a lift-off S / D based device. Table 1 provides the results of the main performance parameters for three different flows.

TFT  parameter lift- off  S / D of the device
a- IGZO  S / D after etching equipment
a- IGZO  Etching device before S / D
? _{E range}  (cm ² / (V.s) 12-15 5-12 12-15 SS ^-One
(V / decade ) 0.3-04 0.3-0.8 0.3-04 Hysteresis  (V) <0.5 &Lt; 1.0 <0.5

Transition characteristics of the standard BCE treated TFT showed a low mobility of 5-12 cm ² / (Vs), a degraded subthreshold swing of 0.60V / decade, and a negative threshold voltage of -0.5V. Also, the hysteresis in the transition curve increased significantly compared to the other two flows. The latter shows that many defects occur during the dry etching of the S / D metal layer on top of the small island of a-IGZO. This damage is due to local charge accumulation by plasma exposure during the dry etching process in the separated active area. Overall, it has been observed that the modified BCE flow leads to significant improvements in device characteristics.

It has been demonstrated whether the a-IGZO layer present under the metal line can potentially affect the parasitic capacitance of the signal line. This is particularly important for (TFT) displays and circuit applications. To demonstrate this effect, two capacitors corresponding to gate dielectrics were compared with and without a-IGZO. As shown in Fig. 7, only a change of only 5% of the total capacitance was measured. The influence of the bias stress on the electrical performance of the TFT was also investigated. The gate field corresponding to +/- 1.0 MV / cm in the positive and negative directions was applied in the dark room for a stress time of 10 ⁴ seconds at room temperature. For positive gate biases (V _DS = 12V and V _GS = 12V) corresponding to fully-on condiction, a threshold voltage shift of 0.9 V was observed. For negative biases (V _DS = 0 V and V _GS = -12 V), a threshold voltage shift of 1.0 V was observed. Figures 8 (a) and 8 (b) show the change in the transfer characteristics as a function of the bias stress time for the positive and negative gate biases. Figure 8 (c) provides a V _TH shift comparison as a function of stress time in both positive and negative directions.

Finally, the modified BCE process flow according to an embodiment of the present invention was integrated on a PEN foil with 200 nm ICP-CVD SiN as gate dielectric and 100 nm MoCr as gate metallization.

The substrate foil was implemented as a 25 占 퐉 thick thermally stabilized PEN foil from a commercial supplier and the substrate foil was laminated onto a 150 mm rigid glass carrier. Carriers serve as supports during the entire fabrication process of digital circuits and displays. In the first step, a 200 nm SiN barrier layer was deposited at 150 占 폚 by inductively coupled plasma chemical vapor deposition (ICP-CVD) on top of the PEN foil. The gate metal is formed by physical vapor deposition (PVD) of a 100 nm thick MoCr alloy layer, followed by a wet etch patterning procedure. Next, a 200 nm thick SiN gate dielectric layer was deposited at 150 DEG C by ICP-CVD. For low gate leakage current and high breakdown fields, there is a need for a TFT that is used as a mounting block in circuitry and display backplanes. It is difficult to achieve good dielectric properties by conventional CVD deposition at the low temperatures required for processing on PEN foils (less than 200 [deg.] C). Thus, the processing conditions of the SiN dielectric layer deposited by ICP-CVD at 150 占 폚 were optimized. A leakage current of 1.3 e ^-6 mA / cm ^{2 at 2} MV / cm and a breakdown field of ~ 8 MV / cm were obtained (dielectric constant ε = 7.1).

Next, a 15 nm thick a-IGZO (In: Ga: Zn = 1: 1: 1) film as an active layer was deposited by DC sputtering containing 6% O ₂ in argon. Thickness and O ₂ / Ar ratio is optimized to obtain a desired TFT performance at lower processing temperatures. In addition, a 100 nm thick Mo source and drain (S / D) contact is formed by PVD and SF ₆ / O ₂ And then patterned by a dry etching chemical. After S / D formation, the active layer was patterned by a wet etching procedure using an oxalic acid solution. On top of the active layer, a 100 nm SiO ₂ passivation layer was deposited by reactive pulse-DC PVD.

Transition and output characteristics of the obtained TFT (W / L = 55/5 占 퐉 / 占 퐉) are shown in Fig. The TFT shows a linear mobility (μ) of 12-15 cm ² / (Vs), a V _TH of-1.0V, an I _{ON / OFF} ratio of 10 ⁸ , and a subthreshold swing of 0.3V / decade. In Figure 9 (c), the diffused V _ON and I _ON of the nine measured TFTs appear throughout the 6 inch wafer containing the PEN foil. At V _D = 10 V and V _G = 20 V, the spread of V _ON and I _ON is less than 5%.

The above description describes specific embodiments of the present disclosure. It will be understood, however, that although the foregoing disclosure has been described in detail, the present disclosure may be embodied in various ways. Where a particular term is used to describe a particular feature or aspect of the disclosure, it is to be understood that the term is not to be construed as limiting the invention to include any particular features or aspects of the disclosure, Please note.

Although the foregoing description illustrates, describes, and describes the novel features of the invention as applied to various embodiments, various omissions, substitutions and alterations in the details and forms of the apparatus and process shown are within the scope of the present invention By a person skilled in the art.

Claims (11)

A method of fabricating a bottom-gate top-contact metal oxide semiconductor thin film transistor,
Forming a gate electrode on the substrate;
Providing a gate dielectric layer covering the gate electrode;
Depositing a metal oxide semiconductor layer on the gate dielectric layer;
Depositing a metal layer or a metal layer stack on the metal oxide semiconductor layer;
Patterning the metal layer or metal layer stack to form source and drain contacts, the patterning the metal layer or metal layer stack including dry etching of the metal layer or metal layer stack; And
Thereafter, patterning the metal oxide semiconductor layer;
/ RTI &gt;
The method according to claim 1,
Depositing a passivation layer, and performing an annealing process.
3. The method according to claim 1 or 2,
Wherein the metal oxide semiconductor layer comprises or consists of an amorphous IGZO (indium gallium zinc oxide) layer.
3. The method according to claim 1 or 2,
Wherein the metal oxide semiconductor layer comprises or consists of any one or any combination of InZnO, HfInZnO, SiInZnO, ZnO, CuO or SnO layers.
3. The method according to any one of the preceding claims,
Wherein the metal oxide semiconductor layer has a thickness of 10 nm to 80 nm.
3. The method according to any one of the preceding claims,
Wherein the metal layer comprises or consists of Mo or the metal layer stack comprises a Mo / Al / Mo stack, a Mo / Au stack, a Mo / Ti stack, a Mo / Ti / Al / Mo stack or a Mo / &Lt; / RTI &gt;
3. The method according to any one of the preceding claims,
Wherein the metal layer or the metal layer stack has a thickness of about 50 nm to 300 nm.
3. The method according to any one of the preceding claims,
Wherein patterning the metal oxide semiconductor layer is performed after patterning a metal layer or metal layer stack on top of the metal oxide semiconductor layer to define the source and drain contacts.
3. The method according to any one of the preceding claims,
Wherein the substrate comprises a polyethylene naphthalate foil.
3. The method according to any one of the preceding claims,
Further comprising forming a via in the gate dielectric layer to contact the gate.
Use of a method according to any one of the preceding claims for making a transistor with a channel length of the order of 2 to 5 micrometers.

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