WO2019109310A1 - Thin film transistor and manufacturing method thereof, array substrate, and display device - Google Patents

Thin film transistor and manufacturing method thereof, array substrate, and display device Download PDF

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Publication number
WO2019109310A1
WO2019109310A1 PCT/CN2017/115043 CN2017115043W WO2019109310A1 WO 2019109310 A1 WO2019109310 A1 WO 2019109310A1 CN 2017115043 W CN2017115043 W CN 2017115043W WO 2019109310 A1 WO2019109310 A1 WO 2019109310A1
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Prior art keywords
layer
insulating layer
gate
barrier pattern
forming
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PCT/CN2017/115043
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French (fr)
Chinese (zh)
Inventor
赵晓辉
李明亮
王征文
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深圳市柔宇科技有限公司
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Priority to PCT/CN2017/115043 priority Critical patent/WO2019109310A1/en
Publication of WO2019109310A1 publication Critical patent/WO2019109310A1/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Abstract

Provided are a thin film transistor and a manufacturing method thereof, an array substrate, and a display device. A thin film transistor comprises a gate electrode (41), an active layer (20) electrically insulated from the gate electrode, a source electrode, a drain electrode, and a gate insulation layer (31) provided between the gate electrode and the active layer (20). The source electrode and the drain electrode are respectively in contact with the active layer, and the gate insulation layer and the gate electrode are formed by means of the following steps: forming an active layer on the upper surface of a substrate (10); forming an insulation layer (30) and a metal layer (40) in turn on the upper surfaces of the active layer and the substrate; performing a first patterning process on the metal layer by means of a first block pattern (511) to form a gate electrode; and performing, in the presence of the first block pattern, a second patterning process on the insulation layer by means of a second block pattern (522) to form a gate insulation layer.

Description

Thin film transistor and preparation method thereof, array substrate and display device Technical field

The present invention relates to the field of display technologies, and in particular, to a thin film transistor and a method for fabricating the same, an array substrate, and a display device.

technical background

Thin film transistors (TFTs) are one of the types of field effect transistors. Thin film transistors play an important role in the performance of display devices. They are roughly fabricated by depositing various thin films on the substrate, such as semiconductor active layers and dielectrics. Layers and metal electrode layers, etc., but there are still various problems affecting the performance of the thin film transistor during the preparation process, thereby affecting the display effect or the service life of the display device.

Therefore, research on thin film transistors has yet to be deepened.

Summary of the invention

The present invention aims to solve at least one of the technical problems in the related art to some extent. To this end, an object of the present invention is to provide a method of fabricating a thin film transistor which is simple to prepare, protects the active layer and the gate from damage, or prevents electrical abnormality of the TFT.

The present invention was obtained by the inventors based on the following findings and findings:

In the current method of fabricating a thin film transistor, the following problems usually occur: 1. excessive etching causes electrical anomaly; 2. in forming a gate insulating layer, referring to FIG. 1A and FIG. 1B, the gate insulating layer 1 and the gate The difference in alignment accuracy between the two causes a shift between the two, resulting in partial gate 3 not being covered by the photoresist 4 to be exposed, and etched away, thereby causing TFT electrical anomaly, and FIG. 1A And in FIG. 1B, 5 is an active layer, 6 is a substrate; 3. In the process of forming a gate, the active layer is etched by the acid solution of the etched gate, resulting in lower productivity. In view of the above technical problems, a large number of studies by the inventors have found that in the process of preparing a thin film transistor, the metal layer is first patterned by the first barrier pattern to form a first barrier pattern on the upper surface of the gate after the gate is formed, after which The insulating layer is patterned by the second barrier pattern in the presence of the first barrier pattern to form a gate insulating layer. When the thin film transistor is prepared by the above method, the above problem can be well solved, and the electrical characteristics and the use performance of the thin film transistor are improved.

In view of this, in one aspect of the invention, the present invention provides a method of fabricating a thin film transistor. According to an embodiment of the present invention, the thin film transistor includes a gate, an active layer electrically insulated from the gate, a source and a drain, and is disposed between the gate and the active layer a gate insulating layer, the source and the drain are respectively in contact with the active layer, and the gate insulating layer and the gate are formed by forming the active layer on an upper surface of the substrate Forming an insulating layer and a metal layer sequentially on the active layer and the upper surface of the substrate; the gold is passed through the first barrier pattern The dying layer performs a first patterning process to form the gate electrode; in the presence of the first blocking pattern, the insulating layer is subjected to a second patterning process by the second blocking pattern to form the gate Insulation. Therefore, in the process of preparing the thin film transistor by the method, the gate insulating layer and the gate are accurately aligned, no offset occurs, and the protection gate is not damaged, so that the TFT is not electrically abnormal, and the method can also In the process of forming the gate, the active layer is damaged, so as to avoid the problem of low productivity. In addition, the method is simple and easy to operate, mature in process, and easy to industrialize.

According to an embodiment of the present invention, the gate insulating layer and the gate electrode are formed by forming a first barrier pattern on an upper surface of the metal layer, and removing the metal layer not covered by the first barrier pattern Forming the gate; forming a second barrier pattern on the exposed upper surface of the insulating layer while leaving the first barrier pattern, removing the insulating layer not covered by the second barrier pattern Forming the gate insulating layer, wherein a projection of the active layer on the substrate covers a projection of the insulating layer not covered by the second blocking pattern on a substrate.

According to an embodiment of the invention, the insulating layer and the metal layer are formed by chemical vapor deposition or physical vapor deposition.

According to an embodiment of the invention, the first barrier pattern is formed by: forming a first photoresist layer on an upper surface of the metal layer; sequentially exposing and developing the first photoresist layer Processing to obtain the first barrier pattern.

According to an embodiment of the present invention, removing the metal layer not covered by the first barrier pattern is performed by an etching method.

According to an embodiment of the present invention, the second barrier pattern is formed by forming a second photoresist layer on an upper surface of the exposed insulating layer; and sequentially exposing the second photoresist layer And developing treatment to obtain the second barrier pattern.

According to an embodiment of the present invention, removing the insulating layer not covered by the second barrier pattern is performed by an etching method.

In another aspect of the invention, the invention provides a thin film transistor. According to an embodiment of the invention, the thin film transistor is obtained by the method described above. Thereby, the thin film transistor has better electrical properties, good use performance, and long life.

In yet another aspect of the invention, the invention provides an array substrate. According to an embodiment of the present invention, the thin film transistor described above is included. Thereby, the use performance of the array substrate can be improved.

In still another aspect of the invention, the invention provides a display device. According to an embodiment of the invention, the array substrate described above is included. Therefore, the use performance is good and the market is competitive.

DRAWINGS

1A and 1B are views showing the structure of a thin film transistor in the prior art.

2 is a flow chart showing the preparation of a thin film transistor in one embodiment of the present invention.

Fig. 3 is a view showing the structure of a thin film transistor in another embodiment of the present invention.

Fig. 4A is a view showing the structure of a thin film transistor in still another embodiment of the present invention.

Fig. 4B is a view showing the structure of a thin film transistor in still another embodiment of the present invention.

Fig. 5 is a view showing the structure of a thin film transistor in still another embodiment of the present invention.

Fig. 6A is a view showing the structure of a thin film transistor in still another embodiment of the present invention.

Fig. 6B is a view showing the structure of a thin film transistor in still another embodiment of the present invention.

Fig. 7 is a view showing the structure of a thin film transistor in still another embodiment of the present invention.

Fig. 8 is a view showing the structure of a thin film transistor in still another embodiment of the present invention.

Fig. 9 is a view showing the structure of a thin film transistor in still another embodiment of the present invention.

Specific embodiment

Embodiments of the present invention are described in detail below. The embodiments described below are illustrative only and are not to be construed as limiting the invention. Where specific techniques or conditions are not indicated in the examples, they are carried out according to the techniques or conditions described in the literature in the art or in accordance with the product specifications. The reagents or instruments used are not indicated by the manufacturer, and are conventional products that can be obtained commercially.

In one aspect of the invention, the invention provides a method of making a thin film transistor. According to an embodiment of the invention, the thin film transistor includes a gate, an active layer electrically insulated from the gate, a source and a drain, and a gate insulating layer disposed between the gate and the active layer, the source And the drain are respectively in contact with the active layer. Referring to FIG. 2, the gate insulating layer and the gate are formed by the following steps:

S100: forming an active layer on the upper surface of the substrate.

According to the embodiment of the present invention, there is no limitation on the specific kind of the substrate, and those skilled in the art can flexibly select according to actual needs. In an embodiment of the invention, specific types of substrates include, but are not limited to, glass substrates, metal substrates, or polymer substrates. Thereby, the use performance is better and the selectivity is wide.

According to the embodiment of the present invention, the method of forming the active layer is not limited, and those skilled in the art can flexibly select according to actual conditions. In an embodiment of the invention, the method of forming the active layer includes, but is not limited to, chemical vapor deposition or physical vapor deposition. Thus, the method is simple and easy to operate, the process is mature, and it is easy to industrialize production. Specifically, an entire semiconductor layer may be formed on the upper surface of the substrate, and then the semiconductor layer is patterned by a patterning process such as photolithography to obtain an active layer.

There is also no limitation on the material forming the active layer according to an embodiment of the present invention, and the method is applicable to any material which can be used as an active layer in the art. In an embodiment of the invention, the material forming the active layer includes, but is not limited to, polysilicon, amorphous silicon, indium gallium zinc oxide, indium tin zinc oxide, or indium zinc tin oxide. As a result, the material sources are extensive and the performance is used. good.

S200: forming an insulating layer and a metal layer in sequence on the active layer and the upper surface of the substrate.

According to an embodiment of the present invention, referring to FIG. 3, an active layer 20 is formed on the upper surface 11 of the substrate 10, and then an insulating layer 30 and a metal layer 40 are sequentially formed on the active layer 20 and the upper surface of the substrate 10. According to the embodiment of the present invention, the method of forming the insulating layer and the metal layer is not limited, and those skilled in the art can flexibly select according to actual needs. In an embodiment of the invention, the insulating layer and the metal layer are formed by chemical vapor deposition or physical vapor deposition. Thus, the method is simple and easy to operate, the process is mature, and it is easy to industrialize production.

According to the embodiment of the present invention, the material for forming the insulating layer is also not limited. In the embodiment of the present invention, the material for forming the insulating layer includes, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, and organic insulating material. Materials such as polyimide, acrylic materials, etc.

According to the embodiment of the present invention, the material for forming the metal layer is also not limited, and those skilled in the art can flexibly select according to actual conditions. In embodiments of the invention, the material forming the metal layer includes, but is not limited to, ITO, silver, tungsten, titanium, nickel, or an alloy. Thereby, the conductivity is good, the use effect is good, and the material source is wide.

S300: performing a first patterning process on the metal layer 40 by using the first blocking pattern 511 to form a gate electrode 41. FIG. 5 is a schematic structural view.

According to the embodiment of the present invention, the material for forming the first barrier pattern has no limitation as long as it can serve as a barrier during the formation of the gate electrode, and the protected metal layer is not removed, and those skilled in the art can Flexible choice of demand. In an embodiment of the invention, the material forming the first barrier pattern includes, but is not limited to, a photoresist. Thereby, the formation of the first barrier pattern is facilitated, and the use effect is also good.

According to the embodiment of the present invention, the method for forming the first barrier pattern is not limited, and those skilled in the art can flexibly select according to the actual situation of the material of the first barrier pattern. In an embodiment of the present invention, when the material forming the first barrier pattern is a photoresist, referring to FIG. 4A and FIG. 4B, the first barrier pattern may be formed by the following steps:

Step 1: Form a first photoresist layer 51 on the upper surface of the metal layer 40. Referring to FIG. 4A, a schematic structural view is shown.

According to an embodiment of the present invention, the method of forming the first photoresist has no limitation, and those skilled in the art can flexibly select according to actual needs. In an embodiment of the invention, the method of forming the first photoresist may be a method such as coating.

Step 2: sequentially exposing and developing the first photoresist layer 51 to obtain a first barrier pattern 511, which is shown in FIG. 4B.

According to an embodiment of the present invention, the gate is formed by removing the metal layer 40 not covered by the first barrier pattern 511 by etching, after the first barrier pattern 511 is formed on the upper surface of the metal layer 40. A gate electrode 41 is formed, and a schematic structural view is shown in FIG. 5. Therefore, since the upper surface of the substrate is provided with an insulating layer, when etching the metal layer, the etching liquid for etching the metal layer does not damage the substrate, the active layer or other structures, so as to avoid electrical abnormality. Bad problems such as reduced production capacity.

S400: The second insulating layer 30 is subjected to a second patterning process by the second barrier pattern 522 to form the gate insulating layer 31 in the presence of the first barrier pattern 511. FIG. 7 and FIG.

According to the embodiment of the present invention, the material forming the second barrier pattern has no limitation as long as it can serve as a barrier during the formation of the gate insulating layer, and the covered insulating layer is not removed, and those skilled in the art can Flexible choice of actual needs. In an embodiment of the invention, the material forming the second barrier pattern includes, but is not limited to, a photoresist. Thereby, the formation of the second barrier pattern is facilitated, and the use effect is also good.

According to the embodiment of the present invention, the method for forming the second barrier pattern is not limited, and those skilled in the art can flexibly select according to the actual situation of the material of the second barrier pattern. In an embodiment of the present invention, when the material forming the second barrier pattern is a photoresist, referring to FIGS. 6A and 6B, the second barrier pattern may be formed by the following steps:

Step 1: Form a second photoresist layer 52 on the upper surface of the exposed insulating layer 30, which is referred to FIG. 6A.

According to an embodiment of the present invention, the method of forming the second photoresist has no limitation, and those skilled in the art can flexibly select according to actual needs. In an embodiment of the present invention, the method of forming the second photoresist may be a method such as coating.

Step 2: sequentially exposing and developing the second photoresist layer 52 to obtain a second barrier pattern 522. Referring to FIG. 6B, the projection of the active layer 20 on the substrate is not covered by the second barrier pattern. Projection of the insulating layer 30 covered by 522 on the substrate. Thereby, the formation of the gate insulating layer in the subsequent step is facilitated.

According to an embodiment of the present invention, the gate insulating layer is formed by forming a second barrier pattern 522 on the upper surface of the exposed insulating layer 30 while leaving the first barrier pattern 511, and removing the unetched by etching The insulating layer 30 covered by the second barrier pattern 522 is formed to form the gate insulating layer 31. Referring to FIG. 7 for a schematic structural view, the first blocking pattern 511 and the second blocking pattern 522 are removed. FIG. 8 is a schematic structural view. Thereby, the insulating layer is patterned in the presence of the first barrier pattern to form a gate insulating layer, which can prevent the alignment accuracy between the gate and the gate insulating layer from being different during the formation of the gate insulating layer. Resulting in an offset between the two, thereby affecting the electrical characteristics of the TFT, and further, the projection of the active layer 20 on the substrate covers the projection of the insulating layer 30 not covered by the second barrier pattern 522 on the substrate, ie, The insulating layer 30 is retained in the non-corresponding region of the active layer 20. During the etching process for forming the gate insulating layer, the etching solution can be prevented from damaging the substrate or other structures on the substrate, so as not to affect the array substrate. Electrical characteristics.

According to an embodiment of the present invention, the inventors have found that the thin film transistor is prepared by the above method, and the gate insulating layer and the gate are accurately aligned without offset, and the gate can be protected from damage, so as to prevent electrical abnormality of the TFT. Moreover, the method can also avoid the problem that the active layer is corroded by the acid solution of the etched gate during the process of forming the gate, so as to avoid the problem of low productivity, and the method is simple and easy to operate, and the process is mature and easy. Industrial production.

In accordance with an embodiment of the present invention, in order to improve the performance of the thin film transistor, the above method further includes the step of forming a barrier layer, and the barrier layer 60 is disposed on the upper surface 11 of the substrate 10, a schematic structural view of which is referred to FIG. Thereby, the use performance of the TFT can be improved, and in the TFT preparation process, since the insulating layer 30 is retained in the non-corresponding region of the active layer 20, the etching solution can be prevented during the etching process of forming the gate insulating layer. Damage to the barrier layer, so as not to affect the TFT Electrical characteristics or other undesirable unknown problems.

According to an embodiment of the present invention, the method of forming the barrier layer has no limitation, and those skilled in the art can flexibly select according to actual conditions. In embodiments of the invention, methods of forming a barrier layer include, but are not limited to, chemical vapor deposition, physical vapor deposition, or coating. Thus, the method is simple, the process is mature, and it is easy to industrialize production.

According to the embodiment of the present invention, the material forming the barrier layer is also not limited, and no limitation is imposed herein. In an embodiment of the invention, the material forming the barrier layer includes, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride or an organic insulating material.

Of course, those skilled in the art can understand that in addition to the above steps of forming a barrier layer, an active layer, a gate insulating layer and a gate, the method of forming a thin film transistor further includes a conventional necessary step of forming a source, a drain and an electrode. The method for forming the same is a conventional technical means in the art, and will not be further described herein.

In another aspect of the invention, the invention provides a thin film transistor. According to an embodiment of the invention, the thin film transistor is obtained by the method described above. Thereby, the thin film transistor has better electrical properties, good use performance, and long life.

In yet another aspect of the invention, the invention provides an array substrate. According to an embodiment of the present invention, the thin film transistor described above is included. Thereby, the use performance of the array substrate can be improved, and the array substrate has all the features and advantages of the thin film transistor described above, and will not be further described herein.

In accordance with embodiments of the present invention, in addition to the thin film transistors described above, the array substrate also includes other structures and components necessary for conventional array substrates, such as pixels, planar layers, other necessary circuit structures, and the like.

In still another aspect of the invention, the invention provides a display device. According to an embodiment of the invention, the array substrate described above is included. Therefore, the use performance is good and the market competitiveness is strong. The display device has all the features and advantages of the thin film transistor and the array substrate described above, and will not be further described herein.

According to an embodiment of the present invention, in addition to the array substrate described above, the display device further includes other structures and components necessary for the conventional display device. Taking the mobile phone as an example, the display device includes color in addition to the array substrate described above. Structures and components such as a film substrate, a touch screen, a camera module, a fingerprint module, and an audio processing module.

According to an embodiment of the present invention, the specific type of the display device is not limited, and may be any display device having a display function, such as a mobile phone, a computer, a television, or a wearable device having a display function.

Moreover, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining "first" and "second" may include one or more of the features either explicitly or implicitly. In the description of the present invention, the meaning of "a plurality" is two or more unless specifically and specifically defined otherwise.

In the present invention, the first feature "on" or "under" the second feature may be a direct contact of the first and second features, or the first and second features may be indirectly through an intermediate medium, unless otherwise explicitly stated and defined. contact. Moreover, the first feature The "above", "above" and "above" features of the second feature may be that the first feature is directly above or above the second feature, or merely that the first feature level is higher than the second feature. The first feature "below", "below" and "below" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely that the first feature level is less than the second feature.

In the description of the present specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means a specific feature described in connection with the embodiment or example. A structure, material or feature is included in at least one embodiment or example of the invention. In the present specification, the schematic representation of the above terms is not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, various embodiments or examples described in the specification, as well as features of various embodiments or examples, may be combined and combined.

Although the embodiments of the present invention have been shown and described, it is understood that the above-described embodiments are illustrative and are not to be construed as limiting the scope of the invention. The embodiments are subject to variations, modifications, substitutions and variations.

Claims (10)

  1. A method of fabricating a thin film transistor, comprising: a gate electrode, an active layer electrically insulated from the gate, a source and a drain, and a gate electrode and the a gate insulating layer between the source layers, the source and the drain are respectively in contact with the active layer, and the gate insulating layer and the gate are formed by the following steps:
    Forming the active layer on an upper surface of the substrate;
    Forming an insulating layer and a metal layer in sequence on the active layer and the upper surface of the substrate;
    Performing a first patterning process on the metal layer by a first blocking pattern to form the gate;
    The insulating layer is subjected to a second patterning treatment by the second barrier pattern in the presence of the first barrier pattern to form the gate insulating layer.
  2. The method of claim 1 wherein said gate insulating layer and said gate are formed by the following steps:
    Forming a first blocking pattern on the upper surface of the metal layer, removing the metal layer not covered by the first blocking pattern to form the gate;
    Forming a second barrier pattern on the exposed upper surface of the insulating layer while leaving the first barrier pattern, removing the insulating layer not covered by the second barrier pattern to form the gate insulating layer ,
    Wherein the projection of the active layer on the substrate covers the projection of the insulating layer not covered by the second blocking pattern on the substrate.
  3. The method of claim 1 wherein said insulating layer and said metal layer are formed by chemical vapor deposition or physical vapor deposition.
  4. The method of claim 2 wherein said first barrier pattern is formed by the following steps:
    Forming a first photoresist layer on an upper surface of the metal layer;
    The first photoresist layer is sequentially subjected to exposure and development processing to obtain the first barrier pattern.
  5. The method according to claim 2, wherein removing the metal layer not covered by the first barrier pattern is performed by an etching method.
  6. The method of claim 2 wherein said second barrier pattern is formed by the following steps:
    Forming a second photoresist layer on the exposed upper surface of the insulating layer;
    The second photoresist layer is sequentially subjected to exposure and development processing to obtain the second barrier pattern.
  7. The method according to claim 2, wherein the removing the insulating layer not covered by the second barrier pattern is performed by an etching method.
  8. A thin film transistor obtained by the method of any one of claims 1-7 of.
  9. An array substrate comprising the thin film transistor of claim 8.
  10. A display device comprising the array substrate of claim 9.
PCT/CN2017/115043 2017-12-07 2017-12-07 Thin film transistor and manufacturing method thereof, array substrate, and display device WO2019109310A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102763202A (en) * 2010-02-19 2012-10-31 株式会社半导体能源研究所 Semiconductor device and method for manufacturing the same
CN103137495A (en) * 2011-11-30 2013-06-05 株式会社半导体能源研究所 Method for manufacturing semiconductor device
CN105977306A (en) * 2016-06-21 2016-09-28 北京大学深圳研究生院 Self-aligned thin-film transistor and preparation method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102763202A (en) * 2010-02-19 2012-10-31 株式会社半导体能源研究所 Semiconductor device and method for manufacturing the same
CN103137495A (en) * 2011-11-30 2013-06-05 株式会社半导体能源研究所 Method for manufacturing semiconductor device
CN105977306A (en) * 2016-06-21 2016-09-28 北京大学深圳研究生院 Self-aligned thin-film transistor and preparation method thereof

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