CN111446295A - Thin film transistor, array substrate and display panel - Google Patents
Thin film transistor, array substrate and display panel Download PDFInfo
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- CN111446295A CN111446295A CN202010267456.XA CN202010267456A CN111446295A CN 111446295 A CN111446295 A CN 111446295A CN 202010267456 A CN202010267456 A CN 202010267456A CN 111446295 A CN111446295 A CN 111446295A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
Abstract
The application discloses thin film transistor includes: the metal layer is arranged on a substrate and comprises a first metal area and a second metal area which are mutually disconnected; the buffer layer is arranged on the metal layer and covers the metal layer and the substrate; the active layer is arranged on the buffer layer and comprises a channel region, a source contact region and a drain contact region, wherein the source contact region and the drain contact region are arranged on two sides of the channel region; a gate insulating layer disposed on the active layer and covering the channel region; the grid electrode is arranged on the grid electrode insulating layer and corresponds to the channel region of the active layer; the source contact area is electrically connected with the first metal area, and the drain contact area is electrically connected with the second metal area.
Description
Technical Field
The application relates to the technical field of display, in particular to a thin film transistor, an array substrate and a display panel.
Background
In the prior art, since there is no overlapping area between the gate and the source of the array substrate with the top-gate self-aligned structure, the array substrate (TFT) with the top-gate self-aligned structure can reduce the parasitic capacitance to a large extent, reduce the RC circuit delay, and reflect to the pixel circuit, i.e. have a higher switching speed, thereby realizing a higher resolution display, and is increasingly applied to displays such as AMO L ED/Micro L ED/Min L ED.
The array substrate includes a thin film transistor, a general structure of the thin film transistor is shown in fig. 1 and fig. 2, as shown in fig. 1, the thin film transistor includes a gate 101, a source 102 and a drain 103, the source 102 and the drain 103 are located in the same layer, the source 102 and the drain 103 are connected through an active layer 104, the gate 101, the source 102 and the drain 103 are located in different layers, and a gate insulating layer 105 is disposed between the gate 101 and the active layer 104, and the thin film transistor further includes a buffer layer 200, a dielectric layer 300 and a passivation layer 400 disposed on a substrate 100; as shown in fig. 2, a thin film transistor is proposed, which is different from that in fig. 1, in that the thin film transistor further includes a light shielding layer 106, the light shielding layer 106 is located below the active layer 104, an orthographic projection of the light shielding layer 106 on the substrate 100 covers an orthographic projection of the active layer 104 on the substrate 100, the light shielding layer 106 serves as a metal layer, and at the same time, the light shielding layer 106 serves as a light blocking function for the thin film transistor; the light-shielding layer 106 is connected to the source electrode 102, so as to prevent induced charges generated by the light-shielding layer 106 from affecting the TFT characteristics, for example, prevent the threshold voltage of the TFT structure from continuously changing during operation.
However, the conventional top gate self-aligned type array substrate has disadvantages in that: the structure is complex, the manufacturing process is more, the number of layers of the metal layer and the insulating layer is increased, the cost is increased, and the production period is prolonged; and the light shielding layer only has the function of shielding light for the driving TFT, and the light shielding layer is not used in other parts, so that the utilization rate of preparing the light shielding layer is low.
Therefore, it is desirable to provide a new thin film transistor, an array substrate and a display panel.
Disclosure of Invention
The embodiment of the application provides a thin film transistor, an array substrate and a display panel, through setting up the metal level to the first metal area and the second metal area of mutual disconnection, the active layer includes a channel region and set up in a source contact area and a drain contact area of channel region both sides make the first metal area of metal level with the active layer source contact area electric connection is regarded as simultaneously thin film transistor's source electrode, and makes the second metal area of metal level with the drain contact area electric connection of active layer is regarded as simultaneously thin film transistor's drain electrode. The thin film transistor is simple in structure and few in manufacturing process, and the purposes of reducing cost and production period are achieved by reducing a metal layer and an insulating layer.
An embodiment of the present application provides a thin film transistor, including: the metal layer is arranged on a substrate and comprises a first metal area and a second metal area which are mutually disconnected; the buffer layer is arranged on the metal layer and covers the metal layer and the substrate; the active layer is arranged on the buffer layer and comprises a channel region, a source electrode contact region and a drain electrode contact region, wherein the source electrode contact region and the drain electrode contact region are arranged on two sides of the channel region; the grid electrode insulating layer is arranged on the active layer and covers the channel region; the grid electrode is arranged on the grid electrode insulating layer and corresponds to the channel region of the active layer; the source contact region is electrically connected with the first metal region, and the drain contact region is electrically connected with the second metal region.
In some embodiments, the thin film transistor further includes a dielectric layer disposed on the gate electrode and covering the gate electrode, the gate insulating layer, the source contact region, the drain contact region, and the buffer layer.
In some embodiments, the buffer layer includes a first via exposing a portion of the first metal region and a second via exposing a portion of the second metal region; the source contact region of the active layer extends towards the first metal region and contacts the first metal region through the first via; the drain contact region of the active layer extends toward the second metal region and contacts the second metal region through the second via.
In some embodiments, an orthographic projection of the source contact region of the active layer on the substrate falls within an orthographic projection of the first metal region of the metal layer on the substrate, and an orthographic projection of the drain contact region of the active layer on the substrate falls within an orthographic projection of the second metal region of the metal layer on the substrate.
In some embodiments, an orthographic projection of the channel region of the active layer on the substrate falls within an orthographic projection of the first metal region of the metal layer on the substrate, and a coincidence ratio of the orthographic projection of the channel region of the active layer on the substrate and an orthographic projection of the second metal region of the metal layer on the substrate is 0.
In some embodiments, a coincidence degree of an orthographic projection of the channel region of the active layer on the substrate and an orthographic projection of the first metal region of the metal layer on the substrate is 0, and a coincidence degree of an orthographic projection of the channel region of the active layer on the substrate and an orthographic projection of the second metal region of the metal layer on the substrate is 0.
In some embodiments, the material of the active layer is a metal oxide semiconductor, and the material of the metal oxide semiconductor is selected from one of indium gallium zinc oxide, indium zinc tin oxide and indium gallium zinc tin oxide.
In some embodiments, the source contact region of the active layer is conductively formed, and the drain contact region of the active layer is conductively formed.
The present application further provides an array substrate, which includes a substrate and a plurality of thin film transistors arranged on the substrate in an array manner.
The present application also provides a display panel including the thin film transistor or the array substrate as described above.
The thin film transistor, the array substrate and the display panel provided by the embodiment of the application, the thin film transistor comprises a buffer layer, a metal layer, an active layer, a gate insulating layer, a gate and a dielectric layer which are sequentially stacked on a substrate, wherein the metal layer includes a first metal region and a second metal region disconnected from each other, and, the active layer comprises a channel region, a source contact region and a drain contact region arranged at two sides of the channel region, the source contact region is electrically connected with the first metal region, the drain contact region is electrically connected with the second metal region, so that the source contact region of the active layer of the present application and the first metal region simultaneously serve as the source of the thin film transistor, the drain contact region of the active layer and the second metal region simultaneously serve as the drain of the thin film transistor; in addition, the metal layer can selectively block light for a channel region of the thin film transistor, so that the metal layer is simultaneously equivalent to a light shielding layer. Therefore, the thin film transistor has a simple structure and fewer manufacturing processes, and achieves the purposes of reducing the cost and the production period by reducing one metal layer and one insulating layer.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the prior art.
Fig. 2 is a schematic structural diagram of a thin film transistor according to another embodiment of the prior art.
Fig. 3 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of a thin film transistor according to another embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure. The embodiment of the application provides a thin film transistor, the thin film transistor includes a metal layer 2 arranged on a substrate 1, a buffer layer 3 arranged on the metal layer 2 and covering the metal layer 2 and the substrate 1, an active layer 4 arranged on the buffer layer 3, a gate insulating layer 5 arranged on the active layer 4, a gate electrode 6 arranged on the gate insulating layer 5, and a dielectric layer 7 arranged on the gate electrode 6 and covering the gate electrode 6, the gate insulating layer 5 and the active layer 4.
As shown in fig. 3, the metal layer 2 includes a first metal region 21 and a second metal region 22 that are disconnected from each other, and the first metal region 21 and the second metal region 22 are disposed in the same layer, that is, the thickness of the first metal region 21 in the direction perpendicular to the substrate 1 is equal to the thickness of the second metal region 22 in the direction perpendicular to the substrate 1. In the present embodiment, the material of the first metal region 21 and the second metal region 22 of the metal layer 2 is selected from an alloy including one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), which is not illustrated herein.
As shown in fig. 3, the active layer 4 includes a channel region 41, a source contact region 42 and a drain contact region 43, wherein the channel region 41 corresponds to the gate 6 and the gate insulating layer 5, the gate 6 and the gate insulating layer 5 define the channel region 41 opposite to the gate 6 and the source contact region 42 and the drain contact region 43 respectively disposed at two sides of the channel region 41 on the active layer 4, and the gate insulating layer 5 covers the channel region 41. In the present embodiment, the material of the active layer 4 is a metal oxide semiconductor; and the material of the metal oxide semiconductor is selected from one of indium gallium zinc oxide, indium zinc tin oxide and indium gallium zinc tin oxide.
In the present embodiment, the source contact region 42 is electrically connected to the first metal region 21, and the drain contact region 43 is electrically connected to the second metal region 22.
As shown in fig. 3, the buffer layer 3 includes a first via 31 exposing a portion of the first metal region 21 and a second via 32 exposing a portion of the second metal region 22; wherein, one end of the first via hole 31 extends to the surface of the active layer 4, the other end of the first via hole 31 extends to the surface of the first metal region 21, one end of the second via hole 32 extends to the surface of the active layer 4, and the other end of the second via hole 32 extends to the surface of the second metal region 22, that is, the first via hole 31 and the second via hole 32 vertically penetrate through the buffer layer 3 along the thickness direction of the buffer layer 3, respectively.
Continuing to fig. 3, the source contact region 42 of the active layer 4 extends toward the first metal region 21 and contacts the first metal region 21 through the first via 31, and the source contact region 42 is filled inside the first via 31, and the source contact region 42 is in contact connection with the first metal region 21; the drain contact region 43 of the active layer 4 extends toward the second metal region 22 and contacts the second metal region 22 through the second via hole 32, the drain contact region 43 is filled in the second via hole 32, and the drain contact region 43 is in contact connection with the second metal region 22.
In the embodiment of the present invention, in order to realize the electrical connection between the source contact region 42 and the first metal region 21, and in order to realize the electrical connection between the drain contact region 43 and the second metal region 22, the active layer 4 is formed by using the conventional preparation and using the self-aligned process, specifically, the source contact region 42 and the drain contact region 43 of the active layer 4 are subjected to deep layer conductor processing by using the self-aligned process, so that the source contact region 42 is made conductive, and the drain contact region 43 is made conductive.
It should be noted that the formation process of the active layer 4 described in this application includes two main steps:
firstly, forming the active layer 4 in a first state by adopting a direct current sputtering deposition mode; the material of the active layer 4 in the first state is a metal oxide semiconductor material, and the material of the metal oxide semiconductor is selected from one of indium gallium zinc oxide, indium zinc tin oxide and indium gallium zinc tin oxide.
Then, the active layer 4 in the first state is subjected to deep conductor processing by using a self-aligned process, so as to form the active layer 4 in the final state of the embodiment of the present application, including the source contact region 42 and the drain contact region 43 which are both conductor and the channel region 41 which still has semiconductor properties. That is, the source contact region 42 is made conductive and the drain contact region 43 is made conductive by the self-aligned process, and the source contact region 42 and the drain contact region 43 are made conductive not only on the surface but also on the bottom of the source contact region 42 and the drain contact region 43; and, due to the coverage protection effect of the gate insulating layer 5 and the gate electrode 6 on the channel region 41 of the active layer 4, the channel region 41 of the active layer 4 is not conducted, i.e. the channel region 41 still has semiconductor characteristics.
In this embodiment, since the source contact region 42 and the drain contact region 43 of the active layer 4 are both conductive regions, the first metal region 21 is electrically connected to the source contact region 42, and the second metal region 22 is electrically connected to the drain contact region 43, which is beneficial to realizing the conductive property of the thin film transistor. And the source contact region 42 of the active layer 4 is connected with the first metal region 21 of the metal layer 2 and serves as a source of the thin film transistor in common; the drain contact region 43 of the active layer 4 is connected to the second metal region 22 of the metal layer 2 and collectively serves as a drain of the thin film transistor.
In the conventional embodiment, the metal layer 2 can completely cover the active layer 4, that is, an orthographic projection of the metal layer 2 on the substrate 1 covers an orthographic projection of the active layer 4 on the substrate 1, in other words, an area of the orthographic projection of the metal layer 2 on the substrate 1 is larger than an area of the active layer 4.
Referring to fig. 3, in some embodiments, the source contact region 42 and the drain contact region 43 are symmetrically disposed about the channel region 41, the first via 31 and the second via 32 are identically shaped and sized, and the first via 31 and the second via 32 are symmetrically disposed about the gate 6. In the present embodiment, the first metal region 21 and the second metal region 22 are configured to have the same shape and size and are symmetrically configured with respect to the channel region 41.
In the present embodiment, an orthographic projection of the source contact region 42 of the active layer 2 on the substrate 1 falls within an orthographic projection of the first metal region 21 of the metal layer 2 on the substrate 1, and an orthographic projection of the drain contact region 43 of the active layer 2 on the substrate 1 falls within an orthographic projection of the second metal region 22 of the metal layer 2 on the substrate 1; and, in this embodiment, the coincidence degree of the orthographic projection of the channel region 41 of the active layer 4 on the substrate 1 and the orthographic projection of the first metal region 21 of the metal layer 2 on the substrate 1 is 0, and the coincidence degree of the orthographic projection of the channel region 41 of the active layer 2 on the substrate 1 and the orthographic projection of the second metal region 22 of the metal layer 2 on the substrate 1 is 0, that is, neither the first metal region 21 nor the second metal region 22 of the metal layer 2 shields the channel region 41.
As shown in fig. 3, in the present embodiment, since the first metal region 21 of the metal layer 2 is electrically connected to the source contact region 42, and the second metal region 22 is electrically connected to the drain contact region 43, the induced charges generated by the metal layer 2 can be prevented from affecting the characteristics of the thin film transistor, for example, the threshold voltage of the thin film transistor is prevented from changing continuously during operation. Therefore, in this embodiment, even if neither the first metal region 21 nor the second metal region 22 of the metal layer 2 shields the channel region 41, the normal operation state of the thin film transistor can be maintained.
Referring to fig. 4, in other embodiments of the present disclosure, in order to further improve the characteristics of the thin film transistor, at least one of the first metal region 21 and the second metal region 22 of the metal layer 2 covers the channel region 41 of the active layer 4, except that the thin film transistor is used as a driver, the metal layer 2 can be used as a light shielding layer and block light from the channel region of the thin film transistor, so as to improve the characteristics of the thin film transistor.
As shown in fig. 4, for example, in an embodiment, the difference from the embodiment shown in fig. 3 is that an orthographic projection of the channel region 41 of the active layer 4 on the substrate 1 falls within an orthographic projection of the first metal region 21 of the metal layer 2 on the substrate 1, and an overlap ratio of the orthographic projection of the channel region 41 of the active layer 4 on the substrate 1 and an orthographic projection of the second metal region 22 of the metal layer 2 on the substrate 1 is 0. That is, the first metal region 21 shields the channel region 41 of the active layer 4 from light, and the second metal region 22 does not shield the channel region 41 from light; the first metal region 21 can be used for preventing the active layer 4 from being irradiated by light to cause negative drift of the threshold voltage of the thin film transistor, so that the working stability of the thin film transistor is improved.
In other embodiments, an orthographic projection of the channel region 41 of the active layer 4 on the substrate 1 may also fall within an orthographic projection of the second metal region 22 on the substrate 1, and the channel region 41 of the active layer 4 is shielded from light by the second metal region 22. Meanwhile, the first metal region 21 is electrically connected to the source contact region 42, and the second metal region 22 is electrically connected to the drain contact region 43, which is beneficial to improving the conductive property of the thin film transistor.
In some other embodiments, in order to improve the characteristics of the thin film transistor, in order to enable the metal layer 2 to shield the channel region 41 of the active layer 4 from light, the first metal region 21 and the second metal region 22 of the metal layer 2 may be disposed at different layers, and an orthographic projection of the channel region 41 of the active layer 4 on the substrate 1 may fall within a sum region of an orthographic projection region of the first metal region 21 on the substrate 1 and an orthographic projection of the second metal region 22 on the substrate 1, and the first metal region 21 and the second metal region 22 cooperate to shield the channel region 41 of the active layer 4 from light. It should be noted that the first metal region 21 and the second metal region 22 are disposed in different layers, which increases the complexity of the process flow for manufacturing the thin film transistor, and the present embodiment proposes an alternative technical solution or a technical teaching for providing the related technical solution, and the preferable degree in the present embodiment is not described herein.
In the present embodiment, as shown in fig. 3 and 4, the substrate 1 is a glass substrate, but is not limited thereto, and the substrate 1 may also be a PI substrate or other types of substrates.
In this embodiment, the buffer layer 3 may be a single layer, the buffer layer 3 may also be a composite film, the material of the buffer layer 3 is preferably silicon oxide (SiOx) or silicon nitride (SiNx), and the composite film of the buffer layer 3 may be a composite layer formed by alternately stacking silicon oxide and silicon nitride. The thickness of the buffer layer 3 is sufficient to cover the metal layer 2 and the thickness of the buffer layer 3 is greater than the thickness of the metal layer 2, and the thickness of the buffer layer 3 is not particularly limited. And, in this embodiment, the buffer layer 3 is deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD), and the first via hole 31 and the second via hole 32 are formed by exposure patterning and etching.
Referring to fig. 3 and 4, the Dielectric layer 7(Inter L a layer Dielectric, I L D) is disposed on the gate electrode 6, and the Dielectric layer 7 covers the gate electrode 6, the gate insulating layer 5, the source contact region 42 of the active layer 4, the drain contact region 43 of the active layer 4, and the buffer layer 3, the Dielectric layer 7 prevents water-oxygen breakdown of the gate electrode 6, the source contact region 42 of the active layer 4, and the drain contact region 43 of the active layer 4, the first metal region 21, and the second metal region 22, in this embodiment, the Dielectric layer 7 is formed by chemical vapor deposition (PECVD), and the materials of the Dielectric layer 7 and the gate insulating layer 5 are silicon oxide (SiO).
This application thin film transistor compares with conventional structure, metal level 2 is one thin film transistor is in the light, metal level 2 both is equivalent to one deck light shield layer, metal level 2 does simultaneously again thin film transistor's source drain layer specifically does first metal area 21 regards as channel area 41's light shield layer, first metal area 21 with source contact area 42 is connected and is regarded as simultaneously thin film transistor's source electrode, second metal area 22 with active layer 4 the drain contact area is connected and is regarded as simultaneously thin film transistor's drain electrode, just first metal area 21 with second metal area 22 sets up with the layer.
The application also provides an array substrate, which comprises the substrate 1 and a plurality of thin film transistors arranged on the substrate 1 in an array manner. In this embodiment, the array substrate is a self-aligned top gate array substrate.
In addition, the present application also provides a display panel including the thin film transistor as described above; alternatively, the display panel comprises the self-aligned top gate array substrate as described above.
In the present application, as shown in fig. 3 and 4, the thin film transistor includes a two-metal layer structure and a three-insulation layer structure, the two-metal layer structure includes the gate 6, the first metal region 21 and the second metal region 22 disposed on the same layer, the three-insulation layer structure includes the buffer layer 3, the gate insulation layer 5 and the dielectric layer 7, and compared to the thin film transistor illustrated in fig. 2 that includes the three-metal layer structure and the four-insulation layer structure, the three-metal layer structure includes the same layer where the light shielding layer 106, the source electrode 102 and the drain electrode 103 are located, and the layer where the gate electrode 101 is located, and the four-insulation layer structure includes the buffer layer 200, the gate insulation layer 105, the dielectric layer 300 and the passivation layer 400, which is equivalent to the present application that one metal layer and one insulation layer are reduced. The thin film transistor is simple in structure and less in manufacturing process, and the purposes of reducing cost and production period are achieved by reducing a metal layer and an insulating layer.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The thin film transistor, the array substrate and the display panel provided by the embodiments of the present application are described in detail above, and specific examples are applied herein to explain the principles and embodiments of the present application, and the description of the embodiments above is only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A thin film transistor, comprising:
the metal layer is arranged on a substrate and comprises a first metal area and a second metal area which are mutually disconnected;
the buffer layer is arranged on the metal layer and covers the metal layer and the substrate;
the active layer is arranged on the buffer layer and comprises a channel region, a source electrode contact region and a drain electrode contact region, wherein the source electrode contact region and the drain electrode contact region are arranged on two sides of the channel region;
the grid electrode insulating layer is arranged on the active layer and covers the channel region; and the number of the first and second groups,
a gate electrode disposed on the gate insulating layer and corresponding to the channel region of the active layer;
the source contact region is electrically connected with the first metal region, and the drain contact region is electrically connected with the second metal region.
2. The thin film transistor of claim 1, further comprising a dielectric layer disposed on the gate and covering the gate, the gate insulating layer, the source contact region, the drain contact region, and the buffer layer.
3. The thin film transistor of claim 1, wherein the buffer layer includes a first via exposing a portion of the first metal region and a second via exposing a portion of the second metal region;
the source contact region of the active layer extends towards the first metal region and contacts the first metal region through the first via; the drain contact region of the active layer extends toward the second metal region and contacts the second metal region through the second via.
4. The thin film transistor of claim 3, wherein an orthographic projection of the source contact region of the active layer on the substrate falls within an orthographic projection of the first metal region of the metal layer on the substrate, and wherein an orthographic projection of the drain contact region of the active layer on the substrate falls within an orthographic projection of the second metal region of the metal layer on the substrate.
5. The thin film transistor according to claim 4, wherein an orthographic projection of the channel region of the active layer on the substrate falls within an orthographic projection of the first metal region of the metal layer on the substrate, and a coincidence ratio of the orthographic projection of the channel region of the active layer on the substrate and an orthographic projection of the second metal region of the metal layer on the substrate is 0.
6. The thin film transistor according to claim 4, wherein a coincidence ratio of an orthographic projection of the channel region of the active layer on the substrate and an orthographic projection of the first metal region of the metal layer on the substrate is 0, and a coincidence ratio of an orthographic projection of the channel region of the active layer on the substrate and an orthographic projection of the second metal region of the metal layer on the substrate is 0.
7. The thin film transistor according to claim 1, wherein a material of the active layer is a metal oxide semiconductor, and the material of the metal oxide semiconductor is one selected from indium gallium zinc oxide, indium zinc tin oxide, and indium gallium zinc tin oxide.
8. The thin film transistor according to claim 1, wherein the source contact region of the active layer is made conductive, and wherein the drain contact region of the active layer is made conductive.
9. An array substrate, comprising a substrate, and a plurality of the thin film transistors of claim 1 arranged on the substrate in an array.
10. A display panel comprising the thin film transistor according to claim 1 or the array substrate according to claim 9.
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