CN109638078B - TFT preparation method, TFT, OLED backboard and display device - Google Patents

TFT preparation method, TFT, OLED backboard and display device Download PDF

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CN109638078B
CN109638078B CN201811330692.0A CN201811330692A CN109638078B CN 109638078 B CN109638078 B CN 109638078B CN 201811330692 A CN201811330692 A CN 201811330692A CN 109638078 B CN109638078 B CN 109638078B
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layer
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grid
semiconductor
semiconductor layer
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CN109638078A (en
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周星宇
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks

Abstract

The embodiment of the invention discloses a TFT (thin film transistor) preparation method, a TFT, an OLED (organic light emitting diode) back plate and a display device, wherein the method comprises the following steps: forming a light shielding layer on the glass substrate by using a black photoresist material; depositing a buffer layer, a first semiconductor layer, a first grid insulating layer and a grid metal layer on the shading layer in sequence; etching the first grid insulation layer except the lower part of the grid metal layer to obtain a second grid insulation layer; carrying out plasma treatment on the first semiconductor layer, so that the first semiconductor layer which is not shielded by the second grid electrode insulating layer forms a semiconductor layer, and the rest forms a second semiconductor layer; and sequentially depositing an interlayer insulating layer, a source drain metal layer, a passivation layer, a planarization layer, a pixel electrode layer and a pixel definition layer. According to the embodiment of the invention, the thickness of the planarization layer can be reduced, the accuracy of the exposure process is improved, and the flatness of the OLED light emitting area corresponding to the TFT is increased.

Description

TFT preparation method, TFT, OLED backboard and display device
Technical Field
The invention relates to the technical field of semiconductor materials, in particular to a TFT (thin film transistor) preparation method, a TFT, an OLED (organic light emitting diode) back plate and a display device.
Background
The OLED, i.e., an Organic Light-Emitting Diode (Organic Light-Emitting Diode), has characteristics of self-luminescence, high brightness, wide viewing angle, high contrast, flexibility, low power consumption, etc., and thus has attracted much attention as a new generation of display mode, and has begun to gradually replace the conventional liquid crystal display, and is widely applied to mobile phone screens, computer monitors, full-color televisions, etc.
In the OLED device manufactured by the inkjet printing process, it is required that the surface of the light emitting region is as flat as possible, so that the thickness of the OLED layer is uniform, but generally, a Thin-film transistor (TFT) substrate has various traces and vias, which cause fluctuation. A common TFT substrate is manufactured with a Planarization Layer (PLN), and for inkjet printing (InkjetPrinter, IJP) with high requirement for flatness, the PLN needs to be made thick, which wastes materials on one hand, and on the other hand, the exposure process is difficult to control because the material is too thick, and the impurity content of the material is increased, which affects the TFT performance.
Disclosure of Invention
The embodiment of the invention provides a TFT (thin film transistor) preparation method, a TFT, an OLED (organic light emitting diode) back plate and a display device, so that the thickness of a planarization layer can be reduced, the accuracy of an exposure process is improved, and the flatness of an OLED light emitting area corresponding to the TFT is increased.
In order to solve the above problem, in a first aspect, the present invention provides a method for manufacturing a TFT, the method including:
forming a light shielding layer on the glass substrate by using a black photoresist material;
depositing a buffer layer, a first semiconductor layer, a first grid insulating layer and a grid metal layer on the shading layer in sequence;
etching the first grid insulation layer except the lower part of the grid metal layer to obtain a second grid insulation layer;
performing plasma treatment on the first semiconductor layer, so that the first semiconductor layer which is not shielded by the second gate insulating layer forms a semiconductor layer, and the rest forms a second semiconductor layer;
sequentially depositing an interlayer insulating layer, a source drain metal layer, a passivation layer, a planarization layer, a pixel electrode layer and a pixel defining layer;
the light shielding layer comprises a first light shielding area, and the width of the second semiconductor layer is smaller than that of the first light shielding area.
Further, the light-shielding layer further includes a second light-shielding region, and the second light-shielding region is located below the pixel opening region of the pixel defining layer.
Further, the step of forming a light shielding layer on the glass substrate using a black photoresist includes:
and coating a layer of acrylic or polyimide black photoresist material, and defining a pattern by using yellow light to form a light shielding layer.
Furthermore, the thickness of the shading layer is 0.5-4 μm.
Further, the step of sequentially depositing a buffer layer, a first semiconductor layer, a first gate insulating layer and a gate metal layer on the light-shielding layer includes:
depositing a layer of multi-layer structure film on the shading layer to serve as a buffer layer;
depositing a layer of metal oxide semiconductor material as a first semiconductor layer, and etching the pattern;
depositing a multi-layer structure film as a first grid insulation layer;
and depositing a layer of metal as a grid metal layer.
Further, the step of etching away the first gate insulating layer outside the lower portion of the gate metal layer to obtain a second gate insulating layer includes:
etching the graph of the grid metal layer by using yellow light;
and etching the gate insulating layer by utilizing the self-alignment of the pattern of the gate metal layer, and etching off the first gate insulating layer except the part below the gate metal layer to obtain a second gate insulating layer.
Further, the step of performing plasma processing on the first semiconductor layer so that the first semiconductor layer not covered by the second gate insulating layer forms a conductor layer, and the remaining step of forming the second semiconductor layer includes:
performing N on the first semiconductor layer2And performing plasma treatment, so that the first semiconductor layer which is not shielded by the second grid insulating layer forms an N-ion conductor layer, and the second semiconductor layer is formed in the rest.
Further, the step of sequentially depositing an interlayer insulating layer, a source/drain metal layer, a passivation layer, a planarization layer, a pixel electrode layer, and a pixel definition layer includes:
depositing an interlayer insulating layer, and performing yellow light and etching to form an opening;
depositing a layer of metal in the opening of the interlayer insulating layer to serve as a source drain metal layer;
depositing a passivation layer on the source drain metal layer;
manufacturing a planarization layer on the passivation layer and using a yellow light contact hole;
and manufacturing a pixel electrode and a pixel definition layer on the planarization layer.
Further, the thickness of the planarization layer is 0.5-2 μm.
In a second aspect, the present application provides a TFT comprising:
a glass substrate;
a light-shielding layer; the light shielding layer is prepared from a black light resistance material and comprises a first light shielding area;
the buffer layer is prepared on the surface of the shading layer;
the semiconductor layer is prepared on the surface of the buffer layer, and the width of the semiconductor layer is smaller than that of the first shading area;
conductor regions prepared on both sides of the semiconductor layer;
a gate insulating layer prepared on the semiconductor layer;
the grid metal layer is prepared on the grid insulating layer;
the interlayer dielectric layer covers the grid metal layer and the buffer layer, and two openings are correspondingly arranged above the conductor region;
the source drain metal layer comprises a source electrode metal area and a drain electrode metal area which are respectively arranged in the two openings between the interlayer dielectric layers;
the passivation layer is prepared on the surface of the interlayer dielectric layer and covers the source drain metal layer;
the planarization layer is prepared on the passivation layer, wherein the passivation layer and the planarization layer on the drain metal region form an opening;
the pixel electrode layer is prepared on the planarization layer and in the openings of the passivation layer and the planarization layer;
and the pixel defining layer is prepared on the pixel electrode layer and is filled in the opening formed by the passivation layer and the planarization layer.
Further, the light-shielding layer further includes a second light-shielding region, and the second light-shielding region is located below the pixel opening region of the pixel defining layer.
Furthermore, the thickness of the shading layer is 0.5-4 μm.
Further, the thickness of the planarization layer is 0.5-2 μm.
Further, the semiconductor layer is an N-ion conductor layer.
In a third aspect, the present application provides an OLED backplane comprising a TFT as described in any of the second aspects.
In a fourth aspect, the present application provides a display device comprising the OLED backplane as described in the third aspect.
The method of the embodiment of the invention utilizes black photoresist material to form a shading layer on a glass substrate; depositing a buffer layer, a first semiconductor layer, a first grid insulating layer and a grid metal layer on the shading layer in sequence; etching the first grid insulation layer except the lower part of the grid metal layer to obtain a second grid insulation layer; carrying out plasma treatment on the first semiconductor layer, so that the first semiconductor layer which is not shielded by the second grid electrode insulating layer forms a semiconductor layer, and the rest forms a second semiconductor layer; and sequentially depositing an interlayer insulating layer, a source drain metal layer, a passivation layer, a planarization layer, a pixel electrode layer and a pixel definition layer. According to the embodiment of the invention, the black light resistance material is adopted to prepare the light shielding layer on the glass substrate, on one hand, the light shielding layer is not made of a metal material, a connection signal is not needed, and a special hole forming process is not needed to be carried out on the buffer layer, and meanwhile, the width of the second semiconductor layer is smaller than that of the first light shielding region in the light shielding layer, so that the semiconductor layer of the channel is protected from being irradiated by light, the thickness of the planarization layer can be reduced, the accuracy of an exposure process is improved, and the flatness of an OLED light emitting region corresponding to.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart of an embodiment of a method for manufacturing a TFT according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an embodiment of a TFT according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
As shown in fig. 1, which is a schematic diagram of an embodiment of a method for manufacturing a TFT according to an embodiment of the present invention, the method includes:
s101, forming a light shielding layer on the glass substrate by using a black photoresist material.
Wherein the step of forming the light-shielding layer on the glass substrate using the black photoresist may further include: and coating a layer of acrylic or polyimide black photoresist material, and defining a pattern by using yellow light to form a light shielding layer.
S102, depositing a buffer layer, a first semiconductor layer, a first grid insulating layer and a grid metal layer on the shading layer in sequence.
In this embodiment, the step of sequentially depositing the buffer layer, the first semiconductor layer, the first gate insulating layer, and the gate metal layer on the light-shielding layer may further include: depositing a layer of multi-layer structure film on the shading layer to serve as a buffer layer; depositing a layer of metal oxide semiconductor material as a first semiconductor layer, and etching the pattern; depositing a multi-layer structure film as a first grid insulation layer; and depositing a layer of metal as a grid metal layer.
Wherein, a multi-layer structure film is deposited on the light-shielding layer as a buffer layer, and the thickness of the buffer layer can be 1000-5000 angstroms. The multilayer structure film corresponding to the buffer layer may be SiOxOr SiNxThe film of (2) may be SiOxAnd SiNxThe composition of the multilayer structure film is not limited herein.
In the embodiment of the present invention, when a layer of metal Oxide semiconductor material is deposited as the first semiconductor layer, the metal Oxide semiconductor material (Oxide) may be Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), Indium Gallium Zinc Tin Oxide (IGZTO), or the like, the thickness is 100-.
In addition, the first gate insulating layer refers to a GI layer, which is formed by a process in LTPS called GI position, i.e., GI layer Deposition. GI is an insulating layer between the gate metal and the semiconductor layer in a TFT, usually SiNx/SiOxIt is called Gate Insulator. Specifically, in the step of depositing a multi-layer structure film as the first gate insulating layer, the multi-layer structure film corresponding to the first gate insulating layer may be SiOxOr SiNxThe multilayer structure film of (2) may also be SiOxAnd SiNxThe thickness of the formed multilayer structure film is 1000-3000 angstroms.
S103, etching off the first gate insulating layer except the lower part of the gate metal layer to obtain a second gate insulating layer.
Specifically, the step of etching away the first gate insulating layer except under the gate metal layer to obtain the second gate insulating layer may further include: etching the graph of the grid metal layer by using yellow light; and etching the gate insulating layer by utilizing the self-alignment of the pattern of the gate metal layer, and etching off the first gate insulating layer except the part below the gate metal layer to obtain a second gate insulating layer. In the process, the grid insulation layer exists only under the film layer with the grid metal pattern, and the grid insulation layer is etched at the rest part.
And S104, carrying out plasma treatment on the first semiconductor layer, so that the first semiconductor layer which is not shielded by the second grid electrode insulating layer forms a semiconductor layer, and the rest forms a second semiconductor layer.
The light shielding layer comprises a first light shielding area, and the width of the second semiconductor layer is smaller than that of the first light shielding area, so that the first light shielding area can shield the second semiconductor layer area, and the semiconductor layer of the channel is protected from being irradiated by light.
Specifically, the performing plasma processing on the first semiconductor layer to form a conductor layer on the first semiconductor layer uncovered by the second gate insulating layer, and the remaining step of forming the second semiconductor layer may further include: performing N on the first semiconductor layer2And performing plasma treatment, so that the first semiconductor layer which is not shielded by the second gate insulating layer forms an N-ion conductor layer, and the second semiconductor layer is formed in the rest. As a final result, for the first semiconductor layer without the second gate insulating layer and gate metal layer over it, the resistance is significantly reduced after processing, forming an N + conductor layer, and the second semiconductor layer under the second gate insulating layer is not processed to maintain the semiconductor characteristics as a TFT channel.
And S105, sequentially depositing an interlayer insulating layer, a source drain electrode metal layer, a passivation layer, a planarization layer, a pixel electrode layer and a pixel definition layer.
In the embodiment of the present invention, the step of sequentially depositing the interlayer insulating layer, the source/drain metal layer, the passivation layer, the planarization layer, the pixel electrode layer, and the pixel defining layer may further include: depositing an interlayer insulating layer, and performing yellow light and etching to form an opening; depositing a layer of metal in the opening of the interlayer insulating layer to serve as a source drain metal layer; depositing a passivation layer on the source drain metal layer; manufacturing a planarization layer on the passivation layer and using a yellow light contact hole; and manufacturing a pixel electrode and a pixel definition layer on the planarization layer.
Wherein the deposited interlayer insulating layer ILD may be SiOxOr SiNxThe multilayer structure film of (2) may also be SiOxAnd SiNxThe thickness of the formed multilayer structure film is 2000A-10000A, and yellow light and etching are carried out after an interlayer insulating layer ILD is deposited.
In addition, the material of the source and drain metal layer may be Mo, Al, Cu, Ti, or the like, or an alloy of at least two of Mo, Al, Cu, Ti, or the like, the thickness of the source and drain metal layer is 2000-. Then, a planarization layer is manufactured on the passivation layer, and a yellow light contact hole is used; and manufacturing a pixel electrode and a pixel definition layer on the planarization layer. The passivation layer may be SiOxOr SiNxThe multilayer structure film of (2) may also be SiOxAnd SiNxThe thickness of the formed multilayer structure film is 1000-5000 angstroms.
The thickness of the planarization layer in the embodiment of the invention can be 0.5-2 μm. Compared with the prior art, the flatness of the OLED light emitting area is greatly reduced, namely, the flatness of the OLED light emitting area is improved and the degree of concave-convex is reduced because the light shielding layer is arranged, so that the PLN (Planarization layer) does not need too thick photoresist material.
The method of the embodiment of the invention utilizes black photoresist material to form a shading layer on a glass substrate; depositing a buffer layer, a first semiconductor layer, a first grid insulating layer and a grid metal layer on the shading layer in sequence; etching the first grid insulation layer except the lower part of the grid metal layer to obtain a second grid insulation layer; carrying out plasma treatment on the first semiconductor layer, so that the first semiconductor layer which is not shielded by the second grid electrode insulating layer forms a semiconductor layer, and the rest forms a second semiconductor layer; and sequentially depositing an interlayer insulating layer, a source drain metal layer, a passivation layer, a planarization layer, a pixel electrode layer and a pixel definition layer. According to the embodiment of the invention, the black light resistance material is adopted to prepare the light shielding layer on the glass substrate, on one hand, the light shielding layer is not made of a metal material, a connection signal is not needed, and a special hole forming process is not needed to be carried out on the buffer layer, and meanwhile, the width of the second semiconductor layer is smaller than that of the first light shielding region in the light shielding layer, so that the semiconductor layer of the channel is protected from being irradiated by light, the thickness of the planarization layer can be reduced, the accuracy of an exposure process is improved, and the flatness of an OLED light emitting region corresponding to.
Further, in some embodiments of the present invention, the light shielding layer may further include a second light shielding region, and the second light shielding region is located below the pixel opening region of the pixel defining layer. The pixel opening area of the pixel definition layer corresponds to the concave position of the light emitting area of the OLED backboard, and the concave position of the light emitting area of the OLED backboard is also provided with a light shielding layer pattern (a second light shielding area), so that light irradiation is further avoided, and the accuracy of an exposure process is improved.
In order to achieve a good light shielding effect, in this embodiment, the thickness of the light shielding layer may be set to be 0.5 to 4 μm. Preferably, the thickness of the shading layer can be set to be 0.8-3 μm. Correspondingly, the first light-shielding region and the second light-shielding region may be uniform in thickness with the light-shielding layer.
An embodiment of the present invention further provides a TFT, as shown in fig. 2, which is a schematic structural diagram of an embodiment of the TFT in the embodiment of the present invention, where the TFT includes:
a glass substrate 201;
a light-shielding layer 202; the light shielding layer 202 is prepared from a black light-resistant material and is prepared on the surface of the glass substrate 201, and the light shielding layer 202 comprises a first light shielding region 2021;
a buffer layer 203 prepared on the surface of the light-shielding layer 202;
the semiconductor layer 204 is prepared on the surface of the buffer layer, and the width of the semiconductor layer is smaller than that of the first shading area;
a conductor region 205 formed on both sides of the semiconductor layer 204;
a gate insulating layer 206 formed on the semiconductor layer 204;
a gate metal layer 207 formed on the gate insulating layer 206;
an interlayer dielectric layer 208 covering the gate metal layer 207 and the buffer layer 203, and two openings are correspondingly arranged above the conductor region 205;
the source-drain metal layer 209 comprises a source metal region and a drain metal region 2091, which are respectively arranged in the two openings between the interlayer dielectric layers 208;
a passivation layer 210 prepared on the surface of the interlayer dielectric layer 208 and covering the source drain metal layer 209;
a planarization layer 211 formed on the passivation layer 210, wherein the passivation layer 210 and the planarization layer 211 on the drain metal region 2091 form an opening;
a pixel electrode layer 212 formed on the planarization layer and in the openings of the passivation layer 210 and the planarization layer 211;
and a pixel defining layer 213, which is prepared on the pixel electrode layer 212 and fills the openings formed by the passivation layer 210 and the planarization layer 211.
In the embodiment of the invention, the light-shielding layer 202 is prepared by adopting the black light-resistant material on the glass substrate, on one hand, because the light-shielding layer 202 is not made of a metal material, a signal is not required to be connected, and a special hole forming process is not required to be carried out on the buffer layer 203, and meanwhile, because the width of the semiconductor layer 204 is smaller than that of the first light-shielding region 2021 in the light-shielding layer 202, the semiconductor layer 204 of the channel is protected from being irradiated by light, so that the thickness of the planarization layer 211 can be reduced, the accuracy of an exposure process is improved, and the.
Further, the light-shielding layer 202 further includes a second light-shielding region 2022, and the second light-shielding region 2022 is located below the pixel opening region of the pixel defining layer 213. The pixel opening region of the pixel defining layer 213 corresponds to the recessed portion of the light emitting region of the OLED backplane, and the recessed portion of the light emitting region of the OLED backplane also has a light shielding layer pattern (a second light shielding region 2022), so as to further avoid light irradiation and improve the accuracy of the exposure process.
Further, the thickness of the light-shielding layer 202 is 0.5 to 4 μm. Preferably, the thickness of the shading layer can be set to be 0.8-3 μm. Correspondingly, the first light-shielding region and the second light-shielding region may be uniform in thickness with the light-shielding layer.
Further, the planarization layer 211 has a thickness of 0.5 to 2 μm. Compared with the prior art, the flatness of the OLED light emitting area is greatly reduced, namely, the flatness of the OLED light emitting area is improved and the degree of concave-convex is reduced because the light shielding layer is arranged, so that the PLN (Planarization layer) does not need too thick photoresist material.
Further, the semiconductor layer 204 is an N-ion conductor layer.
Also provided in embodiments of the present invention is an OLED backplane comprising a TFT as described in any of the embodiments described in embodiments of the present invention.
Embodiments of the present invention further provide a display device, including an OLED backplane as described in any of the embodiments described in embodiments of the present invention.
In a specific implementation, each unit or module may be implemented as an independent entity, or may be combined arbitrarily, and implemented as one or several entities, and the specific implementation of each unit or module may refer to the foregoing method embodiments, for example, the thickness of each layer and the selection of materials of each layer, and is not described herein again.
The TFT manufacturing method, the TFT, the OLED backplane and the display device provided in the embodiments of the present invention are described in detail above, and specific examples are applied herein to illustrate the principles and embodiments of the present invention, and the description of the embodiments is only used to help understanding the method and the core concept of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (14)

1. A method of fabricating a TFT, the method comprising:
forming a light shielding layer on the glass substrate by using a black photoresist material;
depositing a buffer layer, a first semiconductor layer, a first grid insulating layer and a grid metal layer on the shading layer in sequence;
etching the first grid insulation layer except the lower part of the grid metal layer to obtain a second grid insulation layer;
carrying out plasma treatment on the first semiconductor layer, so that the first semiconductor layer which is not shielded by the second grid electrode insulating layer forms a semiconductor layer, and the rest forms a second semiconductor layer;
sequentially depositing an interlayer insulating layer, a source drain metal layer, a passivation layer, a planarization layer, a pixel electrode layer and a pixel defining layer;
the light shielding layer comprises a first light shielding area, and the width of the second semiconductor layer is smaller than that of the first light shielding area;
the light-shielding layer further comprises a second light-shielding region, the second light-shielding region is located below the pixel opening region of the pixel defining layer, and the thickness of the light-shielding material in the first light-shielding region is equal to that of the light-shielding material in the second light-shielding region.
2. The method for manufacturing a TFT according to claim 1,
the step of forming the light shielding layer on the glass substrate by using the black photoresist material includes:
and coating a layer of acrylic or polyimide black photoresist material, and defining a pattern by using yellow light to form a light shielding layer.
3. The method for manufacturing a TFT according to claim 2,
the thickness of the shading layer is 0.5-4 mu m.
4. The method for manufacturing a TFT according to claim 1,
the step of depositing a buffer layer, a first semiconductor layer, a first gate insulating layer and a gate metal layer in sequence on the light-shielding layer includes:
depositing a layer of multi-layer structure film on the shading layer to serve as a buffer layer;
depositing a layer of metal oxide semiconductor material as a first semiconductor layer, and etching the pattern;
depositing a multi-layer structure film as a first grid insulation layer;
and depositing a layer of metal as a grid metal layer.
5. The method for manufacturing a TFT according to claim 1,
the step of etching away the first gate insulating layer outside the lower portion of the gate metal layer to obtain a second gate insulating layer includes:
etching the graph of the grid metal layer by using yellow light;
and etching the gate insulating layer by utilizing the self-alignment of the pattern of the gate metal layer, and etching off the first gate insulating layer except the part below the gate metal layer to obtain a second gate insulating layer.
6. The method for manufacturing a TFT according to claim 1, wherein the step of performing plasma treatment on the first semiconductor layer so that the first semiconductor layer uncovered by the second gate insulating layer forms a conductor layer and the remaining steps of forming the second semiconductor layer include:
and carrying out N2 plasma treatment on the first semiconductor layer, so that the first semiconductor layer which is not shielded by the second gate insulating layer forms an N ion conductor layer, and the rest forms a second semiconductor layer.
7. The method for manufacturing a TFT according to claim 1,
the step of depositing the interlayer insulating layer, the source drain metal layer, the passivation layer, the planarization layer, the pixel electrode layer and the pixel definition layer in sequence comprises the following steps:
depositing an interlayer insulating layer, and performing yellow light and etching to form an opening;
depositing a layer of metal in the opening of the interlayer insulating layer to serve as a source drain metal layer;
depositing a passivation layer on the source drain metal layer;
manufacturing a planarization layer on the passivation layer and utilizing a yellow light contact hole;
and manufacturing a pixel electrode and a pixel definition layer on the planarization layer.
8. The method for manufacturing a TFT according to claim 7,
the thickness of the planarization layer is 0.5-2 μm.
9. A TFT, comprising:
a glass substrate;
the shading layer is prepared on the surface of the glass substrate and is made of a black light resistance material, and the shading layer comprises a first shading area;
the buffer layer is prepared on the surface of the shading layer;
the semiconductor layer is prepared on the surface of the buffer layer, and the width of the semiconductor layer is smaller than that of the first shading area;
conductor regions prepared on both sides of the semiconductor layer;
a gate insulating layer prepared on the semiconductor layer;
the grid metal layer is prepared on the grid insulating layer;
the interlayer dielectric layer covers the grid metal layer and the buffer layer, and two openings are correspondingly arranged above the conductor region;
the source drain metal layer comprises a source electrode metal area and a drain electrode metal area which are respectively arranged in the two openings between the interlayer dielectric layers;
the passivation layer is prepared on the surface of the interlayer dielectric layer and covers the source drain metal layer;
the planarization layer is prepared on the passivation layer, wherein the passivation layer and the planarization layer on the drain metal region form an opening;
the pixel electrode layer is prepared on the planarization layer and in the openings of the passivation layer and the planarization layer;
the pixel defining layer is prepared on the pixel electrode layer and is filled in the opening formed by the passivation layer and the planarization layer;
the light shielding layer further comprises a second light shielding area, the second light shielding area is located below the pixel opening area of the pixel definition layer, and the thickness of the light shielding material in the first light shielding area is equal to that of the light shielding material in the second light shielding area.
10. The TFT according to claim 9,
the thickness of the shading layer is 0.5-4 mu m.
11. The TFT according to claim 9,
the thickness of the planarization layer is 0.5-2 μm.
12. The TFT according to claim 9,
the semiconductor layer is an N-ion conductor layer.
13. An OLED backplane comprising the TFT of any of claims 9 to 12.
14. A display device comprising the OLED backplane as claimed in claim 13.
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