CN111739895A - TFT backboard structure and manufacturing method - Google Patents

TFT backboard structure and manufacturing method Download PDF

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Publication number
CN111739895A
CN111739895A CN202010610465.4A CN202010610465A CN111739895A CN 111739895 A CN111739895 A CN 111739895A CN 202010610465 A CN202010610465 A CN 202010610465A CN 111739895 A CN111739895 A CN 111739895A
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layer
metal
metal layer
active
stress buffer
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温质康
林佳龙
乔小平
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Fujian Huajiacai Co Ltd
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Fujian Huajiacai Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

Abstract

The invention discloses a TFT back plate structure, wherein a first active layer is arranged on a substrate, a first grid electrode insulating layer is arranged on the first active layer, and a first grid electrode layer is arranged on the first grid electrode insulating layer; the passivation layer covers the first active layer, the first grid insulating layer and the first grid layer; the first metal layer is arranged on the passivation layer and is respectively arranged on two sides above the first gate layer, the passivation layer is also arranged on two through holes taking the first active layer as the bottom, and the first metal layer is respectively connected with the first active layer through the two through holes; the first stress buffer layer is arranged on the first metal layer, the second metal layer is arranged on the first stress buffer layer, and the second metal layer wraps the first stress buffer layer; the flat layer covers the first stress buffer layer, the first metal layer and the second metal layer, and the electrode layer is arranged on the flat layer and is connected with the second metal layer through the through hole. The method solves the problems of warping caused by temperature rise and thermal stress accumulation in the process of depositing the disposable thick film, as well as overlarge resistance and low response speed.

Description

TFT backboard structure and manufacturing method
Technical Field
The invention relates to the field of TFT devices, in particular to a TFT backboard structure and a manufacturing method thereof.
Background
The Organic Light Emitting Diode (OLED) display has the characteristics of low power consumption, wide viewing angle, fast response speed, ultra-Light weight, thinness, good shock resistance and the like, has a wide use temperature range, can realize flexible display and large-area full-color display and the like, and is considered as a display device with the most development potential by the industry.
The currently developed OLED is intended to develop a large-sized 8K ultra-high-definition display, where a large-sized TFT array substrate includes a plurality of gate lines and data lines, the plurality of gate lines and the plurality of data lines perpendicular to each other form a plurality of pixel units, and each pixel unit is provided with a Thin Film Transistor (TFT), a pixel electrode, and a storage capacitor.
With the increase of the panel size, the metal gate lines and the data lines are also correspondingly lengthened, in order to protect the charging rate of the large-size display screen and reduce the requirement of response time, the resistance of the metal lines needs to be reduced, the conductive material is changed or the thickness of the material is increased, but the increase of the thickness has certain influence on part of the subsequent processes, the increase of the thickness causes stress concentration of the metal line films, and in addition, the influence of gravity at the center of the panel is large, the warping of the edge films is more serious, and the products influencing the subsequent processes are bad.
Disclosure of Invention
Therefore, it is desirable to provide a TFT backplane structure and a method for manufacturing the same, which can solve the problem of warpage of a large-sized panel metal thick film and reduce and speed up the response speed.
To achieve the above object, the inventors provide a TFT backplane structure comprising: the device comprises a substrate, a first active layer, a first grid insulating layer, a first grid layer, a passivation layer, a flat layer, an electrode layer, a first stress buffer layer, a first metal layer and a second metal layer;
the first active layer is arranged on the substrate, the first grid insulating layer is arranged on the first active layer, and a first grid layer is arranged on the first grid insulating layer; the passivation layer covers the first active layer, the first grid insulating layer and the first grid layer; the first metal layer is arranged on the passivation layer and is respectively arranged on two sides above the first gate layer, the passivation layer is also provided with two through holes taking the first active layer as the bottom, and the first metal layer is respectively connected with the first active layer through the two through holes; the first stress buffer layer is arranged on the first metal layer, the second metal layer is arranged on the first stress buffer layer, the second metal layer wraps the first stress buffer layer, and the second metal layer is connected with the first metal layer; the flat layer covers the first stress buffer layer, the first metal layer and the second metal layer, and the electrode layer is arranged on the flat layer and is connected with the second metal layer through a through hole in the flat layer.
Further, between the substrate and the first active layer, the method further comprises: a light-shielding layer and a buffer layer; the light shading layer is arranged on the substrate, the buffer layer covers the light shading layer, and the first active layer is arranged on the buffer layer.
Further, still include: the storage capacitor is arranged on one side of the first metal layer and comprises: the third metal layer, the fourth metal layer and the second stress buffer layer; the third metal layer is arranged on the passivation layer, the second stress buffer layer is arranged on the third metal layer, and the fourth metal layer is arranged on the second stress buffer layer.
Further, the storage capacitor further includes: a second active layer, a second gate insulating layer, and a second gate layer
The second active layer is arranged on the buffer layer, the second grid insulating layer is arranged on the second active layer, a second grid layer is arranged on the second grid insulating layer, and the passivation layer covers the second active layer, the second grid insulating layer and the second grid layer; the third metal layer is arranged on the passivation layer, the second stress buffer layer is arranged on the third metal layer, the fourth metal layer is arranged on the second stress buffer layer, and the flat layer covers the third metal layer, the fourth metal layer and the second stress buffer layer.
Further, the width of the light shielding layer is larger than the widths of the first active layer and the second active layer.
Further, the first stress buffer layer is an organic insulating layer.
The inventor also provides a manufacturing method of the TFT backboard structure, which comprises the following steps:
manufacturing a first active layer on a substrate;
manufacturing a first grid insulation layer on the first active layer;
depositing a first gate layer on the first gate insulating layer;
manufacturing a passivation layer, and etching the passivation layer to form two through holes with the first active layer as a bottom;
depositing a first metal layer on the two through holes, wherein the first metal layer is connected with the first active layer through the two through holes;
manufacturing a first stress buffer layer on the first metal layer;
depositing a second metal on the first stress buffer layer, exposing, developing and stripping the second metal layer to obtain a second metal layer film, wherein the second metal layer film coats the first stress buffer layer and is connected with the first metal layer;
manufacturing a flat layer, and etching the flat layer to form a through hole with the second metal layer as a bottom;
and manufacturing an electrode layer, wherein the electrode layer is connected with the second metal through a through hole on the flat layer.
Further, in the step of depositing the first metal layer on two of the through holes, simultaneously depositing a third metal layer on the passivation layer;
when the step of manufacturing the first stress buffer layer on the first metal layer is carried out, simultaneously manufacturing a second stress buffer layer on the third metal layer;
and (3) when the second metal is deposited on the first stress buffer layer, simultaneously manufacturing a fourth metal layer on the second stress buffer layer, and exposing, developing and stripping the fourth metal layer to obtain a fourth metal layer film.
Further, the method also comprises the following steps:
when the step of manufacturing the first active layer is carried out, simultaneously manufacturing a second active layer on one side of the first active layer;
when the step of manufacturing the first grid insulation layer on the first active layer is carried out, a second grid insulation layer is manufactured on the second active layer at the same time;
in the step of depositing the first gate layer on the first gate insulating layer, the second gate layer is simultaneously deposited on the second gate insulating layer.
Further, the second metal layer and the electrode layer are deposited by adopting a physical vapor deposition method; the first grid electrode insulating layer, the passivation layer and the flat layer are deposited by a chemical vapor deposition method.
Different from the prior art, the technical scheme designs the metal single layer of the source and the drain into a laminated structure of a first stress buffer layer, a first metal layer and a second metal layer by changing the metal structure of the source and the drain, the first stress buffer layer can relieve stress concentration of a metal film layer and release stress, and the problem of warping caused by temperature rise and thermal stress accumulation in the deposition process of a disposable thick film is solved. The first stress buffer layer separates the first metal layer from the second metal layer to form a parallel equivalent resistor which is reduced, and the problems of overlarge resistance and low response speed in the display process of a large-size panel can be solved.
Drawings
FIG. 1 is a diagram illustrating the structure of a third metal layer and a fourth metal layer according to an embodiment;
FIG. 2 is a diagram illustrating the structure of a first metal layer and a second metal layer according to an embodiment;
FIG. 3 is a schematic diagram of the first metal layer and the second metal layer connected in parallel;
fig. 4 is a diagram illustrating a structure of a storage capacitor according to the related art.
Description of reference numerals:
1. a substrate; 2. a first active layer; 3. a first gate insulating layer; 4. a first gate layer; 5. a passivation layer; 6. a planarization layer; 7. an electrode layer; 8. a first stress buffer layer; 9. a first metal layer; 10. a second metal layer; 11. a light-shielding layer; 12. a buffer layer; 13. a storage capacitor;
131. a second active layer; 132. a second gate insulating layer; 133. a second gate layer; 134. a third metal layer; 135. a fourth metal layer; 136. and a second stress buffer layer.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1 to 4, the present embodiment provides a TFT backplane structure, which includes: the structure comprises a substrate 1, a first active layer 2, a first gate insulating layer 3, a first gate layer 4, a passivation layer 5, a flat layer 6, an electrode layer 7, a first stress buffer layer 8, a first metal layer 9 and a second metal layer 10; the first active layer 2 is arranged on the substrate 1, the first gate insulating layer 3 is arranged on the first active layer 2, and the first gate layer 4 is arranged on the first gate insulating layer 3; the passivation layer 5 covers the first active layer 2, the first gate insulating layer 3 and the first gate layer 4; the first metal layers 9 are arranged on the passivation layer 5 and are respectively arranged on two sides above the first gate layer 4, the passivation layer 5 is also arranged on two through holes taking the first active layer 2 as a bottom, and the first metal layers 9 are respectively connected with the first active layer 2 through the two through holes; the first stress buffer layer 8 is arranged on the first metal layer 9, the second metal layer 10 is arranged on the first stress buffer layer 8, the second metal layer 10 wraps the first stress buffer layer 8, and the second metal layer 10 is connected with the first metal layer 9; it should be noted that, the second metal layer 10 is connected to the first metal layer 9 after surrounding the first stress buffer layer 8. The flat layer 6 covers the first stress buffer layer 8, the first metal layer 9 and the second metal layer 10, and the electrode layer 7 is disposed on the flat layer 6 and connected to the second metal layer 10 through a through hole on the flat layer 6. It should be noted that, in the present embodiment, the two through holes both have the first active layer 2 as a bottom, are disposed on two sides of the first gate layer 4, and are filled with the source metal or the drain metal, so that the first metal layer 9 is connected to the first gate layer 4, and the number of the first metal layer 9 is also two corresponding to the two through holes. In an embodiment, the widths of the first active layer 2, the first gate insulating layer 3 and the first gate layer 4 are reduced layer by layer, and two vias will be disposed on the first active layer 2 together with the first gate insulating layer 3. The first stress buffer layer 8 is coated on the first metal layer 9 by Coater, and the coating range is smaller than the upper surface of the first metal layer 9, so that the second metal layer 10 can completely cover the first stress buffer layer 8 when the second metal layer 10 is deposited. It should be further noted that the first stress buffer layer 8, the first metal layer 9, and the second metal layer 10 are not only used for counteracting the stress, but also used for reducing the resistance there. Referring to fig. 3, the first stress buffer layer 8 divides the first metal layer 9 and the second metal layer 10 into an upper layer and a lower layer, such that the first metal layer 9 is equivalent to the resistor R1, the second metal layer 10 is equivalent to the resistor R2, and the two layers are equivalent to the resistor R3 in parallel, and the parallel formula 1/R3 is 1/R1+1/R2, so that R3 < R1, R3 < R2, the more the resistors are connected in parallel, the smaller the resistors are. A storage capacitor in the background art can be further arranged on one side of the TFT backplane, as shown in fig. 2. According to the technical scheme, the metal structure of the source and the drain is changed, the metal single layer of the source and the drain is designed to be the laminated structure of the first stress buffer layer 8, the first metal layer 9 and the second metal layer 10, the stress concentration of the metal film layer can be relieved by the first stress buffer layer 8, the stress is released, and the warping problem caused by temperature rise and thermal stress accumulation in the deposition process of the disposable thick film is solved. The first stress buffer layer 8 separates the first metal layer 9 from the second metal layer 10 to form a parallel equivalent resistance, so that the parallel equivalent resistance is reduced, and the problems of overlarge resistance and low response speed in the display process of a large-size panel can be solved.
Referring to fig. 1 and 2, the TFT backplane structure further includes, between the substrate 1 and the first active layer 2: a light-shielding layer 11 and a buffer layer 12; the light shielding layer 11 is arranged on the substrate 1, the buffer layer 12 covers the light shielding layer 11, and the first active layer 2 is arranged on the buffer layer 12. Referring to fig. 2, a TFT backplane structure further includes: and the storage capacitor 13 is arranged on one side of the first active layer 2, the storage capacitor 13 is arranged on the substrate 1, and the bottom of the storage capacitor 13 and the bottom of the first active layer 2 are positioned on the same horizontal plane and used for maintaining the electric potential. It should be noted that, in the present embodiment, the storage capacitor 13 may be a conventional storage capacitor 13, that is, as shown in fig. 2, an active layer of the capacitor in fig. 2 is disposed on one side of the first active layer 2, and a gate insulating layer and a gate layer are sequentially stacked on the active layer, and a metal layer is disposed on the gate layer; the metal layer is arranged on the passivation layer 5, and the bottom of the metal layer is on the same horizontal plane with the first metal layer 9. The storage capacitor 13 is used to hold the potential and reduce the coupling capacitor voltage division.
The storage capacitor 13 is used for holding the potential and reducing the coupling capacitance voltage division, the storage capacitor 13 is formed by the overlapping part of the light shielding layer 11 and the gate layer in the conventional storage capacitor 13, the storage capacity of the storage capacitor 13 is small, the requirement of a high-quality display panel cannot be met, and if the area of the metal overlapping part is increased, the aperture ratio of the panel is reduced. Therefore, referring to fig. 1, the storage capacitor 13 provided in the present embodiment includes: a second active layer 131, a second gate insulating layer 132, a second gate layer 133, a third metal layer 134, a fourth metal layer 135, and a second stress buffer layer 136; the second active layer 131 is disposed on the buffer layer, the second gate insulating layer 132 is disposed on the second active layer 131, the second gate insulating layer 132 is disposed on the second gate layer 133, and the passivation layer 5 covers the second active layer 131, the second gate insulating layer 132, and the second gate layer 133; the third metal layer 134 is disposed on the passivation layer 5, the second stress buffer layer 136 is disposed on the third metal layer 134, the fourth metal layer 135 is disposed on the second stress buffer layer 136, and the planarization layer 6 covers the third metal layer 134, the fourth metal layer 135, and the second stress buffer layer 136. In this embodiment, the first stress buffer layer 8 and the second stress buffer layer 136 are a first polyimide stress buffer layer and a second polyimide stress buffer layer. And the width of the light shielding layer 11 is greater than the width of the first active layer 2 and the second active layer 131. The three-layer structure of the third metal layer 134, the fourth metal layer 135 and the second stress buffer layer 136 forms a new capacitor structure, and the three layers are all parallel structures and are not wrapped with each other. The capacitors formed by the third metal layer 134 and the fourth metal layer 135 are connected in parallel with the capacitors formed by the second active layer 131, the second gate insulating layer 132 and the second gate layer 133, and a passivation layer 5 is further disposed therebetween. The capacitance formed by the third metal layer 134 and the fourth metal layer 135 increases capacitance, and the relative area of the second active layer 131 and the light shielding layer 11 can be reduced on a certain basis, thereby improving the aperture ratio.
The embodiment also provides a manufacturing method of the TFT backplane structure, which includes the steps of: manufacturing a first active layer 2 on a substrate 1; manufacturing a first gate insulating layer 3 on the first active layer 2; depositing a first gate layer 4 on the first gate insulating layer 3; manufacturing a passivation layer 5, and etching the passivation layer 5 to form two through holes with the first active layer 2 as a bottom; manufacturing source electrode metal or drain electrode metal in the through hole, and depositing a first metal layer 9 on the two source electrode metal or drain electrode metal, wherein the first metal layer 9 is connected with the first active layer 2 through the two source electrode metal or drain electrode metal; manufacturing a first stress buffer layer 8 on the first metal layer 9; depositing a second metal on the first stress buffer layer 8, wherein the second metal layer 10 coats the first stress buffer layer 8, and the second metal layer 10 is connected with the first metal layer 9; manufacturing a flat layer 6, and etching the flat layer 6 to form a through hole with the second metal layer 10 as a bottom; and manufacturing an electrode layer 7, wherein the electrode layer 7 is connected with the second metal through a through hole on the flat layer 6. The first active layer 2 provided on the buffer layer is indium tin zinc oxide, and the first metal layer 9 is in partial contact with the conductive active layer. Of course, in some embodiments, before the "fabricating the first active layer 2 on the substrate 1", the method further includes the following steps: depositing a light shielding layer 11 on the substrate 1; and manufacturing a buffer layer. It should be noted that, the first metal layer 9 is deposited by PVD (physical vapor deposition), a specific pattern is formed by exposure, development and demolding, the first stress buffer layer 8PI (polyimide) is coated by a Coater, the first stress buffer layer 8 is cured, exposed and developed to form a specific pattern, the second metal layer 10 is formed by a PVD (physical vapor deposition) process, and the second metal layer 10 is exposed, developed and demolded to form the second metal layer 10 film wrapping the first stress buffer layer 8 and the first metal layer 9. Specifically, the first metal layer 9 is deposited, the thickness is estimated to be 0.4 um-0.5 um, then the first stress buffer layer 8, namely PI (polyimide), is coated on the first metal layer 9, a pattern is formed through exposure, development and etching, the second metal layer 10 is deposited, the second metal layer 10 forms a pattern wrapping the first metal layer 9 and the first stress buffer layer 8 after etching, and the first stress buffer layer 8 plays a role in eliminating the defects of stress concentration of the metal film due to over-thick film thickness.
It should be further explained that, the method also includes the following steps while manufacturing the TFT backplane structure: in the step of "manufacturing the first active layer 2", the second active layer 131 is simultaneously manufactured on one side of the first active layer 2; in the step of "fabricating the first gate insulating layer 3 on the first active layer 2", the second gate insulating layer 132 is simultaneously fabricated on the second active layer 131; in the step of "depositing the first gate layer 4 on the first gate insulating layer 3", simultaneously depositing the second gate layer 133 on the second gate insulating layer 132; depositing a third metal layer 134 simultaneously on the passivation layer 5, while depositing the first metal layer 9 on both of the vias; in the step "making the first stress buffer layer 8 on the first metal layer 9", making the second stress buffer layer 136 on the third metal layer 134 at the same time; in the step "deposit second metal on the first stress buffer layer 8", a fourth metal layer 135 is simultaneously formed on the second stress buffer layer 136. Specifically, the third metal layer 134 is deposited by PVD (physical vapor deposition), a specific pattern is formed by exposure, development and demolding, the second stress buffer layer 136, i.e., PI (polyimide), is coated by a Coater, the second stress buffer layer 136 forms a specific pattern by curing, exposure, development and demolding, the fourth metal layer 135 is formed by a PVD (physical vapor deposition) process, the fourth metal layer 135 forms a fourth metal layer 135 film by exposure, development and demolding, the three-layer structure of the capacitor can be simultaneously deposited and coated, only by one exposure, development, etching and demolding, the three-layer films are parallel structures and are not mutually wrapped, the two metal layers form a capacitor which is parallel to the original structure capacitor, the capacitor capacity is increased, the capacitor area can be reduced on a certain basis, and the aperture ratio is improved. Further, the electrode layer 7, the second active layer 131, the second gate layer 133, the third metal layer 134, and the fourth metal layer 135 form a parallel capacitor; the electrode layer 7 is ITO (indium tin oxide), and the second active layer 131 is a conductive second active layer 131IGZO (indium tin zinc oxide). In this embodiment, a third metal layer 134 is deposited to a thickness of 0.4um to 0.5um, a second stress buffer layer 136PI (polyimide) is coated on the third metal layer 134, the second stress buffer layer 136 is deposited to a thickness of 1um to 2um, a fourth metal layer 135 is deposited to cover the second stress buffer layer 136, and after exposure and etching, the three-layer film forms a sandwich structure, please refer to fig. 1. The light shielding layer 11 and the electrode layer 7 are deposited by adopting a physical vapor deposition method; the first gate insulating layer 3, the second gate insulating layer 132, the passivation layer 5 and the flat layer 6 are deposited by a chemical vapor deposition method; the formed patterns all need to be subjected to yellow light, wet etching and stripping processes.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.

Claims (10)

1. A TFT backplane structure, comprising: the device comprises a substrate, a first active layer, a first grid insulating layer, a first grid layer, a passivation layer, a flat layer, an electrode layer, a first stress buffer layer, a first metal layer and a second metal layer;
the first active layer is arranged on the substrate, the first grid insulating layer is arranged on the first active layer, and a first grid layer is arranged on the first grid insulating layer; the passivation layer covers the first active layer, the first grid insulating layer and the first grid layer; the first metal layer is arranged on the passivation layer and is respectively arranged on two sides above the first gate layer, the passivation layer is also provided with two through holes taking the first active layer as the bottom, and the first metal layer is respectively connected with the first active layer through the two through holes; the first stress buffer layer is arranged on the first metal layer, the second metal layer is arranged on the first stress buffer layer, the second metal layer wraps the first stress buffer layer, and the second metal layer is connected with the first metal layer; the flat layer covers the first stress buffer layer, the first metal layer and the second metal layer, and the electrode layer is arranged on the flat layer and is connected with the second metal layer through a through hole in the flat layer.
2. The TFT backplane structure of claim 1, further comprising, between the substrate and the first active layer: a light-shielding layer and a buffer layer; the light shading layer is arranged on the substrate, the buffer layer covers the light shading layer, and the first active layer is arranged on the buffer layer.
3. A TFT backplane structure according to claim 1 or 2, further comprising: the storage capacitor is arranged on one side of the first metal layer and comprises: the third metal layer, the fourth metal layer and the second stress buffer layer; the third metal layer is arranged on the passivation layer, the second stress buffer layer is arranged on the third metal layer, and the fourth metal layer is arranged on the second stress buffer layer.
4. The TFT backplane structure of claim 3, wherein the storage capacitor further comprises: a second active layer, a second gate insulating layer, and a second gate layer
The second active layer is arranged on the buffer layer, the second grid insulating layer is arranged on the second active layer, a second grid layer is arranged on the second grid insulating layer, and the passivation layer covers the second active layer, the second grid insulating layer and the second grid layer; and the flat layer covers the third metal layer, the fourth metal layer and the second stress buffer layer.
5. The TFT backplane structure of claim 4, wherein the width of the light shielding layer is greater than the width of the first and second active layers.
6. The TFT backplane structure of claim 1, wherein the first stress buffer layer is an organic insulating layer.
7. A manufacturing method of a TFT backboard structure is characterized by comprising the following steps:
manufacturing a first active layer on a substrate;
manufacturing a first grid insulation layer on the first active layer;
depositing a first gate layer on the first gate insulating layer;
manufacturing a passivation layer, and etching the passivation layer to form two through holes with the first active layer as a bottom;
depositing a first metal layer on the two through holes, wherein the first metal layer is connected with the first active layer through the two through holes;
manufacturing a first stress buffer layer on the first metal layer;
depositing a second metal on the first stress buffer layer, exposing, developing and stripping the second metal layer to obtain a second metal layer film, wherein the second metal layer film coats the first stress buffer layer and is connected with the first metal layer;
manufacturing a flat layer, and etching the flat layer to form a through hole with the second metal layer as a bottom;
and manufacturing an electrode layer, wherein the electrode layer is connected with the second metal through a through hole on the flat layer.
8. The method for fabricating a TFT backplane structure according to claim 7, wherein a third metal layer is deposited on the passivation layer at the same time as the step of depositing the first metal layer on the two through holes;
when the step of manufacturing the first stress buffer layer on the first metal layer is carried out, simultaneously manufacturing a second stress buffer layer on the third metal layer;
and (3) when the second metal is deposited on the first stress buffer layer, simultaneously manufacturing a fourth metal layer on the second stress buffer layer, and exposing, developing and stripping the fourth metal layer to obtain a fourth metal layer film.
9. The method of claim 7, further comprising the steps of:
when the step of manufacturing the first active layer is carried out, simultaneously manufacturing a second active layer on one side of the first active layer;
when the step of manufacturing the first grid insulation layer on the first active layer is carried out, a second grid insulation layer is manufactured on the second active layer at the same time;
in the step of depositing the first gate layer on the first gate insulating layer, the second gate layer is simultaneously deposited on the second gate insulating layer.
10. The method according to claim 7, wherein the second metal layer and the electrode layer are deposited by physical vapor deposition; the first grid electrode insulating layer, the passivation layer and the flat layer are deposited by a chemical vapor deposition method.
CN202010610465.4A 2020-06-29 2020-06-29 TFT backboard structure and manufacturing method Pending CN111739895A (en)

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