CN113363329A - Thin film transistor and preparation method thereof - Google Patents
Thin film transistor and preparation method thereof Download PDFInfo
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- CN113363329A CN113363329A CN202110625610.0A CN202110625610A CN113363329A CN 113363329 A CN113363329 A CN 113363329A CN 202110625610 A CN202110625610 A CN 202110625610A CN 113363329 A CN113363329 A CN 113363329A
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- 239000010409 thin film Substances 0.000 title claims abstract description 91
- 238000002360 preparation method Methods 0.000 title abstract description 9
- 239000010410 layer Substances 0.000 claims abstract description 252
- 239000000758 substrate Substances 0.000 claims abstract description 191
- 239000011229 interlayer Substances 0.000 claims abstract description 52
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 43
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000002041 carbon nanotube Substances 0.000 claims abstract description 16
- 229910021393 carbon nanotube Inorganic materials 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 29
- 238000004519 manufacturing process Methods 0.000 claims description 26
- 229910001404 rare earth metal oxide Inorganic materials 0.000 claims description 19
- 239000010408 film Substances 0.000 claims description 16
- 230000008569 process Effects 0.000 claims description 16
- 238000000059 patterning Methods 0.000 claims description 14
- 239000002131 composite material Substances 0.000 claims description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 4
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 4
- 229910003440 dysprosium oxide Inorganic materials 0.000 claims description 4
- NLQFUUYNQFMIJW-UHFFFAOYSA-N dysprosium(iii) oxide Chemical compound O=[Dy]O[Dy]=O NLQFUUYNQFMIJW-UHFFFAOYSA-N 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- MMKQUGHLEMYQSG-UHFFFAOYSA-N oxygen(2-);praseodymium(3+) Chemical compound [O-2].[O-2].[O-2].[Pr+3].[Pr+3] MMKQUGHLEMYQSG-UHFFFAOYSA-N 0.000 claims description 4
- UZLYXNNZYFBAQO-UHFFFAOYSA-N oxygen(2-);ytterbium(3+) Chemical compound [O-2].[O-2].[O-2].[Yb+3].[Yb+3] UZLYXNNZYFBAQO-UHFFFAOYSA-N 0.000 claims description 4
- 229910003447 praseodymium oxide Inorganic materials 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- 229910003451 terbium oxide Inorganic materials 0.000 claims description 4
- SCRZPWWVSXWCMC-UHFFFAOYSA-N terbium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[Tb+3].[Tb+3] SCRZPWWVSXWCMC-UHFFFAOYSA-N 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 4
- 229910003454 ytterbium oxide Inorganic materials 0.000 claims description 4
- 229940075624 ytterbium oxide Drugs 0.000 claims description 4
- 229910052725 zinc Inorganic materials 0.000 claims description 4
- 239000011701 zinc Substances 0.000 claims description 4
- 229910052726 zirconium Inorganic materials 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 description 22
- 239000002184 metal Substances 0.000 description 22
- 229910052814 silicon oxide Inorganic materials 0.000 description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 238000010586 diagram Methods 0.000 description 10
- 238000009713 electroplating Methods 0.000 description 9
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 8
- UNQHSZOIUSRWHT-UHFFFAOYSA-N aluminum molybdenum Chemical compound [Al].[Mo] UNQHSZOIUSRWHT-UHFFFAOYSA-N 0.000 description 6
- WUUZKBJEUBFVMV-UHFFFAOYSA-N copper molybdenum Chemical compound [Cu].[Mo] WUUZKBJEUBFVMV-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 229910052750 molybdenum Inorganic materials 0.000 description 6
- 239000011733 molybdenum Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000003475 lamination Methods 0.000 description 4
- 239000002109 single walled nanotube Substances 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 150000001879 copper Chemical class 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 239000004611 light stabiliser Substances 0.000 description 2
- 150000002751 molybdenum Chemical class 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
Abstract
The invention discloses a thin film transistor and a preparation method of the thin film transistor. The thin film transistor includes: a substrate; the source electrode and the drain electrode are positioned on the surface of the substrate; an interlayer insulating layer covering the source and drain electrodes; the active layer is positioned on the surface of one side, away from the source electrode and the drain electrode, of the interlayer insulating layer and comprises a source region, a drain region and a channel region positioned between the source region and the drain region, the projected area of the source electrode on the substrate covers the projected area of the channel region on the substrate, or the projected area of the drain electrode on the substrate covers the projected area of the channel region on the substrate, wherein the active layer comprises a metal oxide semiconductor material or a carbon nano tube; the grid electrode insulating layer and the grid electrode are arranged on the surface of one side, away from the interlayer insulating layer, of the active layer in a laminated mode, wherein the grid electrode insulating layer is located between the active layer and the grid electrode. According to the technical scheme provided by the embodiment of the invention, the thin film transistor with good saturation region characteristics and low preparation cost is realized.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a thin film transistor and a preparation method of the thin film transistor.
Background
The thin film transistor is used as a key device of a liquid crystal display and an organic display, and plays an important role in the working performance of a display device. The common thin film transistors are mainly amorphous silicon thin film transistors, polysilicon thin film transistors, organic thin film transistors and metal oxide thin film transistors.
The metal oxide thin film transistor has excellent piezoelectric, photoelectric, gas-sensitive and pressure-sensitive performances and the like, so that the metal oxide thin film transistor has wide development prospect in the field of semiconductors. At present, the structures mainly used by the metal oxide thin film transistor are an etching barrier layer structure, a back channel etching structure and a top gate structure.
The conventional etching barrier layer structure is difficult to realize small size, and parasitic capacitance is large, so that the conventional etching barrier layer structure is difficult to be applied to high-precision display screens and large-size display screens. In a back channel etching structure, the metal oxide semiconductor material is sensitive and has poor etching solution resistance, so that the device performance with high mobility and high stability is difficult to obtain.
However, the top gate structure can only be applied to the fabrication of low-temperature polysilicon thin film transistor devices, and is not widely used in metal oxide thin film transistors due to the complex process and the high number of times of photolithography. The most important reason is that the saturation performance of the output characteristics of the metal oxide thin film transistor is poor.
Fig. 1 is a graph showing the output characteristics of a metal oxide thin film transistor having a top gate structure according to the related art. Fig. 2 is a graph showing the output characteristics of a metal oxide thin film transistor having a dual gate structure according to the prior art. As shown in fig. 1, in the output characteristic of the metal oxide thin film transistor with the top gate structure, when the voltage of the source and drain electrodes is continuously increased, the source and drain current is slowly increased. As shown in fig. 2, on the basis of the top-gate structure device, the output characteristic of the metal oxide thin film transistor with the double-gate structure is that the source-drain current is in the saturation region, which shows good saturation characteristic. The good saturation characteristic can ensure better uniformity of the display screen during working. However, the metal oxide thin film transistor with the double-gate structure needs to add two additional photolithography processes, which increases the cost. Note that the width-to-length ratios of the tfts in fig. 1 and 2 are the same, and the output characteristic curves are plotted at different gate voltages, wherein the gate voltages include 2.1V, 4.1V, 6.1V, 8.1V, and 10.1V.
Therefore, a thin film transistor with good saturation region characteristics and low manufacturing cost and a method for manufacturing the thin film transistor are needed.
Disclosure of Invention
In view of this, embodiments of the present invention provide a thin film transistor and a method for manufacturing the thin film transistor, so as to implement a thin film transistor with good saturation region characteristics and low manufacturing cost.
An embodiment of the present invention provides a thin film transistor, including:
a substrate;
the source electrode and the drain electrode are positioned on the surface of the substrate;
the interlayer insulating layer covers the source electrode and the drain electrode, is positioned on the surface of one side, away from the substrate, of the source electrode and the drain electrode, and is provided with a first through hole and a second through hole, the first through hole exposes part of the source electrode, and the second through hole exposes part of the drain electrode;
the active layer is positioned on the surface of one side, away from the source electrode and the drain electrode, of the interlayer insulating layer and comprises a source region, a drain region and a channel region positioned between the source region and the drain region, the source region is connected with the source electrode through the first through hole, the drain region is connected with the drain electrode through the second through hole, the projected area of the source electrode on the substrate covers the projected area of the channel region on the substrate, or the projected area of the drain electrode on the substrate covers the projected area of the channel region on the substrate, wherein the active layer comprises a metal oxide semiconductor material or a carbon nano tube;
the grid electrode insulating layer and the grid electrode are arranged on the surface of one side, away from the interlayer insulating layer, of the active layer in a stacking mode, wherein the grid electrode insulating layer is located between the active layer and the grid electrode.
Optionally, a projected area of the source electrode on the substrate is larger than or smaller than a projected area of the drain electrode on the substrate.
Optionally, a projected area of the source on the substrate is larger than a projected area of the drain on the substrate, and the projected area of the source on the substrate covers a projected area of the channel region on the substrate.
Optionally, a projected area of the drain on the substrate is larger than a projected area of the source on the substrate, and the projected area of the drain on the substrate covers the projected area of the channel region on the substrate.
Optionally, a projection of the gate on the substrate overlaps a projection of the gate insulating layer on the substrate.
Optionally, a projection of the gate on the substrate overlaps a projection of the channel region on the substrate, the conductivity of the source region is greater than the conductivity of the channel region, and the conductivity of the drain is greater than the conductivity of the channel region.
Optionally, the active layer comprises a composite oxide (MO) composed of an oxide MO corresponding to at least one of indium, zinc, gallium, tin, zirconium, and tantalum, and a rare earth oxide ROx(RO)yFilm of wherein，0<x<1, 0.0001 and y are less than or equal to 0.2, x + y is 1, and the rare earth oxide comprises at least one of praseodymium oxide, terbium oxide, dysprosium oxide and ytterbium oxide.
The embodiment of the invention also provides a preparation method of the thin film transistor, which comprises the following steps:
providing a substrate;
forming a source electrode and a drain electrode on the surface of the substrate;
forming an interlayer insulating layer on the surface of one side of the source electrode and the drain electrode, which is far away from the substrate, wherein the interlayer insulating layer covers the source electrode and the drain electrode, the interlayer insulating layer is provided with a first via hole and a second via hole, the first via hole exposes part of the source electrode, and the second via hole exposes part of the drain electrode;
forming an active layer on the surface of one side, away from the source electrode and the drain electrode, of the interlayer insulating layer, wherein the active layer comprises a source region, a drain region and a channel region located between the source region and the drain region, the source region is connected with the source electrode through the first via hole, the drain region is connected with the drain electrode through the second via hole, the projected area of the source electrode on the substrate covers the projected area of the channel region on the substrate, or the projected area of the drain electrode on the substrate covers the projected area of the channel region on the substrate, and the active layer comprises a metal oxide semiconductor material or a carbon nanotube;
and forming a gate insulating layer and a gate on the surface of one side of the channel region, which is far away from the interlayer insulating layer, wherein the gate insulating layer and the gate are stacked on the surface of one side of the active layer, which is far away from the interlayer insulating layer, and the gate insulating layer is positioned between the active layer and the gate.
Optionally, the forming a gate insulating layer and a gate on a surface of the channel region on a side away from the interlayer insulating layer includes:
forming an insulating layer on the surface of one side, away from the interlayer insulating layer, of the channel region;
forming a conductive layer on the surface of the insulating layer, which is far away from the active layer;
patterning the conducting layer to form the grid electrode, wherein the projection of the grid electrode on the substrate covers the projection of the channel region on the substrate;
and patterning the insulating layer by using the grid as a mask through a self-alignment process to form the grid insulating layer, wherein the projection of the grid on the substrate is overlapped with the projection of the grid insulating layer on the substrate.
Optionally, the patterning the conductive layer to form the gate includes:
carrying out patterning processing on the conducting layer to form a grid electrode which is overlapped with the projection of the substrate and the projection of the channel region on the substrate;
after a gate insulating layer and a gate are formed on the surface of the channel region on the side away from the interlayer insulating layer, the method further comprises the following steps:
and performing high conductivity treatment on the source region and the drain region by taking the gate electrode and the gate insulating layer as masks, wherein the conductivity of the source region is greater than that of the channel region, and the conductivity of the drain electrode is greater than that of the channel region.
In the technical solution provided by this embodiment, the active layer includes a metal oxide semiconductor material or a carbon nanotube, and the thin film transistor can exhibit excellent device performance. The projection area of the source electrode on the substrate covers the projection area of the channel region on the substrate, or the projection area of the drain electrode on the substrate covers the projection area of the channel region on the substrate, the source electrode or the drain electrode can reflect light rays of one side surface of the substrate, which is far away from the active layer, so that photo-generated carriers are prevented from being generated in the channel region under the action of the light rays of one side surface of the substrate, which is far away from the active layer, and the thin film transistor is enabled to show good output characteristics in the saturation region. Compared with the metal oxide thin film transistor with the double-gate structure, the technical scheme provided by the embodiment reduces the number of masks required for preparing the gate and saves the manufacturing cost of the metal oxide thin film transistor.
Drawings
FIG. 1 is a graph showing the output characteristics of a top-gate metal oxide thin film transistor according to the prior art;
FIG. 2 is a graph showing the output characteristics of a dual gate MOS TFT according to the prior art;
fig. 3 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention;
fig. 6 is a schematic flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present invention;
FIG. 7 is a flow chart of a method of preparation comprising step 150 of FIG. 6;
fig. 8-17 are cross-sectional views corresponding to steps of a method for fabricating a thin film transistor according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 3 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention. Fig. 4 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention. Referring to fig. 3 and 4, the thin film transistor includes: a substrate 10; a source electrode 20 and a drain electrode 30, wherein the source electrode 20 and the drain electrode 30 are positioned on the surface of the substrate 10; the interlayer insulating layer 40 covers the source electrode 20 and the drain electrode 30, the interlayer insulating layer 40 is positioned on the surface of one side, away from the substrate 10, of the source electrode 20 and the drain electrode 30, the interlayer insulating layer 40 is provided with a first through hole 41 and a second through hole 42, the first through hole 41 exposes part of the source electrode 20, and the second through hole 42 exposes part of the drain electrode 30; an active layer 50, the active layer 50 being located on a surface of the interlayer insulating layer 40 on a side away from the source electrode 20 and the drain electrode 30, the active layer 50 including a source region 51, a drain region 53 and a channel region 52 located between the source region 51 and the drain region 53, the source region 51 being connected to the source electrode 20 through a first via 41, the drain region 53 being connected to the drain electrode 30 through a second via 42, a projected area of the source electrode 20 on the substrate 10 covering a projected area of the channel region 52 on the substrate 10 or a projected area of the drain electrode 30 on the substrate 10 covering a projected area of the channel region 52 on the substrate 10, wherein the active layer 50 includes a metal oxide semiconductor material or a carbon nanotube; and a gate insulating layer 60 and a gate electrode 70, wherein the gate insulating layer 60 and the gate electrode 70 are stacked on a surface of the active layer 50 on a side facing away from the interlayer insulating layer 40, and the gate insulating layer 60 is located between the active layer 50 and the gate electrode 70.
The active layer 50 includes a metal oxide semiconductor material, and the thin film transistor has excellent piezoelectric, photoelectric, gas-sensitive, and pressure-sensitive properties.
The active layer 50 includes carbon nanotubes. Illustratively, the carbon nanotubes have a diameter greater than or equal to 1.45 nanometers and less than or equal to 1.65 nanometers. The length of the carbon nanotube is greater than or equal to 0.7 nm and less than or equal to 1.3 nm. The thickness of the carbon nanotube is greater than or equal to 5 nanometers and less than or equal to 15 nanometers. Optionally, the carbon nanotubes in this embodiment comprise single-walled carbon nanotubes (SWCNTs). Due to its excellent charge transport properties, good solution processability, high flexibility, excellent mechanical properties and high thermal conductivity, excellent mechanical stability and chemical stability, single-walled carbon nanotubes have been widely used in electronic and optoelectronic devices, such as transparent conductive membrane electrodes, thin film transistors, logic circuits, flexible wearable electronic devices, chemical and biological sensors, supercapacitors, solar cells, etc. The thin film transistor prepared by taking the single-walled carbon nanotube as an active layer material has the advantages of excellent electrical property, smaller characteristic size, good stability, quicker heat dissipation and higher operating frequency, and shows excellent device performance and great application development potential.
In the schematic structural diagram of the thin film transistor shown in fig. 3, a projected area of the source 20 on the substrate 10 covers a projected area of the channel region 52 on the substrate 10. Fig. 4 shows a schematic structural diagram of the thin film transistor, in which a projected area of the drain 30 on the substrate 10 covers a projected area of the channel region 52 on the substrate 10.
In the solution provided in this embodiment, the active layer 50 includes a metal oxide semiconductor material or a carbon nanotube, and the thin film transistor can exhibit excellent device performance. The projected area of the source electrode 20 on the substrate 10 covers the projected area of the channel region 52 on the substrate 10 or the projected area of the drain electrode 30 on the substrate 10 covers the projected area of the channel region 52 on the substrate 10, and the source electrode 20 or the drain electrode 30 can reflect light rays on the surface of the substrate 10 on the side away from the active layer 50, so that photo-generated carriers are prevented from being generated inside the channel region 52 under the action of the light rays on the surface of the substrate 10 on the side away from the active layer 50, and the thin film transistor is enabled to show good output characteristics in a saturation region. Compared with the metal oxide thin film transistor with the double-gate structure, the technical scheme provided by the embodiment reduces the number of masks required for preparing the gate and saves the manufacturing cost of the metal oxide thin film transistor.
Fig. 5 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention. Optionally, on the basis of the above technical solution, referring to fig. 5, the thin film transistor further includes: the planarization layer 80, the planarization layer 80 covering the active layer 50, the gate insulating layer 60 and the gate electrode 70, serves to protect the active layer 50, the gate insulating layer 60 and the gate electrode 70 from external force loss, and provides a flat surface for a subsequently formed display unit. Wherein the anode 90 of the display cell is electrically connected to the source electrode 20 through the third via 81. The thin film transistor provided by the embodiment is used for providing a driving current for the display unit in a saturation state.
Optionally, on the basis of the above technical solution, a projected area of the source electrode 20 on the substrate 10 is larger than or smaller than a projected area of the drain electrode 30 on the substrate 10.
In the structural schematic diagram of the thin film transistor shown in fig. 3, the projected area of the source electrode 20 on the substrate 10 is larger than the projected area of the drain electrode 30 on the substrate 10. Fig. 4 shows a schematic structural diagram of the thin film transistor, in which a projected area of the source electrode 20 on the substrate 10 is smaller than a projected area of the drain electrode 30 on the substrate 10.
Specifically, according to the technical scheme, on the basis that the projection area of the source electrode 20 on the substrate 10 covers the projection area of the channel region 52 on the substrate 10 or the projection area of the drain electrode 30 on the substrate 10 covers the projection area of the channel region 52 on the substrate 10, the area of the electrode which does not need to reflect light rays on the surface of the substrate 10 away from the active layer 50 is set to be smaller, and the manufacturing cost of the thin film transistor can be further saved.
Optionally, on the basis of the above technical solution, referring to fig. 3, a projected area of the source 20 on the substrate 10 is larger than a projected area of the drain 30 on the substrate 10, and the projected area of the source 20 on the substrate 10 covers a projected area of the channel region 52 on the substrate 10.
Specifically, the projected area of the source 20 on the substrate 10 covers the projected area of the channel region 52 on the substrate 10, so that the area of the drain 30 that does not need to reflect the light on the surface of the substrate 10 away from the active layer 50 can be set smaller, and the manufacturing cost of the thin film transistor can be further saved.
Optionally, on the basis of the above technical solution, referring to fig. 4, a projected area of the drain 30 on the substrate 10 is larger than a projected area of the source 20 on the substrate 10, and the projected area of the drain 30 on the substrate 10 covers a projected area of the channel region 52 on the substrate 10.
Specifically, the projected area of the drain 30 on the substrate 10 covers the projected area of the channel region 52 on the substrate 10, so that the area of the source 20 that does not need to reflect the light on the surface of the substrate 10 away from the active layer 50 can be set smaller, and the manufacturing cost of the thin film transistor can be further saved.
In order to further save the manufacturing cost of the thin film transistor, the embodiment of the invention also provides the following technical scheme:
alternatively, on the basis of the above technical solution, referring to fig. 3 to 5, the projection of the gate 70 on the substrate 10 overlaps the projection of the gate insulating layer 60 on the substrate 10.
Specifically, the projection of the gate 70 on the substrate 10 overlaps the projection of the gate insulating layer 60 on the substrate 10, and after the gate 70 is prepared, the gate 70 can be used as a mask through a self-alignment process of the gate 70 to pattern a film layer where the gate insulating layer 60 is located, so as to obtain the gate insulating layer 60, thereby saving the number of masks and further saving the manufacturing cost of the thin film transistor.
Alternatively, on the basis of the above technical solution, referring to fig. 3 to 5, the projection of the gate 70 on the substrate 10 overlaps the projection of the channel region 52 on the substrate 10, the conductivity of the source region 51 is greater than the conductivity of the channel region 52, and the conductivity of the drain 53 is greater than the conductivity of the channel region 52.
Specifically, the projection of the gate 70 on the substrate 10 overlaps the projection of the channel region 52 on the substrate 10, after the gate 70 and the gate insulating layer 60 are prepared, the gate 70 is used as a mask to perform a high conductivity treatment on the source region 51 of the active layer 50 through a self-alignment process of the gate 70 so that the conductivity of the source region 51 is greater than that of the channel region 52, and the drain region 53 of the active layer 50 so that the conductivity of the drain 53 is greater than that of the channel region 52, so that a good ohmic contact is formed between the source region 51 and the source 20 and a good ohmic contact is formed between the drain region 53 and the drain 30 on the basis of saving the number of masks and reducing the manufacturing cost of the thin film transistor.
Optionally, on the basis of the above technical solution, the active layer 50 includes a composite oxide (MO) composed of an oxide MO corresponding to at least one of indium, zinc, gallium, tin, zirconium, and tantalum and a rare earth oxide ROx(RO)yFilm of, wherein 0<x<Y is more than or equal to 1, 0.0001 and less than or equal to 0.2, x + y is 1, and the rare earth oxide comprises at least one of praseodymium oxide, terbium oxide, dysprosium oxide and ytterbium oxide.
Specifically, the active layer 50 may be a composite Oxide (MO) formed by doping a small amount of Rare-earth Oxide (RO) into a Metal Oxide (MO) semiconductor thin filmx(RO)yFilm of, wherein 0<x<1, 0.0001. ltoreq. y.ltoreq.0.2, and x + y is 1. The rare earth oxide can be used as a light stabilizer, so that the light stability of the active layer 50 is enhanced, and the uniformity and stability of the display screen are further enhanced.
The embodiment of the invention also provides a preparation method of the thin film transistor. Fig. 6 is a schematic flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present invention. Fig. 8-17 are cross-sectional views corresponding to steps of a method for fabricating a thin film transistor according to an embodiment of the invention. Referring to fig. 6, the method for manufacturing the thin film transistor includes the steps of:
Referring to fig. 8, a substrate 10 is provided, and illustratively, the substrate 10 may be a wafer.
Referring to fig. 9, the source electrode 20 and the drain electrode 30 may be formed on the surface of the substrate 10 through an electroplating process. Specifically, first, an entire seed layer covering the substrate 10 is formed on the surface of the substrate 10. And then forming a patterned electroplating film layer on the surface of the seed layer, and continuously forming an electroplating metal layer with a preset thickness on the surface of the patterned electroplating mask layer through an electroplating process. And then removing the electroplating film layer, and carrying out a patterning process on the seed layer and the electroplating metal layer to obtain the source electrode 20 and the drain electrode 30. Illustratively, the seed layer may be a stack of metallic molybdenum and metallic copper. Wherein the thickness of the film layer of the metal molybdenum is more than 30 nanometers, and the thickness of the film layer of the metal copper is about 300 nanometers. The electroplated metal layer may be an electroplated copper layer, wherein the electroplated copper layer has a thickness greater than or equal to 300 nanometers and less than or equal to 1000 nanometers. The plating film layer may include SU-8, silicon nitride (SiNx), and silicon oxide (SiO)2) Any one of them. Wherein SU-8 is a negative, epoxy resin, near ultraviolet photoresist. The thickness of the electroplating film layer is greater than or equal to 5 micrometers and less than or equal to 25 micrometers.
For example, a metal layer may be formed on the surface of the substrate 10 by a magnetron sputtering process, and then the metal layer may be patterned by a first mask to form the source electrode 20 and the drain electrode 30. Optionally, taking fig. 3 and fig. 4 as an example for explanation, a projected area of the source 20 on the substrate 10 is greater than or less than a projected area of the drain 30 on the substrate 10, and on the basis that the projected area of the source 20 on the substrate 10 covers the projected area of the channel region 52 on the substrate 10 or the projected area of the drain 30 on the substrate 10 covers the projected area of the channel region 52 on the substrate 10, an area of an electrode that does not need to reflect light on a surface of the substrate 10 away from the active layer 50 is set to be smaller, so that the manufacturing cost of the thin film transistor can be further saved. Optionally, on the basis of the above technical solution, a projected area of the source 20 on the substrate 10 is larger than a projected area of the drain 30 on the substrate 10, and the projected area of the source 20 on the substrate 10 covers a projected area of the channel region 52 on the substrate 10. Specifically, the projected area of the source 20 on the substrate 10 covers the projected area of the channel region 52 on the substrate 10, so that the area of the drain 30 that does not need to reflect the light on the surface of the substrate 10 away from the active layer 50 can be set smaller, and the manufacturing cost of the thin film transistor can be further saved. Optionally, on the basis of the above technical solution, a projected area of the drain 30 on the substrate 10 is larger than a projected area of the source 20 on the substrate 10, and the projected area of the drain 30 on the substrate 10 covers a projected area of the channel region 52 on the substrate 10. Specifically, the projected area of the drain 30 on the substrate 10 covers the projected area of the channel region 52 on the substrate 10, so that the area of the source 20 that does not need to reflect the light on the surface of the substrate 10 away from the active layer 50 can be set smaller, and the manufacturing cost of the thin film transistor can be further saved.
Alternatively, the source electrode 20 and the drain electrode 30 may include a stack of at least one of metal molybdenum, aluminum molybdenum metal stack, copper molybdenum metal stack, and metal aluminum. Illustratively, the thickness of the molybdenum metal is about
The thickness of the aluminum in the aluminum-molybdenum metal lamination is about
The thickness of the molybdenum in the aluminum-molybdenum metal lamination layer is about
The thickness of the copper-molybdenum metal laminated copper is about
The thickness of the copper-molybdenum metal laminated molybdenum is about
And step 130, forming an interlayer insulating layer on the surface of the source electrode and the drain electrode on the side away from the substrate, wherein the interlayer insulating layer covers the source electrode and the drain electrode, the interlayer insulating layer is provided with a first via hole and a second via hole, the first via hole exposes part of the source electrode, and the second via hole exposes part of the drain electrode.
Referring to fig. 10, an interlayer insulating layer 40 is formed on the surface of the source electrode 20 and the drain electrode 30 facing away from the substrate 10, wherein the interlayer insulating layer 40 covers the source electrode 20 and the drain electrode 30, the interlayer insulating layer 40 is provided with a first via hole 41 and a second via hole 42, the first via hole 41 exposes a portion of the source electrode 20, and the second via hole 42 exposes a portion of the drain electrode 30. The interlayer insulating layer 40 is patterned by a second mask to form a first via hole 41 and a second via hole 42. Optionally, the interlayer insulating layer 40 may be patterned by a second mask to form the third via 81 at the same time as the first via 41 and the second via 42.
Optionally, the interlayer insulating layer 40 includes at least one of silicon nitride, aluminum nitride, and silicon oxide. Illustratively, the interlayer insulating layer 40 includes a stack of silicon nitride (SiNx) and silicon oxide (SiO), silicon oxide (SiO)2) And alumina (Al)2O3) And silicon oxide (SiO)2) The laminate of (1). Wherein, in the laminated layer of silicon nitride (SiNx) and silicon oxide (SiO), the thickness of the silicon nitride (SiNx) is about
The thickness of silicon oxide (SiO) is about
Silicon oxide (SiO)2) Is about a
Alumina (Al)2O3) And silicon oxide (SiO)2) In the stack of (A) and (B) aluminum oxide (Al)2O3) Is about a
Silicon oxide (SiO)2) Is about a
And 140, forming an active layer on the surface of one side, away from the source electrode and the drain electrode, of the interlayer insulating layer, wherein the active layer comprises a source region, a drain region and a channel region located between the source region and the drain region, the source region is connected with the source electrode through a first via hole, the drain region is connected with the drain electrode through a second via hole, the projected area of the source electrode on the substrate covers the projected area of the channel region on the substrate or the projected area of the drain electrode on the substrate covers the projected area of the channel region on the substrate, and the active layer comprises a metal oxide semiconductor material or a carbon nanotube.
Referring to fig. 11, an active layer 50 is formed on a surface of the interlayer insulating layer 40 on a side facing away from the source electrode 20 and the drain electrode 30, wherein the active layer 50 includes a source region 51, a drain region 53 and a channel region 52 located between the source region 51 and the drain region 53, the source region 51 is connected to the source electrode 20 through a first via 41, the drain region 53 is connected to the drain electrode 30 through a second via 42, a projected area of the source electrode 20 on the substrate 10 overlaps a projected area of the channel region 52 on the substrate 10 or a projected area of the drain electrode 30 on the substrate 10 overlaps a projected area of the channel region 52 on the substrate 10, and wherein the active layer 50 includes a metal oxide semiconductor material or a carbon nanotube.
Note that, the film layer where the active layer 50 is located is patterned by a third mask to form the active layer 50.
Optionally, on the basis of the above technical solution, the active layer 50 includes a composite oxide (MO) composed of an oxide MO corresponding to at least one of indium, zinc, gallium, tin, zirconium, and tantalum and a rare earth oxide ROx(RO)yFilm of, wherein 0<x<Y is more than or equal to 1, 0.0001 and less than or equal to 0.2, x + y is 1, and the rare earth oxide comprises at least one of praseodymium oxide, terbium oxide, dysprosium oxide and ytterbium oxide.
Specifically, the active layer 50 may be a composite Oxide (MO) formed by doping a small amount of Rare-earth Oxide (RO) into a Metal Oxide (MO) semiconductor thin filmx(RO)yFilm of, wherein 0<x<1, 0.0001. ltoreq. y.ltoreq.0.2, and x + y is 1. The rare earth oxide can be used as a light stabilizer to reinforce the active layer50, thereby enhancing the uniformity and stability of the display screen.
And 150, forming a gate insulating layer and a gate on the surface of the channel region on the side away from the interlayer insulating layer, wherein the gate insulating layer and the gate are stacked on the surface of the active layer on the side away from the interlayer insulating layer, and the gate insulating layer is positioned between the active layer and the gate.
Referring to fig. 15, a gate insulating layer 60 and a gate electrode 70 are formed on a surface of the channel region 52 on a side facing away from the interlayer insulating layer 40, wherein the gate insulating layer 60 and the gate electrode 70 are stacked on a surface of the active layer 50 on a side facing away from the interlayer insulating layer 40, and the gate insulating layer 60 is located between the active layer 50 and the gate electrode 70.
Optionally, on the basis of the above technical solution, the gate insulating layer 60 includes a stack of a first layer of silicon oxide, aluminum oxide, and a second layer of silicon oxide. Wherein the first layer of silicon oxide has a thickness of about 1500A and the first layer of aluminum oxide has a thickness of about 1500A
The thickness of the second oxide pair is about
Optionally, the material of the gate 70 includes at least one of metal molybdenum, aluminum molybdenum metal stack, and copper molybdenum metal stack. Optionally, the thickness of the molybdenum metal is about
The thickness of the aluminum in the aluminum-molybdenum metal lamination is about
The thickness of the molybdenum in the aluminum-molybdenum metal lamination layer is about
The thickness of the copper-molybdenum metal laminated copper is about
The thickness of the copper-molybdenum metal laminated molybdenum is about
In the solution provided in this embodiment, the active layer 50 includes a metal oxide semiconductor material or a carbon nanotube, and the thin film transistor can exhibit excellent device performance. The projected area of the source electrode 20 on the substrate 10 covers the projected area of the channel region 52 on the substrate 10 or the projected area of the drain electrode 30 on the substrate 10 covers the projected area of the channel region 52 on the substrate 10, and the source electrode 20 or the drain electrode 30 can reflect light rays on the surface of the substrate 10 on the side away from the active layer 50, so that photo-generated carriers are prevented from being generated inside the channel region 52 under the action of the light rays on the surface of the substrate 10 on the side away from the active layer 50, and the thin film transistor is enabled to show good output characteristics in a saturation region. Compared with the metal oxide thin film transistor with the double-gate structure, the technical scheme provided by the embodiment reduces the number of masks required for preparing the gate and saves the manufacturing cost of the metal oxide thin film transistor.
The electrode layer with a relatively large thickness or a relatively large area is formed by an electroplating process, so that the forming efficiency is high, and the preparation cost is low.
The methods of preparing the gate insulating layer 60 and the gate electrode 70 will be described in detail below. Fig. 7 is a flow chart of the manufacturing method involved in step 150 of fig. 6.
Optionally, on the basis of the foregoing technical solution, referring to fig. 7, the step 150 of forming a gate insulating layer and a gate on a surface of the channel region on a side away from the interlayer insulating layer includes:
Referring to fig. 12, an insulating layer 61 is formed on a surface of the channel region 52 on a side facing away from the interlayer insulating layer 40.
Referring to fig. 13, a conductive layer 71 is formed on a surface of the insulating layer 61 facing away from the active layer 50.
And 1503, performing patterning processing on the conductive layer to form a gate, wherein the projection of the gate on the substrate covers the projection of the channel region on the substrate.
Referring to fig. 14, the conductive layer 71 is patterned to form a gate 70, wherein a projection of the gate 70 on the substrate 10 overlaps a projection of the channel region 52 on the substrate 10. The conductive layer 71 is patterned by a fourth mask to form the gate electrode 70.
And 1504, with the grid as a mask, carrying out patterning processing on the insulating layer through a self-alignment process to form a grid insulating layer, wherein the projection of the grid on the substrate is overlapped with the projection of the grid insulating layer on the substrate.
Referring to fig. 15, the insulating layer 61 is patterned by a self-aligned process using the gate electrode 70 as a mask to form a gate insulating layer 60, wherein a projection of the gate electrode 70 on the substrate 10 overlaps a projection of the gate insulating layer 60 on the substrate 10.
Specifically, the projection of the gate 70 on the substrate 10 overlaps the projection of the gate insulating layer 60 on the substrate 10, and after the gate 70 is prepared, the gate 70 can be used as a mask through a self-alignment process of the gate 70 to pattern a film layer where the gate insulating layer 60 is located, so as to obtain the gate insulating layer 60, thereby saving the number of masks and further saving the manufacturing cost of the thin film transistor.
Optionally, on the basis of the foregoing technical solution, the step 1503 of performing patterning processing on the conductive layer to form the gate includes:
and patterning the conductive layer to form a gate electrode which is overlapped on the projection of the substrate and the projection of the channel region on the substrate.
Referring to fig. 14, the conductive layer 71 is patterned to form a gate electrode 70 overlapping a projection of the substrate 10 and a projection of the channel region 52 on the substrate 10.
Optionally, on the basis of the foregoing technical solution, the step 150 further includes, after forming the gate insulating layer and the gate on the surface of the channel region on the side away from the interlayer insulating layer:
and taking the grid electrode and the grid electrode insulating layer as masks, and carrying out high conductivity treatment on the source region and the drain region, wherein the conductivity of the source region is greater than that of the channel region, and the conductivity of the drain electrode is greater than that of the channel region.
Referring to fig. 16, the gate electrode 70 and the gate insulating layer 60 are used as masks to perform a high conductivity process on the source region 51 and the drain region 53, wherein the conductivity of the source region 51 is greater than that of the channel region 52, and the conductivity of the drain region 53 is greater than that of the channel region 52.
Specifically, the projection of the gate 70 on the substrate 10 overlaps the projection of the channel region 52 on the substrate 10, after the gate 70 and the gate insulating layer 60 are prepared, the gate 70 is used as a mask to perform a high conductivity treatment on the source region 51 of the active layer 50 through a self-alignment process of the gate 70 so that the conductivity of the source region 51 is greater than that of the channel region 52, and the drain region 53 of the active layer 50 so that the conductivity of the drain 53 is greater than that of the channel region 52, so that a good ohmic contact is formed between the source region 51 and the source 20 and a good ohmic contact is formed between the drain region 53 and the drain 30 on the basis of saving the number of masks and reducing the manufacturing cost of the thin film transistor.
Optionally, on the basis of the above technical solution, after performing the high conductivity processing on the source region 51 and the drain region 53 by using the gate electrode 70 and the gate insulating layer 60 as masks, the method further includes:
referring to fig. 17, a planarization layer 80 and an anode 90 are formed. The planarization layer 80 covers the active layer 50, the gate insulating layer 60, and the gate electrode 70, protects the active layer 50, the gate insulating layer 60, and the gate electrode 70 from external force, and provides a flat surface for a display unit to be formed later. The anode 90 of the display unit is electrically connected to the source electrode 20 through the third via hole 81. The thin film transistor provided by the embodiment is used for providing a driving current for the display unit in a saturation state.
Optionally, passivation layer 80 comprises a mixture of silicon oxide and organic material, wherein the silicon oxide has a thickness of about
The thickness of the organic is about 1.2 um. It should be noted that the passivation layer 80 is provided with a third via 81 therein, which can be formed by patterning through a fifth mask. Optionally, the anode 90 comprises an ITO conductive film,At least one of metallic nickel, metallic copper and metallic Au. Note that the patterned anode 90 may be formed by a sixth mask. Wherein the thickness of the anode 90 is greater than or equal to
And is less than or equal to
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A thin film transistor, comprising:
a substrate;
the source electrode and the drain electrode are positioned on the surface of the substrate;
the interlayer insulating layer covers the source electrode and the drain electrode, is positioned on the surface of one side, away from the substrate, of the source electrode and the drain electrode, and is provided with a first through hole and a second through hole, the first through hole exposes part of the source electrode, and the second through hole exposes part of the drain electrode;
the active layer is positioned on the surface of one side, away from the source electrode and the drain electrode, of the interlayer insulating layer and comprises a source region, a drain region and a channel region positioned between the source region and the drain region, the source region is connected with the source electrode through the first through hole, the drain region is connected with the drain electrode through the second through hole, the projected area of the source electrode on the substrate covers the projected area of the channel region on the substrate, or the projected area of the drain electrode on the substrate covers the projected area of the channel region on the substrate, wherein the active layer comprises a metal oxide semiconductor material or a carbon nano tube;
the grid electrode insulating layer and the grid electrode are arranged on the surface of one side, away from the interlayer insulating layer, of the active layer in a stacking mode, wherein the grid electrode insulating layer is located between the active layer and the grid electrode.
2. The thin film transistor according to claim 1, wherein a projected area of the source electrode on the substrate is larger or smaller than a projected area of the drain electrode on the substrate.
3. The thin film transistor according to claim 1, wherein a projected area of the source electrode on the substrate is larger than a projected area of the drain electrode on the substrate, and the projected area of the source electrode on the substrate covers a projected area of the channel region on the substrate.
4. The thin film transistor according to claim 1, wherein a projected area of the drain electrode on the substrate is larger than a projected area of the source electrode on the substrate, and the projected area of the drain electrode on the substrate covers a projected area of the channel region on the substrate.
5. The thin film transistor of claim 1, wherein a projection of the gate electrode on the substrate overlaps a projection of the gate insulating layer on the substrate.
6. The thin film transistor of claim 5, wherein a projection of the gate electrode on the substrate overlaps a projection of the channel region on the substrate, wherein a conductivity of the source region is greater than a conductivity of the channel region, and wherein a conductivity of the drain electrode is greater than a conductivity of the channel region.
7. The thin film transistor of claim 1, wherein the active layer comprises a composite oxide (MO) of an oxide MO corresponding to at least one of indium, zinc, gallium, tin, zirconium, and tantalum, and a rare earth oxide ROx(RO)yFilm of, wherein 0<x<1, 0.0001 and y are less than or equal to 0.2, x + y is 1, and the rare earth oxide comprises at least one of praseodymium oxide, terbium oxide, dysprosium oxide and ytterbium oxide.
8. A method for manufacturing a thin film transistor includes:
providing a substrate;
forming a source electrode and a drain electrode on the surface of the substrate;
forming an interlayer insulating layer on the surface of one side of the source electrode and the drain electrode, which is far away from the substrate, wherein the interlayer insulating layer covers the source electrode and the drain electrode, the interlayer insulating layer is provided with a first via hole and a second via hole, the first via hole exposes part of the source electrode, and the second via hole exposes part of the drain electrode;
forming an active layer on the surface of one side, away from the source electrode and the drain electrode, of the interlayer insulating layer, wherein the active layer comprises a source region, a drain region and a channel region located between the source region and the drain region, the source region is connected with the source electrode through the first via hole, the drain region is connected with the drain electrode through the second via hole, the projected area of the source electrode on the substrate covers the projected area of the channel region on the substrate, or the projected area of the drain electrode on the substrate covers the projected area of the channel region on the substrate, and the active layer comprises a metal oxide semiconductor material or a carbon nanotube;
and forming a gate insulating layer and a gate on the surface of one side of the channel region, which is far away from the interlayer insulating layer, wherein the gate insulating layer and the gate are stacked on the surface of one side of the active layer, which is far away from the interlayer insulating layer, and the gate insulating layer is positioned between the active layer and the gate.
9. The method of manufacturing a thin film transistor according to claim 8, wherein forming a gate insulating layer and a gate electrode on a surface of the channel region on a side facing away from the interlayer insulating layer comprises:
forming an insulating layer on the surface of one side, away from the interlayer insulating layer, of the channel region;
forming a conductive layer on the surface of the insulating layer, which is far away from the active layer;
patterning the conducting layer to form the grid electrode, wherein the projection of the grid electrode on the substrate covers the projection of the channel region on the substrate;
and patterning the insulating layer by using the grid as a mask through a self-alignment process to form the grid insulating layer, wherein the projection of the grid on the substrate is overlapped with the projection of the grid insulating layer on the substrate.
10. The method of manufacturing a thin film transistor according to claim 9, wherein the patterning the conductive layer to form the gate electrode includes:
carrying out patterning processing on the conducting layer to form a grid electrode which is overlapped with the projection of the substrate and the projection of the channel region on the substrate;
after a gate insulating layer and a gate are formed on the surface of the channel region on the side away from the interlayer insulating layer, the method further comprises the following steps:
and performing high conductivity treatment on the source region and the drain region by taking the gate electrode and the gate insulating layer as masks, wherein the conductivity of the source region is greater than that of the channel region, and the conductivity of the drain electrode is greater than that of the channel region.
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| CN115377204A (en) * | 2022-10-25 | 2022-11-22 | Tcl华星光电技术有限公司 | Display panel, manufacturing method thereof and display device |
| WO2022252470A1 (en) * | 2021-06-04 | 2022-12-08 | 华南理工大学 | Thin-film transistor and method for manufacturing thin-film transistor |
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- 2021-10-19 WO PCT/CN2021/124665 patent/WO2022252470A1/en unknown
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022252470A1 (en) * | 2021-06-04 | 2022-12-08 | 华南理工大学 | Thin-film transistor and method for manufacturing thin-film transistor |
| CN115377204A (en) * | 2022-10-25 | 2022-11-22 | Tcl华星光电技术有限公司 | Display panel, manufacturing method thereof and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2022252470A1 (en) | 2022-12-08 |
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