CN106298815A - Thin film transistor (TFT) and preparation method thereof, array base palte and display device - Google Patents
Thin film transistor (TFT) and preparation method thereof, array base palte and display device Download PDFInfo
- Publication number
- CN106298815A CN106298815A CN201610966325.4A CN201610966325A CN106298815A CN 106298815 A CN106298815 A CN 106298815A CN 201610966325 A CN201610966325 A CN 201610966325A CN 106298815 A CN106298815 A CN 106298815A
- Authority
- CN
- China
- Prior art keywords
- active layer
- tft
- thin film
- film transistor
- type semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 65
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 51
- 238000009413 insulation Methods 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims description 73
- 229920002120 photoresistant polymer Polymers 0.000 claims description 54
- 239000000463 material Substances 0.000 claims description 34
- 230000008569 process Effects 0.000 claims description 24
- 238000000059 patterning Methods 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 17
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 15
- 230000008021 deposition Effects 0.000 claims description 12
- 239000002041 carbon nanotube Substances 0.000 claims description 10
- 229910021393 carbon nanotube Inorganic materials 0.000 claims description 10
- 239000000155 melt Substances 0.000 claims description 8
- 230000000717 retained effect Effects 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 6
- 238000002161 passivation Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 229910021389 graphene Inorganic materials 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229920001621 AMOLED Polymers 0.000 description 3
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000002262 irrigation Effects 0.000 description 1
- 238000003973 irrigation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 239000006250 one-dimensional material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78639—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a drain or source connected to a bulk conducting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The invention provides a kind of thin film transistor (TFT) and preparation method thereof, array base palte and display device, belong to Display Technique field.Wherein, described thin film transistor (TFT) includes grid, gate insulation layer, source electrode, drain electrode and the active layer being positioned on underlay substrate, it is formed with one way conducting device, so that the signal of telecommunication is transferred to described drain electrode through described one way conducting device by described active layer between described active layer and described drain electrode.Technical scheme can effectively reduce the off-state current of thin film transistor (TFT), improves the display effect of display device.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of thin film transistor (TFT) and preparation method thereof, array base palte and
Display device.
Background technology
Along with the rise of Global Information Community adds the demand to various display devices.Therefore, various planes are shown
The research and development of device has put into the biggest effort, such as liquid crystal display (LCD), plasma display panel (PDP), electroluminescent
Display (ELD) and vacuum fluorescent display (VFD).
Thin film transistor (TFT) (Thin Film Transistor, TFT) is the key electricity of the one in modern microelectronic technology
Sub-device, has been widely used in the fields such as flat faced display.Conventional semiconductors industry and TFT-LCD show industry
In thin film transistor (TFT) all based on silicon materials, and carbon-based semiconductors material as a new generation semi-conducting material, because of
For its higher mobility, and the special electrical properties etc. being different from body material starts to obtain increasingly extensive research and development
Using, such as Graphene (Graphene), CNT (CNT) etc. is obtained for the most deep exploitation and attempts using.
The CNT-TFT of array is to use Solution coating processes to prepare at present, and active layer region forms random network and divides
The CNT of cloth, for short channel TFT, its off-state current is relatively big, and about 10-11-10-10A, prepares in this performance basis
The brightness of its OFF state of TFT-LCD higher, thus display contrast the most poor；And use long channel TFT, although pass can be reduced
State electric current, lifting switch ratio, but the aperture opening ratio of whole display device can be by extreme influence.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of thin film transistor (TFT) and preparation method thereof, array base palte and display
Device, it is possible to effectively reduce the off-state current of thin film transistor (TFT), improve the display effect of display device.
For solving above-mentioned technical problem, embodiments of the invention provide technical scheme as follows:
On the one hand, it is provided that a kind of thin film transistor (TFT), described thin film transistor (TFT) includes being positioned on underlay substrate grid, grid are exhausted
Edge layer, source electrode, drain electrode and active layer, be formed with one way conducting device between described active layer and described drain electrode, so that telecommunications
Number it is transferred to described drain electrode through described one way conducting device by described active layer.
Further, described one way conducting device is PN junction, described active layer at least some of be described PN junction just
Pole, is provided with the negative pole that N-type semiconductor figure is described PN junction between described active layer and described drain electrode.
Further, described active layer uses CNT semi-conducting material.
Further, described thin film transistor (TFT) specifically includes:
The grid being positioned on underlay substrate；
Cover the gate insulation layer of described grid；
It is positioned at the active layer on described gate insulation layer；
The described N-type semiconductor figure being positioned on described active layer；
The source electrode being positioned on described active layer and the drain electrode being positioned on described N-type semiconductor figure.
Further, described thin film transistor (TFT) specifically includes:
It is positioned at the active layer on described underlay substrate；
The described N-type semiconductor figure being positioned on described active layer；
Cover described active layer and the gate insulation layer of described N-type semiconductor figure；
Being positioned at the grid on described gate insulation layer, source electrode and drain electrode, described source electrode is by running through the mistake of described gate insulation layer
Hole is connected with described active layer, and described drain electrode is connected with described N-type semiconductor figure by running through the via of described gate insulation layer.
The embodiment of the present invention additionally provides the manufacture method of a kind of thin film transistor (TFT), is included on underlay substrate formation grid
Pole, gate insulation layer, source electrode, drain electrode and active layer, described method also includes:
It is formed with one way conducting device, so that the signal of telecommunication is through described one-way conduction between described active layer and described drain electrode
Device is transferred to described drain electrode by described active layer.
Further, described manufacture method specifically includes:
One underlay substrate is provided；
Described underlay substrate is formed cushion；
Described cushion deposits grid conductive layer, forms described grid by patterning processes；
Form described gate insulation layer；
Deposition of carbon nanotubes semi-conducting material and N-type semiconductor material on described gate insulation layer, at N-type semiconductor material
Upper coating photoresist, uses gray tone mask plate to be exposed photoresist, forms photoresist and does not retains region, photoresist part
Retaining region and photoresist is fully retained region, wherein, photoresist part retains the figure of region correspondence active layer, and photoresist is complete
All risk insurance stays region correspondence N-type semiconductor figure, and photoresist does not retains other regions corresponding, region；
Etching away photoresist and do not retain CNT semi-conducting material and the N-type semiconductor material in region, ash melts photoetching
Glue part retains the photoresist in region, etches away photoresist part and retains the N-type semiconductor material in region, and it is complete that ash melts photoresist
All risk insurance stays the photoresist in region, is formed with active layer and described N-type semiconductor figure；
Sedimentary origin leakage conductance electric layer, forms source electrode and drain electrode by patterning processes.
Further, described manufacture method specifically includes:
One underlay substrate is provided；
Described underlay substrate is formed cushion；
On described cushion, deposition of carbon nanotubes semi-conducting material, is formed with active layer by patterning processes；
Deposited n-type semi-conducting material on described active layer, forms described N-type semiconductor figure by patterning processes；
Formed and cover described active layer and the gate insulation layer of described N-type semiconductor figure；
Depositing conductive layer on described gate insulation layer, form grid, source electrode and drain electrode by patterning processes, described source electrode leads to
Cross the via running through described gate insulation layer to be connected with described active layer, described drain electrode by run through the via of described gate insulation layer with
Described N-type semiconductor figure connects.
The embodiment of the present invention additionally provides a kind of array base palte, including thin film transistor (TFT) as above.
The embodiment of the present invention additionally provides a kind of display device, including array base palte as above.
Embodiments of the invention have the advantages that
In such scheme, between the active layer and drain electrode of thin film transistor (TFT), it is formed with one way conducting device, at active layer
Current potential higher than drain electrode current potential time, one way conducting device turn on；When the current potential of active layer is less than the current potential drained, unidirectional
Logical device cut-off such that it is able to effectively reducing the off-state current of thin film transistor (TFT), the thin film transistor (TFT) in the present invention is applied to show
During showing device, it is possible to increase displaying contrast of display device, improve the display effect of display device.
Accompanying drawing explanation
The energy level schematic diagram of the PN junction that Fig. 1 is formed by CNT and ZnO；
Fig. 2 is the schematic flow sheet of the manufacture method of one embodiment of the invention array base palte；
Fig. 3 is the schematic flow sheet of the manufacture method of another embodiment of the present invention array base palte.
Reference
1 underlay substrate 2 cushion 3 grid 4 gate insulation layer
5 CNT material 6 N-type semiconductor materials 7 drain 8 source electrodes
9 passivation layer 10 pixel electrodes
Detailed description of the invention
For making embodiments of the invention solve the technical problem that, technical scheme and advantage clearer, below in conjunction with
Drawings and the specific embodiments are described in detail.
Embodiments of the invention are for the bigger problem of CNT-TFT off-state current in prior art, it is provided that a kind of thin film is brilliant
Body pipe and preparation method thereof, array base palte and display device, it is possible to effectively reduce the off-state current of thin film transistor (TFT), improve display
The display effect of device.
Embodiment one
The present embodiment provides a kind of thin film transistor (TFT), and described thin film transistor (TFT) includes grid, the grid being positioned on underlay substrate
Insulating barrier, source electrode, drain electrode and active layer, be formed with one way conducting device between described active layer and described drain electrode, so that electric
Signal is transferred to described drain electrode through described one way conducting device by described active layer.
In the present embodiment, between the active layer and drain electrode of thin film transistor (TFT), it is formed with one way conducting device, at active layer
Current potential higher than drain electrode current potential time, one way conducting device turn on；When the current potential of active layer is less than the current potential drained, unidirectional
Logical device cut-off such that it is able to effectively reducing the off-state current of thin film transistor (TFT), the thin film transistor (TFT) in the present invention is applied to show
During showing device, it is possible to increase displaying contrast of display device, improve the display effect of display device.
Specifically, described one way conducting device is PN junction, and described active layer at least some of is the positive pole of described PN junction,
The negative pole that N-type semiconductor figure is described PN junction it is provided with between described active layer and described drain electrode.In preferred embodiment, N-type
Semiconductor figure projection on described underlay substrate overlaps with described drain electrode projection on described underlay substrate.
In preferred embodiment, owing to carbon nano-tube material has higher mobility, therefore, it can utilize CNT material
Material makes active layer, and the intrinsic property simultaneously utilizing carbon nano-tube material is p-type, and the semi-conducting material using N-type intrinsic can
Form PN junction diode therewith, ZnO Yu CNT specifically can be used to form PN junction, the energy of the PN junction that Fig. 1 is formed by CNT and ZnO
Level schematic diagram, the PN junction of formation possesses rectification characteristic, and the current potential at carbon nano-tube material is higher than on the semi-conducting material of N-type intrinsic
Current potential time, PN junction turn on；When adding backward voltage, PN junction ends such that it is able to effectively reduce the off-state current of CNT-TFT, expands
The scope of application of big CNT-TFT.
Further, in addition to ZnO, N-type semiconductor figure can also use a-Si or LTPS.
In specific embodiment, described thin film transistor (TFT) can be bottom gate thin film transistor, specifically includes:
The grid being positioned on underlay substrate；
Cover the gate insulation layer of described grid；
It is positioned at the active layer on described gate insulation layer；
The described N-type semiconductor figure being positioned on described active layer；
The source electrode being positioned on described active layer and the drain electrode being positioned on described N-type semiconductor figure.
In specific embodiment, described thin film transistor (TFT) can be top gate type thin film transistor, specifically includes:
It is positioned at the active layer on described underlay substrate；
The described N-type semiconductor figure being positioned on described active layer；
Cover described active layer and the gate insulation layer of described N-type semiconductor figure；
Being positioned at the grid on described gate insulation layer, source electrode and drain electrode, described source electrode is by running through the mistake of described gate insulation layer
Hole is connected with described active layer, and described drain electrode is connected with described N-type semiconductor figure by running through the via of described gate insulation layer.
The thin film transistor (TFT) of the present embodiment can be as the switching thin-film transistor of array base palte viewing area, it is also possible to make
For the function film transistor that viewing area is peripheral, it is adaptable in the multiple display device such as LCD and AMOLED.
Wherein, active layer is in addition to can using CNT material, it is also possible to use semiconductive carbon nano tube material, silicon nanometer
The one-dimensional materials such as line, iii-v nano wire and other contain overlapping configuration i.e. X, the semi-conducting material of y-type structure.
The thin film transistor (TFT) of the present embodiment can be bottom-gate type configuration, but is not limited to this, it is also possible to for top-gate type structure, friendship
Stack-type structure, reciprocal cross stack-type structure, coplanar type structure or anti-communism surface structure etc..
Embodiment two
Present embodiments provide the manufacture method of a kind of thin film transistor (TFT), be included on underlay substrate formation grid, grid exhausted
Edge layer, source electrode, drain electrode and active layer, described method also includes:
It is formed with one way conducting device, so that the signal of telecommunication is through described one-way conduction between described active layer and described drain electrode
Device is transferred to described drain electrode by described active layer.
In the present embodiment, between the active layer and drain electrode of thin film transistor (TFT), it is formed with one way conducting device, at active layer
Current potential higher than drain electrode current potential time, one way conducting device turn on；When the current potential of active layer is less than the current potential drained, unidirectional
Logical device cut-off such that it is able to effectively reducing the off-state current of thin film transistor (TFT), the thin film transistor (TFT) in the present invention is applied to show
During showing device, it is possible to increase displaying contrast of display device, improve the display effect of display device.
Further, when making the thin film transistor (TFT) of bottom gate type, described manufacture method specifically includes:
One underlay substrate is provided；
Described underlay substrate is formed cushion；
Described cushion deposits grid conductive layer, forms described grid by patterning processes；
Form described gate insulation layer；
Deposition of carbon nanotubes semi-conducting material and N-type semiconductor material on described gate insulation layer, at N-type semiconductor material
Upper coating photoresist, uses gray tone mask plate to be exposed photoresist, forms photoresist and does not retains region, photoresist part
Retaining region and photoresist is fully retained region, wherein, photoresist part retains the figure of region correspondence active layer, and photoresist is complete
All risk insurance stays region correspondence N-type semiconductor figure, and photoresist does not retains other regions corresponding, region；
Etching away photoresist and do not retain CNT semi-conducting material and the N-type semiconductor material in region, ash melts photoetching
Glue part retains the photoresist in region, etches away photoresist part and retains the N-type semiconductor material in region, and it is complete that ash melts photoresist
All risk insurance stays the photoresist in region, is formed with active layer and described N-type semiconductor figure；
Sedimentary origin leakage conductance electric layer, forms source electrode and drain electrode by patterning processes.
Further, when making the thin film transistor (TFT) of top gate type, described manufacture method specifically includes:
One underlay substrate is provided；
Described underlay substrate is formed cushion；
On described cushion, deposition of carbon nanotubes semi-conducting material, is formed with active layer by patterning processes；
Deposited n-type semi-conducting material on described active layer, forms described N-type semiconductor figure by patterning processes；
Formed and cover described active layer and the gate insulation layer of described N-type semiconductor figure；
Depositing conductive layer on described gate insulation layer, form grid, source electrode and drain electrode by patterning processes, described source electrode leads to
Cross the via running through described gate insulation layer to be connected with described active layer, described drain electrode by run through the via of described gate insulation layer with
Described N-type semiconductor figure connects.
Embodiment three
Present embodiments provide a kind of array base palte, including thin film transistor (TFT) as above.
Embodiment four
Present embodiments provide a kind of display device, including array base palte as above.Described display device can be:
Any product with display function or the parts such as LCD TV, liquid crystal display, DPF, mobile phone, panel computer, its
In, described display device also includes flexible PCB, printed circuit board (PCB) and backboard.
Embodiment five
As in figure 2 it is shown, the manufacture method of the thin film transistor (TFT) of the present embodiment specifically includes following steps:
Step 1, as shown in Fig. 2 (a), it is provided that a underlay substrate 1, underlay substrate 1 can use glass substrate or quartz base
Plate；
Step 2, as shown in Fig. 2 (b), on underlay substrate 1 formed cushion 2；
Specifically, SiO thick for CVD (chemical gaseous phase deposition) method deposition 200nm can be used2Thin film is as cushion；
Step 3, as shown in Fig. 2 (c), form the grid 3 of thin film transistor (TFT) on the buffer layer 2；
Specifically, sputtering method can be used to deposit grid conductive layer on the buffer layer 2, form thin film by patterning processes brilliant
The grid 3 of body pipe, grid conductive layer can use the metal materials such as Mo, Al, Cr, alloy material or other composite conducting materials, its
Thickness is 100-500nm, preferably 200nm.
Step 4, as shown in Fig. 2 (d), formed gate insulation layer 4；
The insulant such as silicon oxide, silicon nitride can be used to form gate insulation layer 4, specifically, CVD method can be used to exist
The SiO of 150nm is deposited at 370 DEG C2As gate insulation layer 4.
Step 5, as shown in Fig. 2 (e), use spin-coating method formed one layer of CNT material 5；
Step 6, as shown in Fig. 2 (f), deposit one layer of N-type semiconductor material 6；
Specifically, the ZnO film of sputtering technology deposition 3nm can be used.
Step 7, as shown in Fig. 2 (g), use gray tone mask plate to be patterned the N-type that is formed with on active layer and active layer
Semiconductor figure；
Specifically, ZnO film coats photoresist, use gray tone mask plate that photoresist is exposed, form light
Photoresist does not retains region, photoresist part retains region and photoresist is fully retained region, and wherein, photoresist part retains region
The figure of corresponding active layer, photoresist is fully retained region correspondence N-type semiconductor figure, photoresist do not retain region corresponding other
Region；
Etching away photoresist and do not retain CNT material and the ZnO film in region, ash melts photoresist part and retains the light in region
Photoresist, etches away photoresist part and retains the ZnO film in region, and ash melts photoresist and the photoresist in region is fully retained, and is formed
Active layer and described N-type semiconductor figure.
Step 8, as shown in Fig. 2 (h), form source electrode 8 and the drain electrode 7 of thin film transistor (TFT)；
Specifically, sputtering method sedimentary origin leakage conductance electric layer can be used, be formed the source of thin film transistor (TFT) by patterning processes
Pole 8 and drain electrode 7, source and drain conductive layer can use the metal materials such as Mo, Al, Cr, alloy material or other composite conducting materials, its
Thickness is 100-500nm, preferably 200nm.
The bottom gate thin film transistor of the present embodiment can be produced through above-mentioned steps 1-8.
Further, it is also possible to making array base palte based on above-mentioned thin film transistor (TFT), the manufacture method of array base palte is also
Including:
Step 9, as shown in Fig. 2 (i), formed passivation layer 9；
The insulant such as silicon oxide, silicon nitride can be used to form passivation layer, specifically, CVD method can be used 370
The SiO of 150nm is deposited at DEG C2As passivation layer 9；Passivation layer 9 may be used without the organic materials such as acrylic based material or resin, thick
Degree generally 0.1um-1um.
Step 10, as shown in Fig. 2 (j), formed pixel electrode 10.
Specifically, ITO, IZO or the Graphene of sputtering method deposition 40nm can be used on underlay substrate, be patterned
Form pixel electrode 10.
Further, when array base palte is AMOLED array basal plate, follow-up Making programme also includes depositing acrylic system
Material photoetching, solidify pixel and define layer；Using plasma processes array base palte surface；And then form anode layer, organic
Luminescent layer and cathode layer etc., do not repeat them here.Cathode layer can use LiF:Al layer, and integral thickness is 100-300nm, makes
The light mode that goes out of the AMOLED array basal plate gone out is to go out light in the end.
Embodiment six
As it is shown on figure 3, the manufacture method of the thin film transistor (TFT) of the present embodiment specifically includes following steps:
Step 1, as shown in Fig. 3 (a), it is provided that a underlay substrate 1, underlay substrate 1 can use glass substrate or quartz base
Plate；
Step 2, as shown in Fig. 3 (b), on underlay substrate 1 formed cushion 2；
Specifically, SiO thick for CVD method deposition 200nm can be used2Thin film is as cushion；
Step 3, as shown in Fig. 3 (c), on the buffer layer 2 use spin-coating method formed one layer of CNT material 5, pass through patterning processes
It is formed with the figure of active layer；
Specifically, in patterning processes, O can be used2CNT material 5 is carried out dry etching.
Step 4, as shown in Fig. 3 (d), deposited n-type semi-conducting material 6 on active layer, form N-type half by patterning processes
Conductor fig；
Specifically, it is possible to use the N+-a-Si thin layer of CVD process deposits 3nm, and carry out photoetching, only retain drain region
The N+-a-Si in territory, forms N-type semiconductor figure.
Step 5, as shown in Fig. 3 (e), formed gate insulation layer 4；
The insulant such as silicon oxide, silicon nitride can be used to form gate insulation layer 4, specifically, CVD method can be used to exist
The SiO of 150nm is deposited at 370 DEG C2As gate insulation layer 4.
Step 6, as shown in Fig. 3 (f), formed the grid 3 of thin film transistor (TFT), source electrode 8 and drain electrode 7；
Specifically, can use sputtering method deposit conductive layer, by patterning processes formed thin film transistor (TFT) grid 3,
Source electrode 8 and drain electrode 7, conductive layer can use the metal materials such as Mo, Al, Cr, alloy material or other composite conducting materials, and it is thick
Degree is 100-500nm, preferably 200nm.
The top gate type thin film transistor of the present embodiment can be produced through above-mentioned steps 1-6.
Further, it is also possible to making array base palte based on above-mentioned thin film transistor (TFT), the manufacture method of array base palte is also
Including:
Step 7, as shown in Fig. 3 (g), formed passivation layer 9；
The insulant such as silicon oxide, silicon nitride can be used to form passivation layer, specifically, CVD method can be used 370
The SiO of 150nm is deposited at DEG C2As passivation layer 9；Passivation layer 9 may be used without the organic materials such as acrylic based material or resin, thick
Degree generally 0.1um-1um.
Step 8, as shown in Fig. 3 (h), formed pixel electrode 10.
Specifically, ITO, IZO or the Graphene of sputtering method deposition 40nm can be used, be patterned forming pixel electrode
10。
Further, when array base palte is AMLCD array base palte, follow-up Making programme also includes that PI coating, impressing take
To, Spacer (chock insulator matter) preparation and the preparation of corresponding color membrane substrates, and carry out techniques such as box, cutting, irrigation crystal and sealings,
This repeats no more.
Wherein, in the present embodiment as required, after depositing CNT material, it is also possible to be doped and activating process；Heavy
Etching barrier layer can also be prepared to protect active layer before long-pending conductive layer.
In each method embodiment of the present invention, the priority that the sequence number of described each step can not be used for limiting each step is suitable
Sequence, for those of ordinary skill in the art, on the premise of not paying creative work, changes also the priority of each step
Within protection scope of the present invention.
The above is the preferred embodiment of the present invention, it is noted that for those skilled in the art
For, on the premise of without departing from principle of the present invention, it is also possible to make some improvements and modifications, these improvements and modifications are also
Should be regarded as protection scope of the present invention.
Claims (10)
1. a thin film transistor (TFT), grid that described thin film transistor (TFT) includes being positioned on underlay substrate, gate insulation layer, source electrode, leakage
Pole and active layer, it is characterised in that between described active layer and described drain electrode, be formed with one way conducting device, so that the signal of telecommunication
It is transferred to described drain electrode by described active layer through described one way conducting device.
Thin film transistor (TFT) the most according to claim 1, it is characterised in that described one way conducting device is PN junction, described in have
Active layer at least some of is the positive pole of described PN junction, is provided with N-type semiconductor figure between described active layer and described drain electrode
Negative pole for described PN junction.
Thin film transistor (TFT) the most according to claim 2, it is characterised in that described active layer uses CNT quasiconductor material
Material.
Thin film transistor (TFT) the most according to claim 2, it is characterised in that described thin film transistor (TFT) specifically includes:
The grid being positioned on underlay substrate；
Cover the gate insulation layer of described grid；
It is positioned at the active layer on described gate insulation layer；
The described N-type semiconductor figure being positioned on described active layer；
The source electrode being positioned on described active layer and the drain electrode being positioned on described N-type semiconductor figure.
Thin film transistor (TFT) the most according to claim 2, it is characterised in that described thin film transistor (TFT) specifically includes:
It is positioned at the active layer on described underlay substrate；
The described N-type semiconductor figure being positioned on described active layer；
Cover described active layer and the gate insulation layer of described N-type semiconductor figure；
Be positioned at the grid on described gate insulation layer, source electrode and drain electrode, described source electrode by run through the via of described gate insulation layer with
Described active layer connects, and described drain electrode is connected with described N-type semiconductor figure by running through the via of described gate insulation layer.
6. a manufacture method for thin film transistor (TFT), be included on underlay substrate formation grid, gate insulation layer, source electrode, drain electrode and
Active layer, it is characterised in that described method also includes:
It is formed with one way conducting device, so that the signal of telecommunication is through described one way conducting device between described active layer and described drain electrode
It is transferred to described drain electrode by described active layer.
The manufacture method of thin film transistor (TFT) the most according to claim 6, it is characterised in that described manufacture method is specifically wrapped
Include:
One underlay substrate is provided；
Described underlay substrate is formed cushion；
Described cushion deposits grid conductive layer, forms described grid by patterning processes；
Form described gate insulation layer；
Deposition of carbon nanotubes semi-conducting material and N-type semiconductor material on described gate insulation layer, be coated with on N-type semiconductor material
Cover photoresist, use gray tone mask plate that photoresist is exposed, form photoresist and do not retain region, the reservation of photoresist part
Region and photoresist are fully retained region, and wherein, photoresist part retains the figure of region correspondence active layer, and photoresist is protected completely
Staying region correspondence N-type semiconductor figure, photoresist does not retains other regions corresponding, region；
Etching away photoresist and do not retain CNT semi-conducting material and the N-type semiconductor material in region, ash melts photoresist portion
Code insurance stays the photoresist in region, etches away photoresist part and retains the N-type semiconductor material in region, and ash melts photoresist and protects completely
Stay the photoresist in region, be formed with active layer and described N-type semiconductor figure；
Sedimentary origin leakage conductance electric layer, forms source electrode and drain electrode by patterning processes.
The manufacture method of thin film transistor (TFT) the most according to claim 6, it is characterised in that described manufacture method is specifically wrapped
Include:
One underlay substrate is provided；
Described underlay substrate is formed cushion；
On described cushion, deposition of carbon nanotubes semi-conducting material, is formed with active layer by patterning processes；
Deposited n-type semi-conducting material on described active layer, forms described N-type semiconductor figure by patterning processes；
Formed and cover described active layer and the gate insulation layer of described N-type semiconductor figure；
Depositing conductive layer on described gate insulation layer, form grid, source electrode and drain electrode by patterning processes, described source electrode is by passing through
The via wearing described gate insulation layer is connected with described active layer, and described drain electrode is by running through the via of described gate insulation layer with described
N-type semiconductor figure connects.
9. an array base palte, it is characterised in that include the thin film transistor (TFT) as according to any one of claim 1-5.
10. a display device, it is characterised in that include array base palte as claimed in claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610966325.4A CN106298815A (en) | 2016-10-31 | 2016-10-31 | Thin film transistor (TFT) and preparation method thereof, array base palte and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610966325.4A CN106298815A (en) | 2016-10-31 | 2016-10-31 | Thin film transistor (TFT) and preparation method thereof, array base palte and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106298815A true CN106298815A (en) | 2017-01-04 |
Family
ID=57718915
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610966325.4A Pending CN106298815A (en) | 2016-10-31 | 2016-10-31 | Thin film transistor (TFT) and preparation method thereof, array base palte and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106298815A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107330200A (en) * | 2017-07-03 | 2017-11-07 | 京东方科技集团股份有限公司 | The determination method and apparatus of the tolerance electrostatic potential of thin film transistor (TFT) |
| CN107958938A (en) * | 2017-11-07 | 2018-04-24 | 深圳市华星光电半导体显示技术有限公司 | A kind of thin film transistor (TFT) and display device |
| CN108987576A (en) * | 2018-07-18 | 2018-12-11 | 深圳市华星光电半导体显示技术有限公司 | The preparation method of carbon nano-tube coextruded film, carbon nanotube TFT and preparation method thereof |
| CN111403418A (en) * | 2018-12-29 | 2020-07-10 | 广东聚华印刷显示技术有限公司 | Array substrate, manufacturing method thereof and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05114733A (en) * | 1991-10-21 | 1993-05-07 | Sharp Corp | Thin film transistor |
| EP0697740B1 (en) * | 1994-08-18 | 2000-06-07 | Sun Microsystems, Inc. | Low threshold voltage, high performance junction transistor |
| CN101834137A (en) * | 2009-03-12 | 2010-09-15 | 中芯国际集成电路制造(上海)有限公司 | Ion implantation method for source/drain electrodes |
| CN105655410A (en) * | 2016-04-13 | 2016-06-08 | 京东方科技集团股份有限公司 | Non-shading type thin-film transistor, array substrate and display device |
-
2016
- 2016-10-31 CN CN201610966325.4A patent/CN106298815A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05114733A (en) * | 1991-10-21 | 1993-05-07 | Sharp Corp | Thin film transistor |
| EP0697740B1 (en) * | 1994-08-18 | 2000-06-07 | Sun Microsystems, Inc. | Low threshold voltage, high performance junction transistor |
| CN101834137A (en) * | 2009-03-12 | 2010-09-15 | 中芯国际集成电路制造(上海)有限公司 | Ion implantation method for source/drain electrodes |
| CN105655410A (en) * | 2016-04-13 | 2016-06-08 | 京东方科技集团股份有限公司 | Non-shading type thin-film transistor, array substrate and display device |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107330200A (en) * | 2017-07-03 | 2017-11-07 | 京东方科技集团股份有限公司 | The determination method and apparatus of the tolerance electrostatic potential of thin film transistor (TFT) |
| CN107330200B (en) * | 2017-07-03 | 2020-12-08 | 京东方科技集团股份有限公司 | Method and apparatus for determining withstand electrostatic voltage of thin film transistor |
| CN107958938A (en) * | 2017-11-07 | 2018-04-24 | 深圳市华星光电半导体显示技术有限公司 | A kind of thin film transistor (TFT) and display device |
| CN108987576A (en) * | 2018-07-18 | 2018-12-11 | 深圳市华星光电半导体显示技术有限公司 | The preparation method of carbon nano-tube coextruded film, carbon nanotube TFT and preparation method thereof |
| WO2020015002A1 (en) * | 2018-07-18 | 2020-01-23 | 深圳市华星光电半导体显示技术有限公司 | Manufacturing method for carbon nanotube composite thin film, carbon nanotube tft, and manufacturing method therefor |
| CN108987576B (en) * | 2018-07-18 | 2020-12-25 | 深圳市华星光电半导体显示技术有限公司 | Preparation method of carbon nanotube composite film, carbon nanotube TFT and preparation method thereof |
| US10930851B2 (en) | 2018-07-18 | 2021-02-23 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Manufacturing method for carbon nanotube composite film, carbon nanotube TFT and manufacturing method for the same |
| CN111403418A (en) * | 2018-12-29 | 2020-07-10 | 广东聚华印刷显示技术有限公司 | Array substrate, manufacturing method thereof and display device |
| CN111403418B (en) * | 2018-12-29 | 2023-04-18 | 广东聚华印刷显示技术有限公司 | Array substrate, manufacturing method thereof and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104064688B (en) | There is manufacture method and this TFT substrate of the TFT substrate of storage electric capacity | |
| CN101901787B (en) | Oxide thin film transistor and method of fabricating the same | |
| CN104681629B (en) | Thin film transistor (TFT), array base palte and its respective preparation method, display device | |
| CN105390551B (en) | Thin film transistor (TFT) and its manufacturing method, array substrate, display device | |
| KR102040011B1 (en) | Electrostatic discharging device of display device and method of manufacturing the same | |
| CN103872060B (en) | Array base palte and manufacture method thereof | |
| CN106129122B (en) | Oxide thin film transistor and preparation method thereof, array substrate, display device | |
| CN105161503B (en) | Amorphous silicon semiconductor TFT backplate structure | |
| CN103715267A (en) | TFT, TFT array substrate, manufacturing method of TFT array substrate and display device | |
| CN106129086B (en) | TFT substrate and preparation method thereof | |
| CN106816473A (en) | Thin film transistor (TFT) and preparation method thereof, array base palte and display device | |
| WO2016176881A1 (en) | Manufacturing method for dual-gate tft substrate, and structure of dual-gate tft substrate | |
| CN104900654A (en) | Preparation method and structure of double-grid oxide semiconductor TFT substrate | |
| CN109273365A (en) | Preparation method, thin film transistor (TFT) and the display panel of thin film transistor (TFT) | |
| CN106298815A (en) | Thin film transistor (TFT) and preparation method thereof, array base palte and display device | |
| CN104638017A (en) | Thin film transistor, pixel structure, manufacturing methods of thin film transistor and pixel structure, array substrate and display device | |
| CN104576758A (en) | Thin film transistor, array substrate, manufacturing method for thin film transistor and manufacturing method for array substrate | |
| CN107516661A (en) | The preparation method of display base plate, display device and display base plate | |
| CN108417580A (en) | Array substrate and preparation method thereof and display panel | |
| CN104362179A (en) | Thin-film transistor, manufacturing method of thin-film transistor, array substrate and display device | |
| CN103762244A (en) | Thin film transistor, manufacturing method of thin film transistor, thin film transistor array substrate and liquid crystal panel | |
| CN106252395A (en) | A kind of thin film transistor (TFT) and preparation method thereof | |
| CN108010850A (en) | Thin film transistor (TFT) and preparation method thereof, TFT substrate | |
| CN110233156A (en) | The production method and thin film transistor base plate of thin film transistor base plate | |
| CN108269856A (en) | A kind of oxide semiconductor thin-film transistor and preparation method thereof, array substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170104 |
|
| RJ01 | Rejection of invention patent application after publication |