US20130001573A1 - Thin film transistor and method of manufacturing the same - Google Patents
Thin film transistor and method of manufacturing the same Download PDFInfo
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- US20130001573A1 US20130001573A1 US13/418,172 US201213418172A US2013001573A1 US 20130001573 A1 US20130001573 A1 US 20130001573A1 US 201213418172 A US201213418172 A US 201213418172A US 2013001573 A1 US2013001573 A1 US 2013001573A1
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- 239000010409 thin film Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 186
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 171
- 239000004065 semiconductor Substances 0.000 claims abstract description 166
- 239000000758 substrate Substances 0.000 claims description 50
- 238000002161 passivation Methods 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 38
- 239000010949 copper Substances 0.000 claims description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 28
- 239000010936 titanium Substances 0.000 claims description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- 229910052802 copper Inorganic materials 0.000 claims description 15
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 12
- 229910045601 alloy Inorganic materials 0.000 claims description 12
- 239000000956 alloy Substances 0.000 claims description 12
- 229910052750 molybdenum Inorganic materials 0.000 claims description 12
- 239000011733 molybdenum Substances 0.000 claims description 12
- 229910052719 titanium Inorganic materials 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 10
- 238000004380 ashing Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 385
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 20
- 238000010406 interfacial reaction Methods 0.000 description 16
- 229910052782 aluminium Inorganic materials 0.000 description 15
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 description 11
- 239000002356 single layer Substances 0.000 description 11
- 239000011787 zinc oxide Substances 0.000 description 10
- 239000004020 conductor Substances 0.000 description 9
- 230000008569 process Effects 0.000 description 9
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 8
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 8
- NJWNEWQMQCGRDO-UHFFFAOYSA-N indium zinc Chemical compound [Zn].[In] NJWNEWQMQCGRDO-UHFFFAOYSA-N 0.000 description 6
- 230000003247 decreasing effect Effects 0.000 description 5
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 150000001768 cations Chemical class 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 3
- 230000003252 repetitive effect Effects 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- WGCXSIWGFOQDEG-UHFFFAOYSA-N [Zn].[Sn].[In] Chemical compound [Zn].[Sn].[In] WGCXSIWGFOQDEG-UHFFFAOYSA-N 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
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- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 1
- 229910016553 CuOx Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910001431 copper ion Inorganic materials 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Definitions
- Exemplary embodiments of the present invention relate to a thin film transistor and a method of manufacturing the thin film transistor. More particularly, exemplary embodiments of the present invention relate to a thin film transistor having improved electrical stability and a method of manufacturing the thin film transistor.
- a display apparatus includes an array substrate including a switching element and an opposite substrate facing the array substrate.
- the switching element includes a gate electrode electrically connected to a gate line, a semiconductor layer insulated from the gate electrode, a source electrode electrically connected to a data line and the semiconductor layer, and a drain electrode spaced apart from the source electrode and electrically connected to the semiconductor layer.
- the types of switching elements for the display apparatus may be divided into an amorphous silicon thin film transistor (“TFT”), a poly silicon TFT, and an oxide semiconductor TFT.
- TFT amorphous silicon thin film transistor
- poly silicon TFT a poly silicon TFT
- oxide semiconductor TFT oxide semiconductor
- the amorphous silicon TFT is uniformly formed on a large substrate in a low manufacturing cost.
- the amorphous silicon TFT has a relatively low charge carrier mobility.
- the poly silicon TFT has a charge carrier mobility higher than the amorphous silicon TFT, and a deterioration of a characteristic of the poly silicon TFT is less than the amorphous silicon TFT.
- a process of manufacturing the poly silicon TFT is complicated so that a manufacturing cost is high.
- the oxide semiconductor TFT may be manufactured in a low temperature process, may be formed in a large area, and may have a relatively high charge carrier mobility.
- the switching element when the source electrode and the drain electrode react with the semiconductor layer, a conductive characteristic of the semiconductor layer may be changed.
- a cation included in the oxide semiconductor when the oxide semiconductor reacts with the source electrode and the drain electrode, a cation included in the oxide semiconductor may be deposited so that a wiring resistance may increase. Thus, the electrical stability and reliability of the switching element may decrease.
- the insulating layer or a passivation layer may be lifted off from the source electrode and the drain electrode.
- the insulating layer or the passivation layer of the oxide silicon TFT includes an oxide silicon
- the insulating layer or the passivation layer may be lifted off more frequently and more seriously.
- Exemplary embodiments of the present invention provide a thin film transistor (“TFT”) capable of improving an electrical stability and a reliability using a graphene pattern.
- TFT thin film transistor
- Exemplary embodiments of the present invention also provide a method of manufacturing the TFT.
- the TFT includes a gate electrode, a semiconductor layer, a gate insulating layer, a source electrode, a drain electrode and a graphene pattern.
- the semiconductor layer overlaps with the gate electrode.
- the gate insulating layer is disposed between the gate electrode and the semiconductor layer.
- the source electrode overlaps with the semiconductor layer.
- the drain electrode overlaps with the semiconductor layer.
- the drain electrode is spaced apart from the source electrode.
- the graphene pattern is disposed between the semiconductor layer and at least one of the source electrode and the drain electrode.
- the method includes forming a gate electrode on a base substrate, forming a gate insulating layer on the gate electrode, forming a semiconductor layer overlapping with the gate electrode on the gate insulating layer, forming a graphene layer on the semiconductor layer, forming a source electrode and a drain electrode on the graphene layer and patterning the graphene layer between the source and drain electrodes to form a graphene pattern.
- the method includes forming a source electrode on a base substrate, forming an insulating layer on the source electrode, forming a drain electrode on the insulating layer, forming a graphene pattern on the drain electrode, forming a semiconductor layer on the graphene pattern, patterning the semiconductor layer, forming a gate insulating layer on the semiconductor layer and forming a gate electrode on the gate insulating layer.
- FIG. 1 is a plan view of an array substrate according to an exemplary embodiment of the present invention.
- FIG. 2 is a cross-sectional view taken along a line I-I′ of FIG. 1 .
- FIG. 3A , FIG. 3B , FIG. 3C , and FIG. 3D are cross-sectional views illustrating an exemplary embodiment of a method of manufacturing the array substrate of FIG. 1 .
- FIG. 4 is a cross-sectional view of an array substrate according to another exemplary embodiment of the present invention.
- FIG. 5A , FIG. 5B , FIGS. 5C , 5 D, and 5 E are cross-sectional views illustrating a method of manufacturing the array substrate of FIG. 4 .
- FIG. 6 is a cross-sectional view of an array substrate according to still another exemplary embodiment of the present invention.
- FIG. 7 is a cross-sectional view illustrating a method of manufacturing the array substrate of FIG. 6 .
- FIG. 8 is a cross-sectional view of an array substrate according to still another exemplary embodiment of the present invention.
- FIG. 1 is a plan view of an array substrate according to an exemplary embodiment of the present invention.
- the array substrate includes a gate line GL formed on a base substrate, a data line DL, a thin film transistor (“TFT”) TR 1 and a pixel electrode 180 .
- TFT thin film transistor
- the gate line GL may extend in a first direction.
- the array substrate may include a plurality of the gate lines GL.
- the data line DL may extend in a second direction crossing the first direction.
- the array substrate may include a plurality of the data lines DL.
- the TFT TR 1 is electrically connected to the gate line GL and the data line DL.
- the TFT TR 1 may be disposed in an area where the gate line GL and the data line DL cross with each other.
- the TFT TR 1 includes a gate electrode GE 1 , a source electrode SE 1 and a drain electrode DE 1 .
- the gate electrode GE 1 may be electrically connected to the gate line GL.
- the gate electrode GE 1 may be formed integrally with the gate line GL.
- the gate electrode GE 1 may be a protruded portion from the gate line GL.
- the source electrode SE 1 may be formed integrally with the data line DL.
- the source electrode SE 1 may be a protruded portion from the data line DL.
- the TFT TR 1 is explained in detail referring to FIG. 2 .
- the pixel electrode 180 is electrically connected to the TFT TR 1 .
- a data voltage applied to the data line DL is transmitted to the pixel electrode 180 .
- FIG. 2 is a cross-sectional view taken along line I-I′ of FIG. 1 .
- the TFT TR 1 includes the gate electrode GE 1 , a gate insulating layer 120 , a semiconductor layer 130 , a graphene pattern 140 , the source electrode SE 1 and the drain electrode DE 1
- the gate electrode GE 1 is disposed on the base substrate 110 .
- the gate electrode GE 1 may include one of aluminum (Al), copper (Cu), molybdenum (Mo) and titanium Ti or an alloy thereof.
- the gate electrode GE 1 may include a transparent conductive material such as an indium tin oxide (ITO), an indium zinc oxide (IZO) and an aluminum doped zinc oxide (AZO).
- ITO indium tin oxide
- IZO indium zinc oxide
- AZO aluminum doped zinc oxide
- the present invention is not limited to a material of the gate electrode GE 1 .
- the gate electrode GE 1 may have a single layer structure.
- the gate electrode GE 1 may have a multi layer structure which includes a plurality of conductive layers or at least one of conductive layers and at least one of insulating layers.
- the gate insulating layer 120 is disposed on the gate electrode GE 1 .
- the gate insulating layer 120 insulates the gate line GL from the data line DL.
- the gate insulating layer 120 insulates the gate electrode GE 1 from the semiconductor layer 130 .
- the gate insulating layer 120 may be disposed in an entire area of the base substrate 110 .
- the gate insulating layer 120 may include a silicon oxide (SiOx).
- the gate insulating layer 120 may include a silicon nitride (SiNx).
- the gate insulating layer 120 may have a single layer structure. Alternatively, the gate insulating layer 120 may have a multi layer structure.
- the gate insulating layer 120 may include a first layer disposed on the gate electrode GE 1 and a second layer disposed on the first layer.
- the first layer may include the silicon nitride (SiNx).
- the second layer may include the silicon oxide (SiOx).
- the semiconductor layer 130 is disposed on the gate insulating layer 120 .
- the semiconductor layer 130 overlaps with the gate electrode GE 1 .
- the semiconductor layer 130 functions as a channel layer of the TFT TR 1 .
- the semiconductor layer 130 may include an amorphous silicon semiconductor.
- the semiconductor layer 130 may include an active layer and an ohmic contact layer.
- the active layer may include the amorphous silicon.
- the ohmic contact layer may include an amorphous silicon doped with a dopant.
- the semiconductor layer 130 may include an oxide semiconductor.
- the semiconductor layer 130 may include at least one of a zinc oxide, a tin oxide, a gallium indium zinc (Ga—In—Zn) oxide, an indium zinc (In—Zn) oxide, a indium tin (In—Sn) oxide, indium tin zinc (In—Sn—Zn) oxide and so on.
- the semiconductor layer 130 may include an oxide semiconductor doped with a metal such as aluminum (Al), nickel (Ni), copper (Cu), tantalum (Ta), molybdenum (Mo), hafnium (Hf), titanium (Ti), niobium (Nb), chromium (Cr), and tungsten (W).
- the present invention is not limited to a material of the oxide semiconductor.
- the graphene pattern 140 is disposed on the semiconductor layer 130 .
- the source electrode SE 1 and the drain electrode DE 1 are disposed on the graphene pattern 140 .
- the source electrode SE 1 overlaps with the semiconductor layer 130 .
- the drain electrode DE 1 overlaps with the semiconductor layer 130 .
- the drain electrode DE 1 is spaced apart from the source electrode SE 1 .
- each of the source electrode SE 1 and the drain electrode DE 1 may include aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti) and so on or an alloy thereof.
- Each of the source electrode SE 1 and the drain electrode DE 1 may include a transparent conductive material such as an indium tin oxide (ITO), an indium zinc oxide (IZO) and an aluminum doped zinc oxide (AZO).
- Each of the source electrode SE 1 and the drain electrode DE 1 may include a plurality of layers.
- Each of the source electrode SE 1 and the drain electrode DE 1 may include a first electrode layer making contact with the graphene pattern 140 and a second electrode layer making contact with the first electrode layer.
- the first electrode layer may include one of titanium (Ti), molybdenum (Mo), and an alloy thereof.
- the second electrode layer may include copper (Cu).
- the source electrode SE 1 and the drain electrode DE 1 make direct contact with the semiconductor layer 130 , cations of the source electrode SE 1 and the drain electrode DE 1 may diffuse into the semiconductor layer 130 .
- the source electrode SE 1 and the drain electrode DE 1 includes copper (Cu)
- a copper ion may diffuse into the semiconductor layer 130 .
- a characteristic of the semiconductor layer 130 is changed so that electrical stability and reliability of the TFT TR 1 may be decreased.
- a conductivity of the semiconductor layer 130 and a threshold voltage of the semiconductor layer 130 may be changed.
- a cation of the semiconductor layer 130 may be deposited at the source electrode SE 1 and the drain electrode DE.
- the semiconductor layer 130 includes an indium (In)
- the indium (In) may be deposited at the source electrode SE 1 and the drain electrode DE. Accordingly, wiring resistances of the source electrode SE 1 and the is drain electrode DE 1 may be increased.
- a portion of the graphene pattern 140 is disposed between the source electrode SE 1 and the semiconductor layer 130 to prevent an interfacial reaction between the source electrode SE 1 and the semiconductor layer 130 .
- Another portion of the graphene pattern 140 is disposed between the drain electrode DE 1 and the semiconductor layer 130 to prevent an interfacial reaction between the drain electrode DE 1 and the semiconductor layer 130 .
- the graphene pattern 140 has a relatively high conductivity so that the graphene pattern 140 functions as a portion of the source electrode SE 1 and the drain electrode DE. In addition, the graphene pattern 140 functions as a barrier preventing the source electrode SE 1 and the drain electrode DE 1 from reacting with the semiconductor layer 130 .
- the graphene pattern 140 is disposed between the source electrode SE 1 and the semiconductor layer 130 and between the drain electrode DE 1 and the semiconductor layer 130 so that an electrical stability and a reliability of the TFT TR 1 may be improved.
- the TFT TR 1 may further include a second graphene pattern 160 disposed on the source electrode SE 1 and the drain electrode DE 1 and a passivation layer 170 disposed on the second graphene pattern 160 .
- the passivation layer 170 may be disposed in an entire area of the base substrate 110 .
- the passivation layer 170 may include a silicon oxide (SiOx) and/or a silicon nitride (SiNx).
- the passivation layer 170 may have a single layer structure. Alternatively, the passivation layer 170 may have a multi layer structure.
- the passivation layer 170 may include a first layer disposed on the second graphene pattern 160 and a second layer disposed on the first layer.
- the first layer may include the silicon oxide (SiOx).
- the second layer may include the silicon nitride (SiNx).
- the passivation layer 170 may be lifted off from the source electrode SE 1 and the drain electrode DE 1 due to an interfacial reaction between the passivation layer 170 and the source electrode SE 1 and the drain electrode DE 1 .
- the source electrode SE 1 and the drain electrode DE 1 includes copper (Cu) and the passivation layer includes a silicon oxide (SiOx)
- the copper (Cu) and the silicon oxide (SiOx) react with each other.
- a copper oxide (CuOx) is generated, and the passivation layer may be lifted off from the source electrode SE 1 and the drain electrode DE 1 .
- a portion of the second graphene pattern 160 is disposed between the source electrode SE 1 and the passivation layer 170 to prevent an interfacial reaction between the source electrode SE 1 and the passivation layer 170 .
- Another portion of the second graphene pattern 160 is disposed between the drain electrode DE 1 and the passivation layer 170 to prevent an interfacial reaction between the drain electrode DE 1 and the passivation layer 170 .
- the second graphene pattern 160 is disposed between the source electrode SE 1 and the passivation layer 170 and between the drain electrode DE 1 and the passivation layer 170 so that a productivity and a reliability of the TFT TR 1 may be improved.
- the passivation layer 170 includes a silicon oxide (SiOx)
- the passivation layer is not lifted off from the source electrode SE 1 and the drain electrode DE 1 due to the second graphene pattern 160 .
- an etch stopper protecting the oxide semiconductor may be omitted. Therefore, a process of manufacturing the TFT TR 1 may be simplified and a manufacturing cost of the TFT TR 1 may be decreased.
- a contact hole CNT is formed through the passivation layer 170 .
- the drain electrode DE 1 is exposed through the contact hole CNT.
- the pixel electrode 180 is electrically connected to the drain electrode DE 1 through the contact hole CNT.
- the pixel electrode 180 may include a transparent conductive material such as an indium tin oxide (ITO), an indium zinc oxide (IZO) and an aluminum doped zinc oxide (AZO).
- FIGS. 3A to 3D are cross-sectional views illustrating a method of manufacturing the array substrate of FIG. 1 .
- FIGS. 3A to 3D the method of manufacturing the array substrate may be explained in detail referring to FIGS. 3A to 3D .
- a gate electrode layer is formed on the base substrate 110 .
- the gate electrode GE 1 is formed by patterning the gate electrode layer.
- the gate electrode layer may be patterned by a photo lithography method.
- the gate electrode layer may be patterned using a first mask.
- the gate insulating layer 120 is formed on the gate electrode GE 1 .
- the gate insulating layer 120 may have an upper surface having a protruding portion corresponding to the gate electrode GE 1 .
- the gate insulating layer 120 may have a planar upper surface.
- the semiconductor layer 130 is formed on the gate insulating layer 120 .
- a graphene layer 140 is formed on the semiconductor layer 130 .
- a source-drain electrode layer 150 is formed on the graphene layer 140 .
- a second graphene layer 160 is formed on the source-drain electrode layer 150 .
- the second graphene layer 160 may be omitted according to whether the source-drain electrode layer 150 reacts with the passivation layer 170 .
- the graphene layer 140 may be directly deposited on the semiconductor layer 130 .
- the graphene of the graphene layer 140 may be directly grown on the semiconductor layer 130 .
- the graphene should be grown in a relatively low temperature to prevent damage to elements on the array substrate.
- the graphene may be grown in a temperature under 400 degrees Celsius.
- the graphene may be grown off of the array substrate and be transferred on the semiconductor layer 130 to form the graphene layer 140 .
- the graphene may be grown at a relatively high temperature.
- a quality of the graphene layer 140 may be improved.
- the graphene may be grown at a temperature of about 1000 degrees Celsius.
- the second graphene layer 160 may be directly grown on the source-drain electrode layer 150 .
- the graphene of the second graphene layer 160 may be grown off of the array substrate and be transferred on the source-drain electrode layer 150 to form the second graphene layer 160 .
- the second graphene layer 160 , the source-drain electrode layer 150 and the graphene layer 140 are sequentially patterned so that the second graphene pattern 160 , the source electrode SE 1 , the drain electrode DE 1 and the graphene pattern 140 are formed.
- the second graphene layer 160 , the source-drain electrode layer 150 and the graphene layer 140 may be patterned using a second mask.
- the semiconductor layer 130 may be patterned using the second mask.
- the semiconductor layer 130 may be patterned using an additional mask prior to a second mask process.
- a portion of the second graphene layer 160 may be ashed by an oxygen plasma ashing method to form the second graphene pattern 160 .
- a portion of the second graphene layer 160 between the source electrode SE 1 and the drain electrode DE 1 may be removed.
- a portion of the source-drain electrode layer 150 is etched to form the source electrode SE 1 and the drain electrode DE 1 .
- the source-drain electrode layer 150 may be etched by a dry etching method.
- the source-drain electrode layer 150 may be etched by a wet etching method.
- a portion of the graphene layer 140 may be ashed by the oxygen plasma ashing method to form the graphene pattern 140 .
- a portion of the graphene layer 140 between the source electrode SE 1 and the drain electrode DE 1 may be removed.
- the graphene layer 140 and the source-drain electrode layer 150 have different etching characteristics. Thus, when the source-drain electrode layer 150 is etched, the graphene layer 140 is not easily damaged. Accordingly, although the source-drain electrode layer 150 is etched for a long time, the semiconductor layer 130 may be protected by the graphene layer 140 . In addition, the graphene layer 140 is removed by the oxygen plasma ashing in a short time so that the semiconductor layer 130 may not be damaged.
- the second graphene layer 160 is deposited or transferred in an entire area of the source-drain electrode layer 150 , and then a portion of the second graphene layer 160 is ashed to form the second graphene pattern 160 . Accordingly, the second graphene pattern 160 covers an upper surface of the source electrode SE 1 and an upper surface of the drain electrode DE 1 .
- the source-drain electrode layer 150 is etched to form the source electrode SE 1 and the drain electrode DE 1 , and then graphene may be selectively grown on the source electrode SE 1 and the drain electrode DE 1 to form the second graphene pattern 160 .
- the second graphene pattern 160 may cover an upper surface and a side surface of is the source electrode SE 1 and an upper surface and a side surface of the drain electrode DE 1
- the passivation layer 170 is formed on the second graphene pattern 160 and the semiconductor layer 130 .
- the contact hole CNT is formed through the passivation layer 170 .
- the contact hole CNT may be formed using a third mask.
- the drain electrode DE 1 is exposed through the contact hole CNT.
- the pixel electrode 180 is formed on the passivation layer 170 .
- the pixel electrode 180 may be formed using a fourth mask.
- the pixel electrode 180 makes contact with the drain electrode DE 1 through the contact hole CNT.
- the graphene pattern 140 is disposed between the source electrode SE 1 and the semiconductor layer 130 and between the drain electrode DE 1 and the semiconductor layer 130 so that an electrical stability and a reliability of the TFT TR 1 may be improved.
- the second graphene pattern 160 is formed between the source electrode SE 1 and the passivation layer 170 and between the drain electrode DE 1 and the passivation layer 170 so that a productivity and a reliability of the TFT TR 1 may be improved.
- an etch stopper protecting the oxide semiconductor may be omitted so that a process of manufacturing the TFT TR 1 may be simplified and a manufacturing cost of the TFT TR 1 may be decreased.
- the semiconductor layer 130 may not be damaged.
- FIG. 4 is a cross-sectional view of an array substrate according to another exemplary embodiment of the present invention.
- the array substrate of the present exemplary embodiment is substantially the same as the array substrate in FIGS. 1 to 3D except that the array substrate further includes an etch stopper protecting a semiconductor layer.
- the array substrate further includes an etch stopper protecting a semiconductor layer.
- a TFT TR 2 includes a gate electrode GE 2 , a gate insulating layer 220 , a semiconductor layer 230 , an etch stopper 240 , a graphene pattern 250 , a source electrode SE 2 and a drain electrode DE 2 .
- the gate electrode GE 2 is disposed on a base substrate 210 .
- the gate electrode GE 2 may include a metal, an alloy or a transparent conductive material.
- the gate electrode GE 2 may have a single layer structure.
- the gate electrode GE 2 may have a multi layer structure which includes a plurality of conductive layers or at least one of conductive layers and at least one of insulating layers.
- the gate insulating layer 220 is disposed on the gate electrode GE 2 .
- the gate insulating layer 220 insulates the gate electrode GE 2 from the semiconductor layer 230 .
- the gate insulating layer 220 may include a silicon oxide (SiOx) and/or a silicon nitride (SiNx).
- the gate insulating layer 220 may include a first layer disposed on the gate electrode GE 2 and a second layer disposed on the first layer.
- the first layer may include the silicon nitride (SiNx).
- the second layer may include the silicon oxide (SiOx).
- the semiconductor layer 230 is disposed on the gate insulating layer 220 .
- the semiconductor layer 230 overlaps with the gate electrode GE 2 .
- the semiconductor layer 230 functions as a channel layer of the TFT TR 2 .
- the semiconductor layer 230 includes an oxide semiconductor.
- the semiconductor layer 230 may include at least one of a zinc oxide, a tin oxide, a gallium indium zinc (Ga—In—Zn) oxide, an indium zinc (In—Zn) oxide, a indium tin (In—Sn) oxide, indium tin zinc (In—Sn—Zn) oxide and so on.
- the etch stopper 240 is disposed on the semiconductor layer 230 .
- the etch stopper overlaps with a portion of the semiconductor layer 230 corresponding to an area between the source electrode SE 2 and the drain electrode DE 2 .
- the etch stopper 240 prevents the oxide semiconductor from making contact with the passivation layer 270 so that a characteristic of the oxide semiconductor is not changed.
- the etch stopper 240 includes a silicon oxide (SiOx).
- the etch stopper 240 may have a single layer structure or a multi layer structure.
- the graphene pattern 250 is disposed on the semiconductor layer 230 and the etch stopper 240 .
- the source electrode SE 2 and the drain electrode DE 2 are disposed on the graphene pattern 250 .
- the source electrode SE 2 overlaps with the semiconductor layer 230 .
- the drain electrode DE 2 overlaps with the semiconductor layer 230 .
- the drain electrode DE 2 is spaced apart from the source electrode SE 2 .
- each of the source electrode SE 2 and the drain electrode DE 2 may include aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti) and so on, or an alloy thereof.
- Each of the source electrode SE 2 and the drain electrode DE 2 may include a transparent conductive material such as an indium tin oxide (ITO), an indium zinc oxide (IZO) and an aluminum doped zinc oxide (AZO).
- Each of the source electrode SE 2 and the drain electrode DE 2 may include a plurality of layers.
- Each of the source electrode SE 2 and the drain electrode DE 2 may include a first electrode layer making contact with the graphene pattern 250 and a second electrode layer making contact with the first electrode layer.
- the first electrode layer may include one of titanium (Ti), molybdenum (Mo) and an alloy thereof.
- the second electrode layer may include copper (Cu).
- a portion of the graphene pattern 250 is disposed between the source electrode SE 2 and the semiconductor layer 230 to prevent an interfacial reaction between the source electrode SE 2 and the semiconductor layer 230 .
- Another portion of the graphene pattern 250 is disposed between the drain electrode DE 2 and the semiconductor layer 230 to prevent an interfacial reaction between the drain electrode DE 2 and the semiconductor layer 230 . Accordingly, an electrical stability and a reliability of the TFT TR 2 may be improved.
- the TFT TR 2 may further include a passivation layer 270 disposed on the source electrode SE 2 and the drain electrode DE 2 .
- the passivation layer 270 may be disposed in an entire area of the base substrate 210 .
- the passivation layer 270 may include a silicon nitride (SiNx).
- the passivation layer 270 may have a single layer structure or a multi layer structure.
- a contact hole CNT is formed through the passivation layer 270 .
- the drain electrode DE 2 is exposed through the contact hole CNT.
- a pixel electrode 280 is electrically connected to the drain electrode DE 2 through the contact hole CNT.
- the pixel electrode 280 may include a transparent conductive material such as an indium tin oxide (ITO), an indium zinc oxide (IZO) and an aluminum doped zinc oxide (AZO).
- FIGS. 5A to 5E are cross-sectional views illustrating a method of manufacturing the array substrate of FIG. 4 .
- FIGS. 5A to 5E the method of manufacturing the array substrate may be explained in detail referring to FIGS. 5A to 5E .
- a gate electrode layer is formed on the base substrate 210 .
- the gate electrode GE 2 is formed by patterning the gate electrode layer.
- the gate electrode layer may be patterned by a photo lithography method.
- the gate electrode layer may be patterned using a first mask.
- the gate insulating layer 220 is formed on the gate electrode GE 2 .
- the semiconductor layer 230 is formed on the gate insulating layer 220 .
- the etch stopper 240 is formed on the semiconductor layer 230 .
- the semiconductor layer 230 may be patterned using a second mask.
- the etch stopper 240 may be formed using a third mask.
- a graphene layer 250 is formed on the semiconductor layer 230 and the etch stopper 240 .
- a source-drain electrode layer 260 is formed on the graphene layer 250 .
- the graphene layer 250 may be directly deposited on the semiconductor layer 230 and the etch stopper 240 .
- a graphene of the graphene layer 250 may be directly grown on the semiconductor layer 230 and the etch stopper 240 .
- the graphene may be grown off of the array substrate and be transferred on the semiconductor layer 230 and the etch stopper 240 to form the graphene layer 250 .
- the source-drain electrode layer 260 and the graphene layer 250 are sequentially patterned so that the source electrode SE 2 , the drain electrode DE 2 and the graphene pattern 250 are formed.
- the source-drain electrode layer 260 and the graphene layer 250 may be patterned using a fourth mask.
- a portion of the source-drain electrode layer 260 is etched to form the source electrode SE 2 and the drain electrode DE 2 .
- the source-drain electrode layer 260 may be etched by a dry etching method.
- the source-drain electrode layer 260 may be etched by a wet etching method.
- a portion of the graphene layer 250 may be ashed by the oxygen plasma ashing method to form the graphene pattern 250 .
- a portion of the graphene layer 250 between the source electrode SE 2 and the drain electrode DE 2 may be removed.
- the graphene layer 250 and the source-drain electrode layer 260 have different etching characteristics. Thus, when the source-drain electrode layer 260 is etched, the graphene layer 250 is not easily damaged. Accordingly, although the source-drain electrode layer 260 is etched for a long time, the semiconductor layer 230 may be protected by the graphene layer 250 . In addition, the graphene layer 250 is removed by the oxygen plasma ashing in a short time so that the semiconductor layer 230 may not be damaged.
- the passivation layer 270 is formed on the source electrode SE 2 , the drain electrode DE 2 and the etch stopper 240 .
- the contact hole CNT is formed through the passivation layer 270 .
- the contact hole CNT may be formed using a fifth mask.
- the drain electrode DE 2 is exposed through the contact hole CNT.
- the pixel electrode 280 is formed on the passivation layer 270 .
- the pixel electrode 280 may be formed using a sixth mask.
- the pixel electrode 280 makes contact with the drain electrode DE 2 through the contact hole CNT.
- the graphene pattern 250 is disposed between the source electrode SE 2 and the semiconductor layer 230 and between the drain electrode DE 2 and the semiconductor layer 230 so that an electrical stability and a reliability of the TFT TR 2 may be improved.
- the semiconductor layer 230 may not be damaged.
- FIG. 6 is a cross-sectional view of an array substrate according to still another exemplary embodiment of the present invention.
- FIG. 7 is a cross-sectional view illustrating a method of manufacturing the array substrate of FIG. 6 .
- the array substrate of the present exemplary embodiment is substantially the same as the array substrate in FIGS. 1 to 3D , except that the array substrate includes a vertical TFT including a semiconductor layer disposed in a vertical direction.
- the array substrate includes a vertical TFT including a semiconductor layer disposed in a vertical direction.
- a TFT TR 3 includes a source electrode SE 3 , an insulating layer 320 , a drain electrode DE 3 , a graphene pattern 330 , a semiconductor layer 340 , a gate insulating layer 350 and a gate electrode GE 3 .
- the source electrode SE 3 is disposed on a base substrate 310 .
- the source electrode SE 3 overlaps with the semiconductor layer 340 .
- the source electrode SE 3 may include one of aluminum (Al), copper (Cu), molybdenum (Mo) and titanium Ti or an alloy thereof.
- the source electrode SE 3 may include a transparent conductive material such as an indium tin oxide (ITO), an indium zinc oxide (IZO) or an aluminum doped zinc oxide (AZO).
- the source electrode SE 3 may have a single layer structure.
- the source electrode SE 3 may have a multi layer structure which includes a plurality of conductive layers or at least one of conductive layers and at least one of insulating layers.
- the insulating layer 320 is disposed on the source electrode SE 3 .
- the insulating layer 320 insulates the source electrode SE 3 from the drain electrode DE 3 .
- the insulating layer 320 may include a silicon oxide (SiOx).
- the insulating layer 320 may include a silicon nitride (SiNx).
- the insulating layer 320 may have a single layer structure or a multi layer structure.
- the drain electrode DE 3 is disposed on the insulating layer 320 .
- the drain electrode DE 3 overlaps with the semiconductor layer 340 .
- the drain electrode DE 3 is spaced apart from the source electrode SE 3 .
- the drain electrode DE 3 may include one of aluminum (Al), copper (Cu), molybdenum (Mo) and titanium Ti or an alloy thereof.
- the drain electrode DE 3 may include a transparent conductive material such as an indium tin oxide (ITO), an indium zinc oxide (IZO) or an aluminum doped zinc oxide (AZO).
- the drain electrode DE 3 may have a single layer structure.
- the drain electrode DE 3 may have a multi layer structure which includes a plurality of conductive layers or at least one of conductive layers and at least one of insulating layers.
- the drain electrode DE 3 may include a plurality of electrode layers.
- the drain electrode DE 3 may include a first electrode layer making contact with the graphene pattern 330 and a second electrode layer making contact with the first electrode layer.
- the first electrode layer may include one of titanium (Ti), molybdenum (Mo) and an alloy thereof.
- the second electrode layer may include copper (Cu).
- the graphene pattern 330 is disposed on the drain electrode DE 3 .
- the graphene pattern 330 covers an upper surface and a side surface of the drain electrode DE 3 .
- a portion of the semiconductor layer 340 corresponding to the upper surface of the drain electrode DE 3 is etched.
- a portion of the semiconductor layer 340 corresponding to the side surface of the drain electrode DE 3 remains. Accordingly, a portion of the graphene pattern 330 is disposed between the drain electrode DE 3 and the semiconductor layer 340 .
- Another portion of the graphene pattern 330 is disposed between the drain electrode DE 3 and the gate insulating layer 350 .
- the semiconductor layer 340 extends in a vertical direction according to a side surface of the insulating layer 320 to connect the source electrode SE 3 to the drain electrode DE 3 .
- the semiconductor layer 340 functions as a channel layer of the TFT TR 3 .
- the semiconductor layer 340 may include an amorphous silicon semiconductor.
- the semiconductor layer 340 may include an oxide semiconductor.
- the semiconductor layer 340 entirely overlaps with the drain electrode DE 3 in a process of manufacturing the semiconductor layer 340 .
- the semiconductor layer 340 makes direct contact with the drain electrode DE 3 , a characteristic of the semiconductor layer 340 is changed due to an interfacial reaction between the semiconductor layer 340 and the drain electrode DE 3 so that an electrical stability and a reliability of the TFT TR 3 may be decreased.
- the semiconductor layer 340 may be lifted off from the drain electrode DE 3 due to the interfacial reaction between the semiconductor layer 340 and the drain electrode DE 3 .
- the graphene pattern 330 is disposed between the drain electrode DE 3 and the semiconductor layer 340 in the process of manufacturing the semiconductor layer 340 so that the graphene pattern 330 prevents the interfacial reaction between the semiconductor layer 340 and the drain electrode DE 3 .
- an electrical stability and a reliability of the TFT TR 3 may be improved.
- a productivity and a reliability of the TFT TR 3 may be improved.
- the gate insulating layer 350 is disposed on the graphene pattern 330 and the semiconductor layer 340 .
- the gate insulating layer 350 insulates the gate electrode GE 3 from the semiconductor layer 340 .
- the gate insulating layer 350 may include a silicon oxide (SiOx).
- the gate insulating layer 350 may include a silicon nitride (SiNx).
- the gate insulating layer 350 may have a single layer structure or a multi layer structure.
- the gate insulating layer 350 When the gate insulating layer 350 makes direct contact with the drain electrode DE 3 , the gate insulating layer 350 may be lifted off from the drain electrode DE 3 due to an interfacial reaction between the drain electrode DE 3 and the gate insulating layer 350 .
- a portion of the graphene 330 is disposed between the drain electrode DE 3 and the gate insulating layer 350 to prevent the interfacial reaction between the drain electrode DE 3 and the gate insulating layer 350 .
- a productivity and a reliability of the TFT TR 3 may be improved.
- the gate electrode GE 3 is disposed on the gate insulating layer 350 .
- the gate electrode GE 3 overlaps with the semiconductor layer 340 .
- the gate electrode GE 3 may include one of aluminum (Al), copper (Cu), molybdenum (Mo) and titanium Ti or an alloy thereof.
- the gate electrode GE 3 may include a transparent conductive material, such as an indium tin oxide (ITO), an indium zinc oxide (IZO) or an aluminum doped zinc oxide (AZO).
- the gate electrode GE 3 may have a single layer structure.
- the gate electrode GE 3 may have a multi layer structure which includes a plurality of conductive layers or at least one of conductive layers and at least one of insulating layers.
- the insulating layer 320 When the insulating layer 320 makes direct contact with the source electrode SE 3 , the insulating layer 320 may be lifted off from the source electrode SE 3 due to an interfacial reaction between the source electrode SE 3 and the insulating layer 320 .
- the drain electrode DE 3 When the drain electrode DE 3 makes direct contact with the insulating layer 320 , the drain electrode DE 3 may be lifted off from the insulating layer 320 due to an interfacial reaction between the insulating layer 320 and the drain electrode DE 3 .
- the second graphene pattern prevents the interfacial reaction between the source electrode SE 3 and the insulating layer 320 .
- the third graphene pattern prevents the interfacial reaction between the insulating layer 320 and the drain electrode DE 3 .
- a productivity and a reliability of the TFT TR 3 may be improved.
- an ohmic contact layer may be formed between the source electrode SE 3 and the insulating layer 320 and between the insulating layer 320 and the drain electrode DE 3 .
- the ohmic contact layer may include an amorphous silicon doped with a dopant.
- the graphene pattern 330 is disposed between the drain electrode DE 3 and the semiconductor layer 340 so that an electrical stability, a productivity and a reliability of the TFT TR 3 may be improved.
- the graphene pattern 330 is disposed between the drain electrode DE 3 and the gate insulating layer 350 so that a productivity and a reliability of the TFT TR 3 may be improved.
- FIG. 8 is a cross-sectional view of an array substrate according to still another exemplary embodiment of the present invention.
- the array substrate of the present exemplary embodiment is substantially the same as the array substrate in FIGS. 6 and 7 , except that the array substrate further includes a second graphene pattern and a third graphene pattern.
- the array substrate further includes a second graphene pattern and a third graphene pattern.
- a TFT TR 4 includes a source electrode SE 3 , an insulating layer 320 , a drain electrode DE 3 , a graphene pattern 330 , a semiconductor layer 340 , a gate insulating layer 350 , a gate electrode GE 3 , a second graphene pattern 360 and a third graphene pattern 370 .
- the second graphene pattern 360 is disposed between the source electrode SE 3 and the insulating layer 320 .
- the third graphene pattern 370 is disposed between the drain electrode DE 3 and the insulating layer 320 .
- the graphene pattern 330 is disposed between the drain electrode DE 3 and the semiconductor layer 340 so that an electrical stability, a productivity and a reliability of the TFT TR 4 may be improved.
- the graphene pattern 330 is disposed between the drain electrode DE 3 and the gate insulating layer 350 so that a productivity and a reliability of the TFT TR 4 may be improved.
- the second and third graphene patterns 360 and 370 are respectively disposed between the source electrode SE 3 and the insulating layer 320 and between the drain electrode DE 3 and the insulating layer 320 so that a productivity and a reliability of the TFT TR 4 may be improved.
- the graphene pattern prevents at least one of the source electrode and the drain electrode from reacting with the semiconductor layer so that an electrical stability and a reliability of the TFT may be improved.
- the graphene pattern also prevents at least one of the source electrode and the drain electrode from reacting with the passivation layer so that a process of manufacturing the TFT may be simplified and a manufacturing cost of the TFT may be decreased.
Abstract
Description
- This application claims priority from and the benefit of Korean Patent Application No. 2011-62865, filed on Jun. 28, 2011, which is hereby incorporated by reference for all purposes as if fully set forth herein.
- 1. Field of the Invention
- Exemplary embodiments of the present invention relate to a thin film transistor and a method of manufacturing the thin film transistor. More particularly, exemplary embodiments of the present invention relate to a thin film transistor having improved electrical stability and a method of manufacturing the thin film transistor.
- 2. Description of the Background
- Generally, a display apparatus includes an array substrate including a switching element and an opposite substrate facing the array substrate. The switching element includes a gate electrode electrically connected to a gate line, a semiconductor layer insulated from the gate electrode, a source electrode electrically connected to a data line and the semiconductor layer, and a drain electrode spaced apart from the source electrode and electrically connected to the semiconductor layer.
- For example, the types of switching elements for the display apparatus may be divided into an amorphous silicon thin film transistor (“TFT”), a poly silicon TFT, and an oxide semiconductor TFT.
- The amorphous silicon TFT is uniformly formed on a large substrate in a low manufacturing cost. However, the amorphous silicon TFT has a relatively low charge carrier mobility. The poly silicon TFT has a charge carrier mobility higher than the amorphous silicon TFT, and a deterioration of a characteristic of the poly silicon TFT is less than the amorphous silicon TFT. However, a process of manufacturing the poly silicon TFT is complicated so that a manufacturing cost is high. The oxide semiconductor TFT may be manufactured in a low temperature process, may be formed in a large area, and may have a relatively high charge carrier mobility.
- In a process of manufacturing the switching element, when the source electrode and the drain electrode react with the semiconductor layer, a conductive characteristic of the semiconductor layer may be changed. In addition, when the oxide semiconductor reacts with the source electrode and the drain electrode, a cation included in the oxide semiconductor may be deposited so that a wiring resistance may increase. Thus, the electrical stability and reliability of the switching element may decrease.
- In addition, when the source electrode and the drain electrode react with an insulating layer or a passivation layer, the insulating layer or a passivation layer may be lifted off from the source electrode and the drain electrode. Particularly, when the insulating layer or the passivation layer of the oxide silicon TFT includes an oxide silicon, the insulating layer or the passivation layer may be lifted off more frequently and more seriously.
- The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form any part of the prior art nor what the prior art may suggest to a person of ordinary skill in the art.
- Exemplary embodiments of the present invention provide a thin film transistor (“TFT”) capable of improving an electrical stability and a reliability using a graphene pattern.
- Exemplary embodiments of the present invention also provide a method of manufacturing the TFT.
- In an exemplary embodiment of a TFT according to the present invention, the TFT includes a gate electrode, a semiconductor layer, a gate insulating layer, a source electrode, a drain electrode and a graphene pattern. The semiconductor layer overlaps with the gate electrode. The gate insulating layer is disposed between the gate electrode and the semiconductor layer. The source electrode overlaps with the semiconductor layer. The drain electrode overlaps with the semiconductor layer. The drain electrode is spaced apart from the source electrode. The graphene pattern is disposed between the semiconductor layer and at least one of the source electrode and the drain electrode.
- In an exemplary embodiment of a method of manufacturing a TFT according to the present invention, the method includes forming a gate electrode on a base substrate, forming a gate insulating layer on the gate electrode, forming a semiconductor layer overlapping with the gate electrode on the gate insulating layer, forming a graphene layer on the semiconductor layer, forming a source electrode and a drain electrode on the graphene layer and patterning the graphene layer between the source and drain electrodes to form a graphene pattern.
- In an exemplary embodiment of a method of manufacturing a TFT according to the present invention, the method includes forming a source electrode on a base substrate, forming an insulating layer on the source electrode, forming a drain electrode on the insulating layer, forming a graphene pattern on the drain electrode, forming a semiconductor layer on the graphene pattern, patterning the semiconductor layer, forming a gate insulating layer on the semiconductor layer and forming a gate electrode on the gate insulating layer.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the principles of the invention.
-
FIG. 1 is a plan view of an array substrate according to an exemplary embodiment of the present invention. -
FIG. 2 is a cross-sectional view taken along a line I-I′ ofFIG. 1 . -
FIG. 3A ,FIG. 3B ,FIG. 3C , andFIG. 3D are cross-sectional views illustrating an exemplary embodiment of a method of manufacturing the array substrate ofFIG. 1 . -
FIG. 4 is a cross-sectional view of an array substrate according to another exemplary embodiment of the present invention. -
FIG. 5A ,FIG. 5B ,FIGS. 5C , 5D, and 5E are cross-sectional views illustrating a method of manufacturing the array substrate ofFIG. 4 . -
FIG. 6 is a cross-sectional view of an array substrate according to still another exemplary embodiment of the present invention. -
FIG. 7 is a cross-sectional view illustrating a method of manufacturing the array substrate ofFIG. 6 . -
FIG. 8 is a cross-sectional view of an array substrate according to still another exemplary embodiment of the present invention. - Hereinafter, exemplary embodiments of the present invention will be described in further detail with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like elements.
- It will be understood that when an element or layer is referred to as being “on” or “connected to” another element or layer, it can be directly on or directly connected to the other element or layer, or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there are no intervening elements or layers present. It will be understood that for the purposes of this disclosure, “at least one of X, Y, and Z” can be construed as X only, Y only, Z only, or any combination of two or more items X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ).
-
FIG. 1 is a plan view of an array substrate according to an exemplary embodiment of the present invention. - Referring to
FIG. 1 , the array substrate includes a gate line GL formed on a base substrate, a data line DL, a thin film transistor (“TFT”) TR1 and apixel electrode 180. - The gate line GL may extend in a first direction. The array substrate may include a plurality of the gate lines GL. The data line DL may extend in a second direction crossing the first direction. The array substrate may include a plurality of the data lines DL.
- The TFT TR1 is electrically connected to the gate line GL and the data line DL. The TFT TR1 may be disposed in an area where the gate line GL and the data line DL cross with each other.
- The TFT TR1 includes a gate electrode GE1, a source electrode SE1 and a drain electrode DE1. The gate electrode GE1 may be electrically connected to the gate line GL.
- For example, the gate electrode GE1 may be formed integrally with the gate line GL. The gate electrode GE1 may be a protruded portion from the gate line GL.
- The source electrode SE1 may be formed integrally with the data line DL. The source electrode SE1 may be a protruded portion from the data line DL.
- The TFT TR1 is explained in detail referring to
FIG. 2 . - The
pixel electrode 180 is electrically connected to the TFT TR1. When the TFT TR1 is turned on, a data voltage applied to the data line DL is transmitted to thepixel electrode 180. -
FIG. 2 is a cross-sectional view taken along line I-I′ ofFIG. 1 . - Referring to
FIGS. 1 and 2 , the TFT TR1 includes the gate electrode GE1, agate insulating layer 120, asemiconductor layer 130, agraphene pattern 140, the source electrode SE1 and the drain electrode DE1 - The gate electrode GE1 is disposed on the
base substrate 110. For example, the gate electrode GE1 may include one of aluminum (Al), copper (Cu), molybdenum (Mo) and titanium Ti or an alloy thereof. For example, the gate electrode GE1 may include a transparent conductive material such as an indium tin oxide (ITO), an indium zinc oxide (IZO) and an aluminum doped zinc oxide (AZO). The present invention is not limited to a material of the gate electrode GE1. - The gate electrode GE1 may have a single layer structure. Alternatively, the gate electrode GE1 may have a multi layer structure which includes a plurality of conductive layers or at least one of conductive layers and at least one of insulating layers.
- The
gate insulating layer 120 is disposed on the gate electrode GE1. Thegate insulating layer 120 insulates the gate line GL from the data line DL. In addition, thegate insulating layer 120 insulates the gate electrode GE1 from thesemiconductor layer 130. Thegate insulating layer 120 may be disposed in an entire area of thebase substrate 110. - For example, the
gate insulating layer 120 may include a silicon oxide (SiOx). For example, thegate insulating layer 120 may include a silicon nitride (SiNx). - The
gate insulating layer 120 may have a single layer structure. Alternatively, thegate insulating layer 120 may have a multi layer structure. For example, thegate insulating layer 120 may include a first layer disposed on the gate electrode GE1 and a second layer disposed on the first layer. The first layer may include the silicon nitride (SiNx). The second layer may include the silicon oxide (SiOx). - The
semiconductor layer 130 is disposed on thegate insulating layer 120. Thesemiconductor layer 130 overlaps with the gate electrode GE1. Thesemiconductor layer 130 functions as a channel layer of the TFT TR1. - The
semiconductor layer 130 may include an amorphous silicon semiconductor. Thesemiconductor layer 130 may include an active layer and an ohmic contact layer. The active layer may include the amorphous silicon. The ohmic contact layer may include an amorphous silicon doped with a dopant. - The
semiconductor layer 130 may include an oxide semiconductor. For example, thesemiconductor layer 130 may include at least one of a zinc oxide, a tin oxide, a gallium indium zinc (Ga—In—Zn) oxide, an indium zinc (In—Zn) oxide, a indium tin (In—Sn) oxide, indium tin zinc (In—Sn—Zn) oxide and so on. Thesemiconductor layer 130 may include an oxide semiconductor doped with a metal such as aluminum (Al), nickel (Ni), copper (Cu), tantalum (Ta), molybdenum (Mo), hafnium (Hf), titanium (Ti), niobium (Nb), chromium (Cr), and tungsten (W). The present invention is not limited to a material of the oxide semiconductor. - The
graphene pattern 140 is disposed on thesemiconductor layer 130. The source electrode SE1 and the drain electrode DE1 are disposed on thegraphene pattern 140. - The source electrode SE1 overlaps with the
semiconductor layer 130. The drain electrode DE1 overlaps with thesemiconductor layer 130. The drain electrode DE1 is spaced apart from the source electrode SE1. - For example, each of the source electrode SE1 and the drain electrode DE1 may include aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti) and so on or an alloy thereof. Each of the source electrode SE1 and the drain electrode DE1 may include a transparent conductive material such as an indium tin oxide (ITO), an indium zinc oxide (IZO) and an aluminum doped zinc oxide (AZO).
- Each of the source electrode SE1 and the drain electrode DE1 may include a plurality of layers. Each of the source electrode SE1 and the drain electrode DE1 may include a first electrode layer making contact with the
graphene pattern 140 and a second electrode layer making contact with the first electrode layer. For example, the first electrode layer may include one of titanium (Ti), molybdenum (Mo), and an alloy thereof. The second electrode layer may include copper (Cu). - When the source electrode SE1 and the drain electrode DE1 make direct contact with the
semiconductor layer 130, cations of the source electrode SE1 and the drain electrode DE1 may diffuse into thesemiconductor layer 130. For example, when the source electrode SE1 and the drain electrode DE1 includes copper (Cu), a copper ion may diffuse into thesemiconductor layer 130. Accordingly, a characteristic of thesemiconductor layer 130 is changed so that electrical stability and reliability of the TFT TR1 may be decreased. For example, a conductivity of thesemiconductor layer 130 and a threshold voltage of thesemiconductor layer 130 may be changed. - In addition, a cation of the
semiconductor layer 130 may be deposited at the source electrode SE1 and the drain electrode DE. For example, when thesemiconductor layer 130 includes an indium (In), the indium (In) may be deposited at the source electrode SE1 and the drain electrode DE. Accordingly, wiring resistances of the source electrode SE1 and the is drain electrode DE1 may be increased. - A portion of the
graphene pattern 140 is disposed between the source electrode SE1 and thesemiconductor layer 130 to prevent an interfacial reaction between the source electrode SE1 and thesemiconductor layer 130. Another portion of thegraphene pattern 140 is disposed between the drain electrode DE1 and thesemiconductor layer 130 to prevent an interfacial reaction between the drain electrode DE1 and thesemiconductor layer 130. - The
graphene pattern 140 has a relatively high conductivity so that thegraphene pattern 140 functions as a portion of the source electrode SE1 and the drain electrode DE. In addition, thegraphene pattern 140 functions as a barrier preventing the source electrode SE1 and the drain electrode DE1 from reacting with thesemiconductor layer 130. - The
graphene pattern 140 is disposed between the source electrode SE1 and thesemiconductor layer 130 and between the drain electrode DE1 and thesemiconductor layer 130 so that an electrical stability and a reliability of the TFT TR1 may be improved. - The TFT TR1 may further include a
second graphene pattern 160 disposed on the source electrode SE1 and the drain electrode DE1 and apassivation layer 170 disposed on thesecond graphene pattern 160. Thepassivation layer 170 may be disposed in an entire area of thebase substrate 110. - For example, the
passivation layer 170 may include a silicon oxide (SiOx) and/or a silicon nitride (SiNx). - The
passivation layer 170 may have a single layer structure. Alternatively, thepassivation layer 170 may have a multi layer structure. For example, thepassivation layer 170 may include a first layer disposed on thesecond graphene pattern 160 and a second layer disposed on the first layer. The first layer may include the silicon oxide (SiOx). The second layer may include the silicon nitride (SiNx). - When the
passivation layer 170 makes direct contact with the source electrode SE1 and the drain electrode DE1, thepassivation layer 170 may be lifted off from the source electrode SE1 and the drain electrode DE1 due to an interfacial reaction between thepassivation layer 170 and the source electrode SE1 and the drain electrode DE1. For example, when the source electrode SE1 and the drain electrode DE1 includes copper (Cu) and the passivation layer includes a silicon oxide (SiOx), the copper (Cu) and the silicon oxide (SiOx) react with each other. Thus, a copper oxide (CuOx) is generated, and the passivation layer may be lifted off from the source electrode SE1 and the drain electrode DE1. - A portion of the
second graphene pattern 160 is disposed between the source electrode SE1 and thepassivation layer 170 to prevent an interfacial reaction between the source electrode SE1 and thepassivation layer 170. Another portion of thesecond graphene pattern 160 is disposed between the drain electrode DE1 and thepassivation layer 170 to prevent an interfacial reaction between the drain electrode DE1 and thepassivation layer 170. - The
second graphene pattern 160 is disposed between the source electrode SE1 and thepassivation layer 170 and between the drain electrode DE1 and thepassivation layer 170 so that a productivity and a reliability of the TFT TR1 may be improved. - When the
semiconductor layer 130 includes an oxide semiconductor and thepassivation layer 170 includes a silicon oxide (SiOx), the passivation layer is not lifted off from the source electrode SE1 and the drain electrode DE1 due to thesecond graphene pattern 160. Thus, an etch stopper protecting the oxide semiconductor may be omitted. Therefore, a process of manufacturing the TFT TR1 may be simplified and a manufacturing cost of the TFT TR1 may be decreased. - A contact hole CNT is formed through the
passivation layer 170. The drain electrode DE1 is exposed through the contact hole CNT. Thepixel electrode 180 is electrically connected to the drain electrode DE1 through the contact hole CNT. Thepixel electrode 180 may include a transparent conductive material such as an indium tin oxide (ITO), an indium zinc oxide (IZO) and an aluminum doped zinc oxide (AZO). -
FIGS. 3A to 3D are cross-sectional views illustrating a method of manufacturing the array substrate ofFIG. 1 . - Hereinafter, the method of manufacturing the array substrate may be explained in detail referring to
FIGS. 3A to 3D . - Referring to
FIG. 3A , a gate electrode layer is formed on thebase substrate 110. The gate electrode GE1 is formed by patterning the gate electrode layer. The gate electrode layer may be patterned by a photo lithography method. The gate electrode layer may be patterned using a first mask. - The
gate insulating layer 120 is formed on the gate electrode GE1. Thegate insulating layer 120 may have an upper surface having a protruding portion corresponding to the gate electrode GE1. Alternatively, thegate insulating layer 120 may have a planar upper surface. - Referring to
FIG. 3B , thesemiconductor layer 130 is formed on thegate insulating layer 120. Agraphene layer 140 is formed on thesemiconductor layer 130. A source-drain electrode layer 150 is formed on thegraphene layer 140. Asecond graphene layer 160 is formed on the source-drain electrode layer 150. Thesecond graphene layer 160 may be omitted according to whether the source-drain electrode layer 150 reacts with thepassivation layer 170. - The
graphene layer 140 may be directly deposited on thesemiconductor layer 130. For example, the graphene of thegraphene layer 140 may be directly grown on thesemiconductor layer 130. When the graphene is directly grown on thesemiconductor layer 130, the graphene should be grown in a relatively low temperature to prevent damage to elements on the array substrate. For example, the graphene may be grown in a temperature under 400 degrees Celsius. - The graphene may be grown off of the array substrate and be transferred on the
semiconductor layer 130 to form thegraphene layer 140. When the graphene is grown off of the array substrate, the graphene may be grown at a relatively high temperature. Thus, a quality of thegraphene layer 140 may be improved. For example, the graphene may be grown at a temperature of about 1000 degrees Celsius. - Like the
graphene layer 140, thesecond graphene layer 160 may be directly grown on the source-drain electrode layer 150. The graphene of thesecond graphene layer 160 may be grown off of the array substrate and be transferred on the source-drain electrode layer 150 to form thesecond graphene layer 160. - Referring to
FIG. 3C , thesecond graphene layer 160, the source-drain electrode layer 150 and thegraphene layer 140 are sequentially patterned so that thesecond graphene pattern 160, the source electrode SE1, the drain electrode DE1 and thegraphene pattern 140 are formed. - The
second graphene layer 160, the source-drain electrode layer 150 and thegraphene layer 140 may be patterned using a second mask. Thesemiconductor layer 130 may be patterned using the second mask. Alternatively, thesemiconductor layer 130 may be patterned using an additional mask prior to a second mask process. - A portion of the
second graphene layer 160 may be ashed by an oxygen plasma ashing method to form thesecond graphene pattern 160. A portion of thesecond graphene layer 160 between the source electrode SE1 and the drain electrode DE1 may be removed. - A portion of the source-
drain electrode layer 150 is etched to form the source electrode SE1 and the drain electrode DE1. The source-drain electrode layer 150 may be etched by a dry etching method. The source-drain electrode layer 150 may be etched by a wet etching method. - A portion of the
graphene layer 140 may be ashed by the oxygen plasma ashing method to form thegraphene pattern 140. A portion of thegraphene layer 140 between the source electrode SE1 and the drain electrode DE1 may be removed. - The
graphene layer 140 and the source-drain electrode layer 150 have different etching characteristics. Thus, when the source-drain electrode layer 150 is etched, thegraphene layer 140 is not easily damaged. Accordingly, although the source-drain electrode layer 150 is etched for a long time, thesemiconductor layer 130 may be protected by thegraphene layer 140. In addition, thegraphene layer 140 is removed by the oxygen plasma ashing in a short time so that thesemiconductor layer 130 may not be damaged. - In the present exemplary embodiment, the
second graphene layer 160 is deposited or transferred in an entire area of the source-drain electrode layer 150, and then a portion of thesecond graphene layer 160 is ashed to form thesecond graphene pattern 160. Accordingly, thesecond graphene pattern 160 covers an upper surface of the source electrode SE1 and an upper surface of the drain electrode DE1. - Alternatively, the source-
drain electrode layer 150 is etched to form the source electrode SE1 and the drain electrode DE1, and then graphene may be selectively grown on the source electrode SE1 and the drain electrode DE1 to form thesecond graphene pattern 160. Accordingly, thesecond graphene pattern 160 may cover an upper surface and a side surface of is the source electrode SE1 and an upper surface and a side surface of the drain electrode DE1 - Referring to
FIG. 3D , thepassivation layer 170 is formed on thesecond graphene pattern 160 and thesemiconductor layer 130. The contact hole CNT is formed through thepassivation layer 170. The contact hole CNT may be formed using a third mask. The drain electrode DE1 is exposed through the contact hole CNT. - The
pixel electrode 180 is formed on thepassivation layer 170. Thepixel electrode 180 may be formed using a fourth mask. Thepixel electrode 180 makes contact with the drain electrode DE1 through the contact hole CNT. - According to the present exemplary embodiment, the
graphene pattern 140 is disposed between the source electrode SE1 and thesemiconductor layer 130 and between the drain electrode DE1 and thesemiconductor layer 130 so that an electrical stability and a reliability of the TFT TR1 may be improved. - In addition, the
second graphene pattern 160 is formed between the source electrode SE1 and thepassivation layer 170 and between the drain electrode DE1 and thepassivation layer 170 so that a productivity and a reliability of the TFT TR1 may be improved. - In addition, when the
semiconductor 130 includes an oxide semiconductor, an etch stopper protecting the oxide semiconductor may be omitted so that a process of manufacturing the TFT TR1 may be simplified and a manufacturing cost of the TFT TR1 may be decreased. - In addition, when the source-
drain electrode layer 150 and thegraphene layer 140 are patterned, thesemiconductor layer 130 may not be damaged. -
FIG. 4 is a cross-sectional view of an array substrate according to another exemplary embodiment of the present invention. - The array substrate of the present exemplary embodiment is substantially the same as the array substrate in
FIGS. 1 to 3D except that the array substrate further includes an etch stopper protecting a semiconductor layer. Thus, any repetitive explanation concerning the same or like parts as those described inFIGS. 1 to 3D above will be omitted. - Referring to
FIG. 4 , a TFT TR2 includes a gate electrode GE2, agate insulating layer 220, asemiconductor layer 230, anetch stopper 240, agraphene pattern 250, a source electrode SE2 and a drain electrode DE2. - The gate electrode GE2 is disposed on a
base substrate 210. For example, the gate electrode GE2 may include a metal, an alloy or a transparent conductive material. - The gate electrode GE2 may have a single layer structure. Alternatively, the gate electrode GE2 may have a multi layer structure which includes a plurality of conductive layers or at least one of conductive layers and at least one of insulating layers.
- The
gate insulating layer 220 is disposed on the gate electrode GE2. Thegate insulating layer 220 insulates the gate electrode GE2 from thesemiconductor layer 230. - For example, the
gate insulating layer 220 may include a silicon oxide (SiOx) and/or a silicon nitride (SiNx). - The
gate insulating layer 220 may include a first layer disposed on the gate electrode GE2 and a second layer disposed on the first layer. The first layer may include the silicon nitride (SiNx). The second layer may include the silicon oxide (SiOx). - The
semiconductor layer 230 is disposed on thegate insulating layer 220. Thesemiconductor layer 230 overlaps with the gate electrode GE2. Thesemiconductor layer 230 functions as a channel layer of the TFT TR2. - In the present exemplary embodiment, the
semiconductor layer 230 includes an oxide semiconductor. For example, thesemiconductor layer 230 may include at least one of a zinc oxide, a tin oxide, a gallium indium zinc (Ga—In—Zn) oxide, an indium zinc (In—Zn) oxide, a indium tin (In—Sn) oxide, indium tin zinc (In—Sn—Zn) oxide and so on. - The
etch stopper 240 is disposed on thesemiconductor layer 230. The etch stopper overlaps with a portion of thesemiconductor layer 230 corresponding to an area between the source electrode SE2 and the drain electrode DE2. - The
etch stopper 240 prevents the oxide semiconductor from making contact with thepassivation layer 270 so that a characteristic of the oxide semiconductor is not changed. Theetch stopper 240 includes a silicon oxide (SiOx). Theetch stopper 240 may have a single layer structure or a multi layer structure. - The
graphene pattern 250 is disposed on thesemiconductor layer 230 and theetch stopper 240. The source electrode SE2 and the drain electrode DE2 are disposed on thegraphene pattern 250. - The source electrode SE2 overlaps with the
semiconductor layer 230. The drain electrode DE2 overlaps with thesemiconductor layer 230. The drain electrode DE2 is spaced apart from the source electrode SE2. - For example, each of the source electrode SE2 and the drain electrode DE2 may include aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti) and so on, or an alloy thereof. Each of the source electrode SE2 and the drain electrode DE2 may include a transparent conductive material such as an indium tin oxide (ITO), an indium zinc oxide (IZO) and an aluminum doped zinc oxide (AZO).
- Each of the source electrode SE2 and the drain electrode DE2 may include a plurality of layers. Each of the source electrode SE2 and the drain electrode DE2 may include a first electrode layer making contact with the
graphene pattern 250 and a second electrode layer making contact with the first electrode layer. For example, the first electrode layer may include one of titanium (Ti), molybdenum (Mo) and an alloy thereof. The second electrode layer may include copper (Cu). - A portion of the
graphene pattern 250 is disposed between the source electrode SE2 and thesemiconductor layer 230 to prevent an interfacial reaction between the source electrode SE2 and thesemiconductor layer 230. Another portion of thegraphene pattern 250 is disposed between the drain electrode DE2 and thesemiconductor layer 230 to prevent an interfacial reaction between the drain electrode DE2 and thesemiconductor layer 230. Accordingly, an electrical stability and a reliability of the TFT TR2 may be improved. - The TFT TR2 may further include a
passivation layer 270 disposed on the source electrode SE2 and the drain electrode DE2. Thepassivation layer 270 may be disposed in an entire area of thebase substrate 210. - For example, the
passivation layer 270 may include a silicon nitride (SiNx). Thepassivation layer 270 may have a single layer structure or a multi layer structure. - A contact hole CNT is formed through the
passivation layer 270. The drain electrode DE2 is exposed through the contact hole CNT. Apixel electrode 280 is electrically connected to the drain electrode DE2 through the contact hole CNT. Thepixel electrode 280 may include a transparent conductive material such as an indium tin oxide (ITO), an indium zinc oxide (IZO) and an aluminum doped zinc oxide (AZO). -
FIGS. 5A to 5E are cross-sectional views illustrating a method of manufacturing the array substrate ofFIG. 4 . - Hereinafter, the method of manufacturing the array substrate may be explained in detail referring to
FIGS. 5A to 5E . - Referring to
FIG. 5A , a gate electrode layer is formed on thebase substrate 210. The gate electrode GE2 is formed by patterning the gate electrode layer. The gate electrode layer may be patterned by a photo lithography method. The gate electrode layer may be patterned using a first mask. - The
gate insulating layer 220 is formed on the gate electrode GE2. - Referring to
FIG. 5B , thesemiconductor layer 230 is formed on thegate insulating layer 220. Theetch stopper 240 is formed on thesemiconductor layer 230. Thesemiconductor layer 230 may be patterned using a second mask. Theetch stopper 240 may be formed using a third mask. - Referring to
FIG. 5C , agraphene layer 250 is formed on thesemiconductor layer 230 and theetch stopper 240. A source-drain electrode layer 260 is formed on thegraphene layer 250. - The
graphene layer 250 may be directly deposited on thesemiconductor layer 230 and theetch stopper 240. For example, a graphene of thegraphene layer 250 may be directly grown on thesemiconductor layer 230 and theetch stopper 240. - The graphene may be grown off of the array substrate and be transferred on the
semiconductor layer 230 and theetch stopper 240 to form thegraphene layer 250. - Referring to
FIG. 5D , the source-drain electrode layer 260 and thegraphene layer 250 are sequentially patterned so that the source electrode SE2, the drain electrode DE2 and thegraphene pattern 250 are formed. - The source-
drain electrode layer 260 and thegraphene layer 250 may be patterned using a fourth mask. - A portion of the source-
drain electrode layer 260 is etched to form the source electrode SE2 and the drain electrode DE2. The source-drain electrode layer 260 may be etched by a dry etching method. The source-drain electrode layer 260 may be etched by a wet etching method. - A portion of the
graphene layer 250 may be ashed by the oxygen plasma ashing method to form thegraphene pattern 250. A portion of thegraphene layer 250 between the source electrode SE2 and the drain electrode DE2 may be removed. - The
graphene layer 250 and the source-drain electrode layer 260 have different etching characteristics. Thus, when the source-drain electrode layer 260 is etched, thegraphene layer 250 is not easily damaged. Accordingly, although the source-drain electrode layer 260 is etched for a long time, thesemiconductor layer 230 may be protected by thegraphene layer 250. In addition, thegraphene layer 250 is removed by the oxygen plasma ashing in a short time so that thesemiconductor layer 230 may not be damaged. - Referring to
FIG. 5E , thepassivation layer 270 is formed on the source electrode SE2, the drain electrode DE2 and theetch stopper 240. The contact hole CNT is formed through thepassivation layer 270. The contact hole CNT may be formed using a fifth mask. The drain electrode DE2 is exposed through the contact hole CNT. - The
pixel electrode 280 is formed on thepassivation layer 270. Thepixel electrode 280 may be formed using a sixth mask. Thepixel electrode 280 makes contact with the drain electrode DE2 through the contact hole CNT. - According to the present exemplary embodiment, the
graphene pattern 250 is disposed between the source electrode SE2 and thesemiconductor layer 230 and between the drain electrode DE2 and thesemiconductor layer 230 so that an electrical stability and a reliability of the TFT TR2 may be improved. - In addition, when the source-
drain electrode layer 260 and thegraphene layer 250 are patterned, thesemiconductor layer 230 may not be damaged. -
FIG. 6 is a cross-sectional view of an array substrate according to still another exemplary embodiment of the present invention.FIG. 7 is a cross-sectional view illustrating a method of manufacturing the array substrate ofFIG. 6 . - The array substrate of the present exemplary embodiment is substantially the same as the array substrate in
FIGS. 1 to 3D , except that the array substrate includes a vertical TFT including a semiconductor layer disposed in a vertical direction. Thus, any repetitive explanation concerning the same or like parts as those described inFIGS. 1 to 3D above elements will be omitted. - Referring to
FIGS. 6-7 , a TFT TR3 includes a source electrode SE3, an insulatinglayer 320, a drain electrode DE3, agraphene pattern 330, asemiconductor layer 340, agate insulating layer 350 and a gate electrode GE3. - The source electrode SE3 is disposed on a
base substrate 310. The source electrode SE3 overlaps with thesemiconductor layer 340. - For example, the source electrode SE3 may include one of aluminum (Al), copper (Cu), molybdenum (Mo) and titanium Ti or an alloy thereof. For example, the source electrode SE3 may include a transparent conductive material such as an indium tin oxide (ITO), an indium zinc oxide (IZO) or an aluminum doped zinc oxide (AZO).
- The source electrode SE3 may have a single layer structure. Alternatively, the source electrode SE3 may have a multi layer structure which includes a plurality of conductive layers or at least one of conductive layers and at least one of insulating layers.
- The insulating
layer 320 is disposed on the source electrode SE3. The insulatinglayer 320 insulates the source electrode SE3 from the drain electrode DE3. - For example, the insulating
layer 320 may include a silicon oxide (SiOx). For example, the insulatinglayer 320 may include a silicon nitride (SiNx). The insulatinglayer 320 may have a single layer structure or a multi layer structure. - The drain electrode DE3 is disposed on the insulating
layer 320. The drain electrode DE3 overlaps with thesemiconductor layer 340. The drain electrode DE3 is spaced apart from the source electrode SE3. - For example, the drain electrode DE3 may include one of aluminum (Al), copper (Cu), molybdenum (Mo) and titanium Ti or an alloy thereof. For example, the drain electrode DE3 may include a transparent conductive material such as an indium tin oxide (ITO), an indium zinc oxide (IZO) or an aluminum doped zinc oxide (AZO).
- The drain electrode DE3 may have a single layer structure. Alternatively, the drain electrode DE3 may have a multi layer structure which includes a plurality of conductive layers or at least one of conductive layers and at least one of insulating layers.
- The drain electrode DE3 may include a plurality of electrode layers. The drain electrode DE3 may include a first electrode layer making contact with the
graphene pattern 330 and a second electrode layer making contact with the first electrode layer. For example, the first electrode layer may include one of titanium (Ti), molybdenum (Mo) and an alloy thereof. The second electrode layer may include copper (Cu). - The
graphene pattern 330 is disposed on the drain electrode DE3. Thegraphene pattern 330 covers an upper surface and a side surface of the drain electrode DE3. A portion of thesemiconductor layer 340 corresponding to the upper surface of the drain electrode DE3 is etched. In contrast, a portion of thesemiconductor layer 340 corresponding to the side surface of the drain electrode DE3 remains. Accordingly, a portion of thegraphene pattern 330 is disposed between the drain electrode DE3 and thesemiconductor layer 340. Another portion of thegraphene pattern 330 is disposed between the drain electrode DE3 and thegate insulating layer 350. - Therefore, the
semiconductor layer 340 extends in a vertical direction according to a side surface of the insulatinglayer 320 to connect the source electrode SE3 to the drain electrode DE3. Thesemiconductor layer 340 functions as a channel layer of the TFT TR3. Thesemiconductor layer 340 may include an amorphous silicon semiconductor. Thesemiconductor layer 340 may include an oxide semiconductor. - Referring to
FIGS. 6 and 7 , thesemiconductor layer 340 entirely overlaps with the drain electrode DE3 in a process of manufacturing thesemiconductor layer 340. - When the
semiconductor layer 340 makes direct contact with the drain electrode DE3, a characteristic of thesemiconductor layer 340 is changed due to an interfacial reaction between thesemiconductor layer 340 and the drain electrode DE3 so that an electrical stability and a reliability of the TFT TR3 may be decreased. - In addition, the
semiconductor layer 340 may be lifted off from the drain electrode DE3 due to the interfacial reaction between thesemiconductor layer 340 and the drain electrode DE3. - The
graphene pattern 330 is disposed between the drain electrode DE3 and thesemiconductor layer 340 in the process of manufacturing thesemiconductor layer 340 so that thegraphene pattern 330 prevents the interfacial reaction between thesemiconductor layer 340 and the drain electrode DE3. Thus, an electrical stability and a reliability of the TFT TR3 may be improved. In addition, a productivity and a reliability of the TFT TR3 may be improved. - Referring again to
FIG. 6 , thegate insulating layer 350 is disposed on thegraphene pattern 330 and thesemiconductor layer 340. Thegate insulating layer 350 insulates the gate electrode GE3 from thesemiconductor layer 340. - For example, the
gate insulating layer 350 may include a silicon oxide (SiOx). For example, thegate insulating layer 350 may include a silicon nitride (SiNx). Thegate insulating layer 350 may have a single layer structure or a multi layer structure. - When the
gate insulating layer 350 makes direct contact with the drain electrode DE3, thegate insulating layer 350 may be lifted off from the drain electrode DE3 due to an interfacial reaction between the drain electrode DE3 and thegate insulating layer 350. - A portion of the
graphene 330 is disposed between the drain electrode DE3 and thegate insulating layer 350 to prevent the interfacial reaction between the drain electrode DE3 and thegate insulating layer 350. Thus, a productivity and a reliability of the TFT TR3 may be improved. - The gate electrode GE3 is disposed on the
gate insulating layer 350. The gate electrode GE3 overlaps with thesemiconductor layer 340. - For example, the gate electrode GE3 may include one of aluminum (Al), copper (Cu), molybdenum (Mo) and titanium Ti or an alloy thereof. For example, the gate electrode GE3 may include a transparent conductive material, such as an indium tin oxide (ITO), an indium zinc oxide (IZO) or an aluminum doped zinc oxide (AZO).
- The gate electrode GE3 may have a single layer structure. Alternatively, the gate electrode GE3 may have a multi layer structure which includes a plurality of conductive layers or at least one of conductive layers and at least one of insulating layers.
- When the insulating
layer 320 makes direct contact with the source electrode SE3, the insulatinglayer 320 may be lifted off from the source electrode SE3 due to an interfacial reaction between the source electrode SE3 and the insulatinglayer 320. - When the drain electrode DE3 makes direct contact with the insulating
layer 320, the drain electrode DE3 may be lifted off from the insulatinglayer 320 due to an interfacial reaction between the insulatinglayer 320 and the drain electrode DE3. - The second graphene pattern prevents the interfacial reaction between the source electrode SE3 and the insulating
layer 320. The third graphene pattern prevents the interfacial reaction between the insulatinglayer 320 and the drain electrode DE3. Thus, a productivity and a reliability of the TFT TR3 may be improved. - Although not shown in the figures, when the
semiconductor layer 340 includes an amorphous silicon semiconductor, an ohmic contact layer may be formed between the source electrode SE3 and the insulatinglayer 320 and between the insulatinglayer 320 and the drain electrode DE3. The ohmic contact layer may include an amorphous silicon doped with a dopant. - According to the present exemplary embodiment, the
graphene pattern 330 is disposed between the drain electrode DE3 and thesemiconductor layer 340 so that an electrical stability, a productivity and a reliability of the TFT TR3 may be improved. - In addition, the
graphene pattern 330 is disposed between the drain electrode DE3 and thegate insulating layer 350 so that a productivity and a reliability of the TFT TR3 may be improved. -
FIG. 8 is a cross-sectional view of an array substrate according to still another exemplary embodiment of the present invention. - The array substrate of the present exemplary embodiment is substantially the same as the array substrate in
FIGS. 6 and 7 , except that the array substrate further includes a second graphene pattern and a third graphene pattern. Thus, any repetitive explanation concerning the same or like parts as those described inFIGS. 6 and 7 above elements will be omitted. - Referring to
FIG. 8 , a TFT TR4 includes a source electrode SE3, an insulatinglayer 320, a drain electrode DE3, agraphene pattern 330, asemiconductor layer 340, agate insulating layer 350, a gate electrode GE3, asecond graphene pattern 360 and athird graphene pattern 370. - The
second graphene pattern 360 is disposed between the source electrode SE3 and the insulatinglayer 320. Thethird graphene pattern 370 is disposed between the drain electrode DE3 and the insulatinglayer 320. - According to the present exemplary embodiment, the
graphene pattern 330 is disposed between the drain electrode DE3 and thesemiconductor layer 340 so that an electrical stability, a productivity and a reliability of the TFT TR4 may be improved. - In addition, the
graphene pattern 330 is disposed between the drain electrode DE3 and thegate insulating layer 350 so that a productivity and a reliability of the TFT TR4 may be improved. - In addition, the second and
third graphene patterns layer 320 and between the drain electrode DE3 and the insulatinglayer 320 so that a productivity and a reliability of the TFT TR4 may be improved. - According to the TFT and the method of manufacturing the TFT, the graphene pattern prevents at least one of the source electrode and the drain electrode from reacting with the semiconductor layer so that an electrical stability and a reliability of the TFT may be improved. In addition, the graphene pattern also prevents at least one of the source electrode and the drain electrode from reacting with the passivation layer so that a process of manufacturing the TFT may be simplified and a manufacturing cost of the TFT may be decreased.
- It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Claims (31)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US14/939,564 US9882056B2 (en) | 2011-06-28 | 2015-11-12 | Thin film transistor and method of manufacturing the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR10-2011-0062865 | 2011-06-28 | ||
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US20130175506A1 (en) * | 2012-01-10 | 2013-07-11 | Samsung Electronics Co., Ltd. | Three-dimensional graphene switching device |
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Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6255706B1 (en) * | 1999-01-13 | 2001-07-03 | Fujitsu Limited | Thin film transistor and method of manufacturing same |
US20020001887A1 (en) * | 1999-01-05 | 2002-01-03 | Sung Chae Gee | Thin film transistor and manufacturing method therefor |
US20070045734A1 (en) * | 2005-08-29 | 2007-03-01 | Chuan-Yi Wu | Thin film transistor and fabrication method thereof |
US20100323113A1 (en) * | 2009-06-18 | 2010-12-23 | Ramappa Deepak A | Method to Synthesize Graphene |
US20110012118A1 (en) * | 2009-07-18 | 2011-01-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US20120141799A1 (en) * | 2010-12-03 | 2012-06-07 | Francis Kub | Film on Graphene on a Substrate and Method and Devices Therefor |
US20120139114A1 (en) * | 2010-12-06 | 2012-06-07 | Stmicroelectronics, Inc. | Copper interconnect structure having a graphene cap |
US20120168724A1 (en) * | 2009-07-21 | 2012-07-05 | Cornell University | Transfer-free batch fabrication of single layer graphene devices |
US20120188478A1 (en) * | 2011-01-21 | 2012-07-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4547789A (en) * | 1983-11-08 | 1985-10-15 | Energy Conversion Devices, Inc. | High current thin film transistor |
US4620208A (en) * | 1983-11-08 | 1986-10-28 | Energy Conversion Devices, Inc. | High performance, small area thin film transistor |
WO2000036641A1 (en) * | 1998-12-14 | 2000-06-22 | Frontec Incorporated | Wiring, thin-film transistor substrate with the wiring, method of manufacture thereof, and liquid crystal display device |
JP5135825B2 (en) * | 2007-02-21 | 2013-02-06 | 富士通株式会社 | Graphene transistor and manufacturing method thereof |
JP2011091364A (en) | 2009-07-27 | 2011-05-06 | Kobe Steel Ltd | Wiring structure and method of manufacturing the same, as well as display apparatus with wiring structure |
CN102473732B (en) | 2009-07-27 | 2015-09-16 | 株式会社神户制钢所 | Wire structures and possess the display unit of wire structures |
-
2011
- 2011-06-28 KR KR1020110062865A patent/KR20130006999A/en not_active Application Discontinuation
-
2012
- 2012-03-12 US US13/418,172 patent/US20130001573A1/en not_active Abandoned
- 2012-06-28 CN CN2012102225443A patent/CN102856364A/en active Pending
-
2015
- 2015-11-12 US US14/939,564 patent/US9882056B2/en active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020001887A1 (en) * | 1999-01-05 | 2002-01-03 | Sung Chae Gee | Thin film transistor and manufacturing method therefor |
US6255706B1 (en) * | 1999-01-13 | 2001-07-03 | Fujitsu Limited | Thin film transistor and method of manufacturing same |
US20070045734A1 (en) * | 2005-08-29 | 2007-03-01 | Chuan-Yi Wu | Thin film transistor and fabrication method thereof |
US20100323113A1 (en) * | 2009-06-18 | 2010-12-23 | Ramappa Deepak A | Method to Synthesize Graphene |
US20110012118A1 (en) * | 2009-07-18 | 2011-01-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US20120168724A1 (en) * | 2009-07-21 | 2012-07-05 | Cornell University | Transfer-free batch fabrication of single layer graphene devices |
US20120141799A1 (en) * | 2010-12-03 | 2012-06-07 | Francis Kub | Film on Graphene on a Substrate and Method and Devices Therefor |
US20120139114A1 (en) * | 2010-12-06 | 2012-06-07 | Stmicroelectronics, Inc. | Copper interconnect structure having a graphene cap |
US20120188478A1 (en) * | 2011-01-21 | 2012-07-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
Cited By (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9281404B2 (en) * | 2012-01-10 | 2016-03-08 | Samsung Electronics Co., Ltd. | Three-dimensional graphene switching device |
US20130175506A1 (en) * | 2012-01-10 | 2013-07-11 | Samsung Electronics Co., Ltd. | Three-dimensional graphene switching device |
US20140070220A1 (en) * | 2012-02-27 | 2014-03-13 | Boe Technology Group Co., Ltd. | Array substrate, method for manufacturing the same and display device |
US20140091305A1 (en) * | 2012-09-29 | 2014-04-03 | Boe Technology Group Co., Ltd. | Polysilicon Thin Film And Manufacturing Method Thereof, Array Substrate And Display Device |
US9142409B2 (en) * | 2012-09-29 | 2015-09-22 | Boe Technology Group Co., Ltd. | Polysilicon thin film and manufacturing method thereof, array substrate and display device |
US20140145178A1 (en) * | 2012-11-27 | 2014-05-29 | Samsung Display Co., Ltd. | Switching element, display substrate and method of manufacturing the same |
US8884286B2 (en) * | 2012-11-27 | 2014-11-11 | Samsung Display Co., Ltd. | Switching element, display substrate and method of manufacturing the same |
US20140183520A1 (en) * | 2012-12-31 | 2014-07-03 | Hannstar Display Corporation | Oxide thin film transistor structure and method thereof |
US9679922B2 (en) * | 2015-01-06 | 2017-06-13 | Japan Display Inc. | Display device having vertical oxide semiconductor channel layer on sidewall of insulating spacer |
US20160197099A1 (en) * | 2015-01-06 | 2016-07-07 | Japan Display Inc. | Display device |
US9960188B2 (en) * | 2015-03-18 | 2018-05-01 | Boe Technology Group Co., Ltd. | Thin film transistor, array substrate, and fabrication method there of, and display apparatus |
US20170117302A1 (en) * | 2015-03-18 | 2017-04-27 | Boe Technology Group Co., Ltd. | Thin film transistor, array substrate, and fabrication method there of, and display apparatus |
US9853059B2 (en) * | 2015-07-02 | 2017-12-26 | Japan Display Inc. | Semiconductor device |
US20170005200A1 (en) * | 2015-07-02 | 2017-01-05 | Japan Display Inc. | Semiconductor device |
US10937864B2 (en) | 2015-07-30 | 2021-03-02 | International Business Machines Corporation | Leakage-free implantation-free ETSOI transistors |
US9768254B2 (en) | 2015-07-30 | 2017-09-19 | International Business Machines Corporation | Leakage-free implantation-free ETSOI transistors |
US11502171B2 (en) | 2015-07-30 | 2022-11-15 | International Business Machines Corporation | Leakage-free implantation-free ETSOI transistors |
US10651273B2 (en) | 2015-07-30 | 2020-05-12 | International Business Machines Corporation | Leakage-free implantation-free ETSOI transistors |
US10622388B2 (en) | 2016-04-13 | 2020-04-14 | Boe Technology Group Co., Ltd. | Array substrate sensor and detection device |
US10504926B2 (en) * | 2016-10-31 | 2019-12-10 | Boe Technology Group Co., Ltd. | Thin film transistor, method for fabricating the same, array substrate, and display panel |
US20190267406A1 (en) * | 2017-05-27 | 2019-08-29 | Fuzhou Boe Optoelectronics Technology Co., Ltd. | Thin film transistor, fabrication method therefor, and array substrate |
US11177287B2 (en) * | 2017-05-27 | 2021-11-16 | Fuzhou Boe Optoelectronics Technology Co., Ltd. | Thin film transistor, fabrication method therefor, and array substrate |
US10600816B2 (en) * | 2017-11-17 | 2020-03-24 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Array substrate comprising graphene conductive layer and manufacturing method of the same |
US20190157302A1 (en) * | 2017-11-17 | 2019-05-23 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Array substrate, display panel and manufacturing method of an array substrate |
US10777665B2 (en) | 2018-04-20 | 2020-09-15 | International Business Machines Corporation | III-V and Zn based finFET structure formed using low temperature deposition techniques |
US10431672B1 (en) | 2018-04-20 | 2019-10-01 | International Business Machines Corporation | Method of forming a III-V and Zn based finFET structure using low temperature deposition techniques |
CN111584517A (en) * | 2020-05-15 | 2020-08-25 | Tcl华星光电技术有限公司 | Array substrate and preparation method thereof |
CN113363329A (en) * | 2021-06-04 | 2021-09-07 | 华南理工大学 | Thin film transistor and preparation method thereof |
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EP4152412A1 (en) * | 2021-09-17 | 2023-03-22 | Intel Corporation | Graphitic carbon contacts for devices with oxide channels |
Also Published As
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CN102856364A (en) | 2013-01-02 |
US9882056B2 (en) | 2018-01-30 |
KR20130006999A (en) | 2013-01-18 |
US20160064571A1 (en) | 2016-03-03 |
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