CN111710725A - Double-gate electrode metal oxide thin film transistor and preparation method thereof - Google Patents
Double-gate electrode metal oxide thin film transistor and preparation method thereof Download PDFInfo
- Publication number
- CN111710725A CN111710725A CN202010524581.4A CN202010524581A CN111710725A CN 111710725 A CN111710725 A CN 111710725A CN 202010524581 A CN202010524581 A CN 202010524581A CN 111710725 A CN111710725 A CN 111710725A
- Authority
- CN
- China
- Prior art keywords
- gate electrode
- layer
- electrode
- metal oxide
- oxide semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 85
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 85
- 239000010409 thin film Substances 0.000 title claims abstract description 45
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 34
- 238000002161 passivation Methods 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 163
- 238000004519 manufacturing process Methods 0.000 claims description 25
- 238000000151 deposition Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 16
- 239000002356 single layer Substances 0.000 claims description 16
- 229910004205 SiNX Inorganic materials 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 229910052750 molybdenum Inorganic materials 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 239000007769 metal material Substances 0.000 claims description 4
- 238000004891 communication Methods 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 description 13
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009776 industrial production Methods 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 239000005300 metallic glass Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- -1 IGZO Chemical class 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
Abstract
The invention discloses a double-gate electrode metal oxide thin film transistor and a preparation method thereof, wherein the double-gate electrode metal oxide thin film transistor comprises the following steps: a substrate base plate; the bottom gate electrode, the bottom gate insulating layer, the metal oxide semiconductor layer, the passivation layer, the source electrode, the drain electrode, the first top gate electrode and the second top gate electrode are sequentially arranged on the substrate; a planarization layer and a pixel electrode layer; the source electrode, the drain electrode, the first top gate electrode and the second top gate electrode are located on the same layer, and the second top gate electrode is connected with the bottom gate electrode through a bottom gate electrode contact hole. The top gate electrode and the source-drain electrode are made of the same layer of metal, and the top gate and the bottom gate are in signal communication to form a double-gate structure device, so that the process is simple, and the cost is saved.
Description
Technical Field
The application relates to the technical field of displays, in particular to a double-gate electrode metal oxide thin film transistor and a preparation method thereof.
Background
The thin film transistor is widely applied to the display field as a core device of an active matrix driving flat panel display technology. Currently, in the flat panel display technology, a silicon-based Thin Film Transistor (TFT) is a well-established industrial technology, and mainly includes an amorphous silicon TFT and a polysilicon TFT. As the flat panel display technology is developed toward a large area, high resolution, flexible rollable type, and many new flat panel display technologies are developed, higher requirements are put on the performance of the TFT. In recent years, TFTs having an amorphous metal oxide semiconductor as an active layer have been the focus of research for their excellent performance. The metal oxide TFT has the advantages of wide forbidden band, high uniformity, high stability, high field effect mobility and the like, and the production technology of the metal oxide TFT is compatible with the existing silicon-based flat panel display technology and becomes a development trend for replacing the silicon-based TFT to be applied to the next generation display technology. In the last decade, amorphous metal oxide semiconductors have become the active layer of thin film transistors, such as zinc oxide, indium tin zinc oxide, indium oxide, gallium zinc oxide, and the like.
The mos thin film transistor is considered as a key technology in the next generation flat panel display due to its good device performance and low process cost. However, as the performance of displays, including high resolution, narrow frame technology, etc., is improved, higher requirements are placed on the performance, including mobility and stability, of thin film transistors in the array substrate. The traditional thin film transistor is generally in a single-gate structure and has the problems of poor stability and the like. In order to solve the stability problem of the single-gate thin film transistor, a new double-gate thin film transistor technology is developed, a top gate and a bottom gate are respectively arranged on two sides of an active layer, and the active layer is driven by the double gates, so that the threshold voltage can be easily controlled; meanwhile, the carrier mobility can be greatly improved.
In the prior art, in order to manufacture the dual-gate thin film transistor structure, a metal process is usually added, a new layer of metal forms a top gate, and a three-layer metal layer is formed in the dual-gate thin film transistor structure. The manufacturing cost is increased by adding one more gate metal layer process.
Disclosure of Invention
In order to overcome the defects of the prior art, embodiments of the present application provide a dual-gate metal oxide thin film transistor and a method for fabricating the same. The top gate electrode and the source and drain electrodes are made of the same layer of metal, and the top gate and the bottom gate are in signal communication to form a double-gate structure device.
The embodiment of the invention provides a double-gate electrode metal oxide thin film transistor, which comprises:
a substrate base plate;
a bottom gate electrode disposed on the substrate base plate;
a bottom gate insulating layer covering the bottom gate electrode;
a metal oxide semiconductor layer disposed on the bottom gate insulating layer;
a passivation layer covering the metal oxide semiconductor layer;
a source electrode, a drain electrode, a first top gate electrode and a second top gate electrode disposed on the passivation layer;
a planarization layer covering the source electrode, the drain electrode, the first top gate electrode, and the second top gate electrode; and
a pixel electrode layer disposed on the planarization layer;
the source electrode, the drain electrode, the first top gate electrode and the second top gate electrode are located on the same layer, and the second top gate electrode is connected with the bottom gate electrode through a bottom gate electrode contact hole.
According to the double-gate electrode metal oxide thin film transistor provided by the embodiment of the invention, the source electrode and the drain electrode are respectively connected with the metal oxide semiconductor layer through the metal oxide semiconductor layer contact holes arranged on the passivation layer, and the pixel electrode layer is connected with the source electrode through the contact holes.
According to the double-gate electrode metal oxide thin film transistor provided by the embodiment of the invention, the material of the metal oxide semiconductor layer comprises IGZO or IZTO or IGZTO.
The embodiment of the invention also provides a preparation method of the double-gate electrode metal oxide thin film transistor, which comprises the following steps:
step S1, providing a substrate, depositing a layer of metal on the substrate as a bottom gate electrode, and etching a pattern;
step S2, depositing to form a bottom gate insulating layer;
step S3, depositing a layer of metal oxide semiconductor material to form a metal oxide semiconductor layer, and etching a pattern;
step S4, depositing to form a passivation layer, and etching a metal oxide semiconductor layer contact hole and a bottom gate electrode contact hole by using a yellow light process;
step S5, depositing a metal layer, and etching a pattern to form a source electrode, a drain electrode, a first top gate electrode and a second top gate electrode, wherein the source electrode and the drain electrode are connected with the metal oxide semiconductor layer through a metal oxide semiconductor layer contact hole, and the second top gate electrode is connected with the bottom gate electrode through a bottom gate electrode contact hole;
step S6, depositing a flat layer;
and step S7, preparing a pixel electrode layer on the flat layer, and finishing the manufacture of the thin film transistor backboard.
According to the method for manufacturing the double-gate electrode metal oxide thin film transistor provided by the embodiment of the invention, in the step S1, the metal material of the bottom gate electrode comprises Mo, Al, Cu, Ti or an alloy material, the bottom gate electrode has a single-layer structure or a multi-layer structure, and the thickness of the bottom gate electrode is 1000 to 10000 angstrom.
According to the preparation method of the double-gate electrode metal oxide thin film transistor provided by the embodiment of the invention, in the step S2, the material of the bottom gate insulating layer is SiOx or SiNx, the bottom gate insulating layer is of a single-layer structure or a multi-layer structure, and the thickness of the bottom gate insulating layer is 500 to 4000 angstroms.
According to the method for manufacturing the double-gate electrode metal oxide thin film transistor provided by the embodiment of the invention, in the step S3, the metal oxide semiconductor material comprises IGZO or IZTO or IGZTO, and the thickness of the metal oxide semiconductor layer is 100 to 1000 angstroms.
According to the method for manufacturing the dual-gate electrode metal oxide thin film transistor provided by the embodiment of the invention, in the step S4, the material of the passivation layer comprises SiOx or SiNx, the passivation layer is of a single-layer structure or a multi-layer structure, and the thickness of the passivation layer is 1000 to 5000 angstrom meters.
According to the method for manufacturing the dual-gate metal oxide thin film transistor provided by the embodiment of the invention, in the step S5, the source electrode, the drain electrode, the first top gate electrode and the second top gate electrode are made of Mo, Al, Cu, Ti or an alloy material, the source electrode, the drain electrode, the first top gate electrode and the second top gate electrode are in a single-layer structure or a multi-layer structure, and the thickness of the source electrode, the drain electrode, the first top gate electrode and the second top gate electrode is 1000 to 10000 angstrom.
According to the preparation method of the double-gate electrode metal oxide thin film transistor provided by the embodiment of the invention, the first top gate electrode, the second top gate electrode, the source electrode and the drain electrode are made of the same layer of metal, and the second top gate electrode is connected with the bottom gate electrode to form a double-gate structure.
The invention has the beneficial effects that: the embodiment of the invention provides a double-gate electrode metal oxide thin film transistor and a preparation method thereof. Therefore, the double-gate electrode metal oxide thin film transistor provided by the invention can be used for manufacturing a double-gate structure thin film transistor device with better driving performance by only using two metal layers under the condition of not increasing metal manufacturing procedures, and the working characteristics and the structural, electrical, optical and thermal stability of the double-gate thin film transistor are improved. Compared with the prior art, the double-gate electrode metal oxide thin film transistor has the advantages that the manufacturing process is simple, one Mask and manufacturing process are reduced, the production efficiency is improved, and the production cost is also saved. The method for preparing the double-gate electrode metal oxide thin film transistor directly prepares the top gate electrode through the same yellow light etching process while specifically preparing the source electrode and the drain electrode, reduces the photoetching times and can effectively reduce the preparation cost compared with the traditional preparation process. The double-gate electrode metal oxide thin film transistor realized by the method has the characteristics of simple process, good uniformity, large area, good repeatability and high stability, is compatible with the existing flat panel display process technology, is suitable for industrial production, and improves the production efficiency.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a dual-gate metal oxide thin film transistor according to an embodiment.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Fig. 1 is a schematic structural diagram of a dual-gate mos tft according to an embodiment of the present invention. As shown in fig. 1, the double gate metal oxide thin film transistor includes: the substrate comprises a substrate base plate 1, wherein the substrate base plate 1 is a glass base plate; the bottom gate electrode 2 is arranged on the substrate base plate 1; the bottom gate insulating layer 3, the bottom gate insulating layer 3 covers the bottom gate electrode 2 completely; a metal oxide semiconductor layer 4, the metal oxide semiconductor layer 4 being disposed on the bottom gate insulating layer 3; a passivation layer 5, wherein the passivation layer 5 completely covers the metal oxide semiconductor layer 4; a source electrode 6, a drain electrode 7, a first top gate electrode 8 and a second top gate electrode 9 disposed on the passivation layer 5; a planarization layer 10, wherein the planarization layer 10 completely covers the source electrode 6, the drain electrode 7, the first top gate electrode 8 and the second top gate electrode 9; and a pixel electrode layer 11, the pixel electrode layer 11 being disposed on the planarization layer 10; the source electrode 6, the drain electrode 7, the first top gate electrode 8 and the second top gate electrode 9 are located in the same layer, and the second top gate electrode 9 is connected with the bottom gate electrode 2 through a bottom gate electrode contact hole 21.
Wherein the source electrode 6 and the drain electrode 7 are respectively connected to the metal oxide semiconductor layer 4 through metal oxide semiconductor layer contact holes 41 provided on the passivation layer 5, and the pixel electrode layer 11 is connected to the source electrode 6 through a source electrode contact hole 61. The metal oxide semiconductor layer 4 is any one of IGZO, IZTO, and IGZTO.
Specifically, the thickness of the bottom gate electrode 2 is 1000 to 10000 angstrom, the metal material of the bottom gate electrode 2 includes but is not limited to Mo or Al or Cu or Ti or other alloy materials, and the bottom gate electrode 2 is a single-layer structure or a multi-layer structure. The bottom gate insulating layer 3 is a single-layer structure film layer or a multi-layer structure film layer, the material of the bottom gate insulating layer 3 is any one of SiOx, SiNx or other inorganic materials, and the thickness of the bottom gate insulating layer 3 is 500-4000 angstroms.
Specifically, the metal oxide semiconductor material of the metal oxide semiconductor layer 4 is any one of other metal oxides such as IGZO, IZTO, and IGZTO, and the thickness of the metal oxide semiconductor layer 4 is 100 to 1000 angstrom. The passivation layer 5 is a single-layer structure film layer or a multi-layer structure film layer, the material of the passivation layer 5 is any one of SiOx, SiNx or other inorganic materials, and the thickness of the passivation layer 5 is 1000-5000 angstrom meters. And etching a metal oxide semiconductor layer contact hole 41 and a bottom gate electrode contact hole 21 on the passivation layer 5 by a yellow light process. Wherein the metal oxide semiconductor layer contact hole 41 penetrates through the passivation layer 5 to expose the metal oxide semiconductor layer 4; the bottom gate electrode contact hole 21 penetrates through the passivation layer 5 and the bottom gate insulating layer 3, and exposes the bottom gate electrode 2.
Specifically, the source electrode 6, the drain electrode 7, the first top gate electrode 8, and the second top gate electrode 9 are formed by etching a same metal layer, the material of the metal layer includes but is not limited to Mo or Al or Cu or Ti or other alloy materials, the source electrode 6, the drain electrode 7, the first top gate electrode 8, and the second top gate electrode 9 are of a single-layer structure or a multi-layer structure, and the thickness of the source electrode 6, the drain electrode 7, the first top gate electrode 8, and the second top gate electrode 9 is 1000 to 10000 angstrom. The source electrode 6 and the drain electrode 7 are connected to the metal oxide semiconductor layer 4 through a metal oxide semiconductor layer contact hole 41, and the second top gate electrode 9 is connected to the bottom gate electrode 2 through a bottom gate electrode contact hole 21. The second top gate electrode 9 is connected with the bottom gate electrode 2 to form a double-gate structure.
And etching a source contact hole 61 on the flat layer 10 by a yellow light etching process, wherein the source contact hole 61 penetrates through the flat layer 10 to expose the source electrode 6. The pixel electrode layer 11 is connected to the source electrode 6 through the source contact hole 61.
The embodiment of the invention also provides a preparation method of the double-gate electrode metal oxide thin film transistor, which comprises the following steps:
step S1, cleaning a substrate, depositing a layer of metal on the substrate as a bottom gate electrode, and etching a pattern;
step S2, depositing to form a bottom gate insulating layer;
step S3, depositing a layer of metal oxide semiconductor material to form a metal oxide semiconductor layer, and etching a pattern;
step S4, depositing to form a passivation layer, and etching a metal oxide semiconductor layer contact hole and a bottom gate electrode contact hole by using a yellow light process;
step S5, depositing a metal layer, and etching a pattern to form a source electrode, a drain electrode, a first top gate electrode and a second top gate electrode, wherein the source electrode and the drain electrode are connected with the metal oxide semiconductor layer through a metal oxide semiconductor layer contact hole, and the second top gate electrode is connected with the bottom gate electrode through a bottom gate electrode contact hole;
step S6, depositing a flat layer;
and step S7, preparing a pixel electrode layer on the flat layer, and finishing the manufacture of the thin film transistor backboard.
Specifically, in step S1, the metal material of the bottom gate electrode is Mo, Al, Cu, Ti, or an alloy material, the bottom gate electrode has a single-layer structure or a multi-layer structure, and the thickness of the bottom gate electrode is 1000 to 10000 angstrom.
Specifically, in step S2, the bottom gate insulating layer is made of SiOx or SiNx, the bottom gate insulating layer has a single-layer structure or a multi-layer structure, and the bottom gate insulating layer has a thickness of 500 to 4000 angstroms.
Specifically, in step S3, the metal oxide semiconductor material is IGZO or IZTO or IGZTO, and the thickness of the metal oxide semiconductor layer is 100 to 1000 angstroms.
Specifically, in step S4, the passivation layer is made of SiOx or SiNx, the passivation layer has a single-layer structure or a multi-layer structure, and the thickness of the passivation layer is 1000 to 5000 angstroms.
Specifically, in step S5, the source electrode, the drain electrode, the first top gate electrode, and the second top gate electrode are made of Mo, Al, Cu, Ti, or an alloy material, the source electrode, the drain electrode, the first top gate electrode, and the second top gate electrode are of a single-layer structure or a multi-layer structure, and the thickness of the source electrode, the drain electrode, the first top gate electrode, and the second top gate electrode is 1000 to 10000 angstrom.
The first top gate electrode, the second top gate electrode, the source electrode and the drain electrode are made of the same layer of metal, and the second top gate electrode is connected with the bottom gate electrode to form a double-gate structure.
Specifically, in the steps S6 and S7, a source contact hole is etched on the planarization layer through a photolithography process, and the source contact hole penetrates through the planarization layer to expose the source electrode. The pixel electrode layer is connected with the source electrode through the source electrode contact hole.
The embodiment of the invention provides a double-gate electrode metal oxide thin film transistor and a preparation method thereof. Therefore, the double-gate electrode metal oxide thin film transistor provided by the invention can be used for manufacturing a double-gate structure thin film transistor device with better driving performance by only using two metal layers under the condition of not increasing metal manufacturing procedures, and the working characteristics and the structural, electrical, optical and thermal stability of the double-gate thin film transistor are improved. Compared with the prior art, the double-gate electrode metal oxide thin film transistor has the advantages that the manufacturing process is simple, one Mask and manufacturing process are reduced, the production efficiency is improved, and the production cost is also saved. The method for preparing the double-gate electrode metal oxide thin film transistor directly prepares the top gate electrode through the same yellow light etching process while specifically preparing the source electrode and the drain electrode, reduces the photoetching times and can effectively reduce the preparation cost compared with the traditional preparation process. The double-gate electrode metal oxide thin film transistor realized by the method has the characteristics of simple process, good uniformity, large area, good repeatability and high stability, is compatible with the existing flat panel display process technology, is suitable for industrial production, and improves the production efficiency.
The dual-gate metal oxide thin film transistor and the method for manufacturing the same provided by the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are explained in the present application by applying specific examples, and the description of the above embodiments is only used to help understanding the technical solutions and the core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A double gate metal oxide thin film transistor, comprising:
a substrate base plate;
a bottom gate electrode disposed on the substrate base plate;
a bottom gate insulating layer covering the bottom gate electrode;
a metal oxide semiconductor layer disposed on the bottom gate insulating layer;
a passivation layer covering the metal oxide semiconductor layer;
a source electrode, a drain electrode, a first top gate electrode and a second top gate electrode disposed on the passivation layer;
a planarization layer covering the source electrode, the drain electrode, the first top gate electrode, and the second top gate electrode; and
a pixel electrode layer disposed on the planarization layer;
the source electrode, the drain electrode, the first top gate electrode and the second top gate electrode are located on the same layer, and the second top gate electrode is connected with the bottom gate electrode through a bottom gate electrode contact hole.
2. The double-gate metal oxide thin film transistor of claim 1, wherein the source and drain electrodes are respectively connected to the metal oxide semiconductor layer through metal oxide semiconductor layer contact holes disposed on the passivation layer, and the pixel electrode layer is connected to the source electrode through a source electrode contact hole.
3. The double-gate electrode metal oxide thin film transistor of claim 1, wherein the material of the metal oxide semiconductor layer comprises IGZO or IZTO or IGZTO.
4. A preparation method of a double-gate electrode metal oxide thin film transistor is characterized by comprising the following steps:
step S1, providing a substrate, depositing a layer of metal on the substrate as a bottom gate electrode, and etching a pattern;
step S2, depositing to form a bottom gate insulating layer;
step S3, depositing a layer of metal oxide semiconductor material to form a metal oxide semiconductor layer, and etching a pattern;
step S4, depositing to form a passivation layer, and etching a metal oxide semiconductor layer contact hole and a bottom gate electrode contact hole by using a yellow light process;
step S5, depositing a metal layer, and etching a pattern to form a source electrode, a drain electrode, a first top gate electrode and a second top gate electrode, wherein the source electrode and the drain electrode are connected with the metal oxide semiconductor layer through a metal oxide semiconductor layer contact hole, and the second top gate electrode is connected with the bottom gate electrode through a bottom gate electrode contact hole;
step S6, depositing a flat layer;
and step S7, preparing a pixel electrode layer on the flat layer, and finishing the manufacture of the thin film transistor.
5. The method of claim 4, wherein in step S1, the metal material of the bottom gate electrode comprises Mo or Al or Cu or Ti or alloy material, the bottom gate electrode has a single-layer structure or a multi-layer structure, and the thickness of the bottom gate electrode is 1000 to 10000A m.
6. The method of claim 4, wherein in step S2, the bottom gate insulating layer is made of SiOx or SiNx, has a single-layer structure or a multi-layer structure, and has a thickness of 500-4000 angstroms.
7. The method of claim 4, wherein in step S3, the metal oxide semiconductor material comprises IGZO or IZTO or IGZTO, and the thickness of the metal oxide semiconductor layer is 100-1000A.
8. The method of claim 4, wherein in step S4, the passivation layer is made of SiOx or SiNx, and has a single-layer structure or a multi-layer structure, and the thickness of the passivation layer is 1000 to 5000 angstroms.
9. The method of claim 4, wherein in step S5, the source electrode, the drain electrode, the first top-gate electrode, and the second top-gate electrode are made of Mo, Al, Cu, Ti, or an alloy material, and have a single-layer structure or a multi-layer structure, and the thickness of the source electrode, the drain electrode, the first top-gate electrode, and the second top-gate electrode is 1000 to 10000A m.
10. The method of claim 4, wherein the first top-gate electrode and the second top-gate electrode are made of the same metal layer as the source electrode and the drain electrode, and the second top-gate electrode is connected to the bottom-gate electrode to form a dual-gate structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010524581.4A CN111710725A (en) | 2020-06-10 | 2020-06-10 | Double-gate electrode metal oxide thin film transistor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010524581.4A CN111710725A (en) | 2020-06-10 | 2020-06-10 | Double-gate electrode metal oxide thin film transistor and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111710725A true CN111710725A (en) | 2020-09-25 |
Family
ID=72539847
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010524581.4A Pending CN111710725A (en) | 2020-06-10 | 2020-06-10 | Double-gate electrode metal oxide thin film transistor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111710725A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112542516A (en) * | 2020-11-03 | 2021-03-23 | 北海惠科光电技术有限公司 | Active switch, manufacturing method thereof and display panel |
| CN113594183A (en) * | 2021-07-27 | 2021-11-02 | 上海大学 | Three-dimensional double-active-layer oxide thin film transistor and application thereof |
| CN116666440A (en) * | 2023-07-26 | 2023-08-29 | 浙江朗德电子科技有限公司 | Bottom gate MOS tube and manufacturing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465788A (en) * | 2015-01-04 | 2015-03-25 | 京东方科技集团股份有限公司 | Thin film transistor, preparing method of thin film transistor, array substrate, preparing method of array substrate and display device |
| CN106098786A (en) * | 2016-06-13 | 2016-11-09 | 武汉华星光电技术有限公司 | Double grid electrode oxide thin film transistor and preparation method thereof |
| CN106684155A (en) * | 2017-01-05 | 2017-05-17 | 京东方科技集团股份有限公司 | Dual-gate thin film transistor and preparation method therefor, array substrate and display apparatus |
| CN107104151A (en) * | 2017-05-10 | 2017-08-29 | 陕西师范大学 | A kind of double grid electrode metal oxide thin-film transistor and preparation method thereof |
-
2020
- 2020-06-10 CN CN202010524581.4A patent/CN111710725A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465788A (en) * | 2015-01-04 | 2015-03-25 | 京东方科技集团股份有限公司 | Thin film transistor, preparing method of thin film transistor, array substrate, preparing method of array substrate and display device |
| CN106098786A (en) * | 2016-06-13 | 2016-11-09 | 武汉华星光电技术有限公司 | Double grid electrode oxide thin film transistor and preparation method thereof |
| CN106684155A (en) * | 2017-01-05 | 2017-05-17 | 京东方科技集团股份有限公司 | Dual-gate thin film transistor and preparation method therefor, array substrate and display apparatus |
| CN107104151A (en) * | 2017-05-10 | 2017-08-29 | 陕西师范大学 | A kind of double grid electrode metal oxide thin-film transistor and preparation method thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112542516A (en) * | 2020-11-03 | 2021-03-23 | 北海惠科光电技术有限公司 | Active switch, manufacturing method thereof and display panel |
| CN112542516B (en) * | 2020-11-03 | 2024-01-30 | 北海惠科光电技术有限公司 | Active switch, manufacturing method thereof and display panel |
| CN113594183A (en) * | 2021-07-27 | 2021-11-02 | 上海大学 | Three-dimensional double-active-layer oxide thin film transistor and application thereof |
| CN113594183B (en) * | 2021-07-27 | 2023-09-22 | 上海大学 | Three-dimensional double-active-layer oxide thin film transistor and application thereof |
| CN116666440A (en) * | 2023-07-26 | 2023-08-29 | 浙江朗德电子科技有限公司 | Bottom gate MOS tube and manufacturing method |
| CN116666440B (en) * | 2023-07-26 | 2023-12-26 | 浙江朗德电子科技有限公司 | Bottom gate MOS tube and manufacturing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10895774B2 (en) | Array substrate, manufacturing method, display panel and display device | |
| CN106558593B (en) | Array substrate, display panel, display device and preparation method of array substrate | |
| US10109647B2 (en) | MOTFT with un-patterned etch-stop | |
| US10367073B2 (en) | Thin film transistor (TFT) with structured gate insulator | |
| JP5775253B2 (en) | Thin film transistor substrate and manufacturing method thereof | |
| CN109148482B (en) | Display back plate, preparation method thereof and display device | |
| WO2016165186A1 (en) | Manufacturing method for dual-gate oxide semiconductor tft substrate, and structure of dual-gate oxide semiconductor tft substrate | |
| WO2018099052A1 (en) | Method for manufacturing array substrate, array substrate and display apparatus | |
| US8440483B2 (en) | Method of fabricating array substrate | |
| WO2016165187A1 (en) | Manufacturing method for dual-gate oxide semiconductor tft substrate, and structure of dual-gate oxide semiconductor tft substrate | |
| US9570483B2 (en) | Flat panel display device with oxide thin film transistor and method of fabricating the same | |
| US8304778B2 (en) | Thin film transistor and pixel structure having the thin film transistor | |
| EP3101693B1 (en) | Methods for thin-film transistor, pixel structure, manufacturing , array substrate and display device | |
| CN111710725A (en) | Double-gate electrode metal oxide thin film transistor and preparation method thereof | |
| WO2016165185A1 (en) | Manufacturing method for dual-gate oxide semiconductor tft substrate, and structure of dual-gate oxide semiconductor tft substrate | |
| WO2016176881A1 (en) | Manufacturing method for dual-gate tft substrate, and structure of dual-gate tft substrate | |
| US8310613B2 (en) | Active matrix substrate and liquid crystal device | |
| WO2017161626A1 (en) | Manufacturing method for tft substrate and manufactured tft substrate | |
| US11895870B2 (en) | Display panel and display device | |
| WO2017161625A1 (en) | Manufacturing method for tft substrate and manufactured tft substrate | |
| CN111710726A (en) | Thin film transistor substrate and preparation method thereof | |
| US9461066B2 (en) | Thin film transistor and method of manufacturing the same, array substrate and display device | |
| WO2016179877A1 (en) | Coplanar oxide semiconductor tft substrate structure and manufacturing method therefor | |
| US8324034B2 (en) | Method of manufacturing display device | |
| CN112909027A (en) | Array substrate with high-capacity capacitor structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200925 |