CN108039353B - Array substrate, preparation method thereof and display device - Google Patents
Array substrate, preparation method thereof and display device Download PDFInfo
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- CN108039353B CN108039353B CN201711435850.4A CN201711435850A CN108039353B CN 108039353 B CN108039353 B CN 108039353B CN 201711435850 A CN201711435850 A CN 201711435850A CN 108039353 B CN108039353 B CN 108039353B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The invention discloses an array substrate, which comprises a pixel structure, wherein the pixel structure is provided with a transistor area, and the pixel structure comprises: a patterned data line extending into the transistor region; a patterned oxide semiconductor layer in the transistor region and connected to the data line; a gate insulating layer covering the data line and the oxide semiconductor layer; a patterned gate line and a gate electrode connected to each other, formed on the gate insulating layer; the gate electrode is positioned in the transistor area and extends from the upper part of the oxide semiconductor layer to two opposite side walls of the oxide semiconductor layer; wherein a portion of the oxide semiconductor layer facing the gate electrode forms a channel region, and portions on both sides of the channel region are formed into a conductor to form a source electrode and a drain electrode. The invention also discloses a preparation method of the array substrate and a display device comprising the array substrate.
Description
Technical Field
The invention relates to the technical field of flat panel display, in particular to an array substrate and a preparation method thereof, and further relates to a display device comprising the array substrate.
Background
The conventional flat panel Display device mainly includes a liquid Crystal Display device (L acquired Crystal Display, L CD) and an Organic electroluminescent Display device (O L ED), and a Thin Film Transistor (TFT) array substrate is an important component of the flat panel Display device and can be formed on a glass substrate or a plastic substrate.
In the conventional technology, as shown in fig. 1, the thin film transistor includes a gate electrode 2 formed on a glass substrate 1, a gate insulating layer 3 disposed on the gate electrode 2, an active layer 4 formed on the gate insulating layer 3, and a source electrode 5 and a drain electrode 6 formed on the active layer 4, wherein the source electrode 5 and the drain electrode 6 are spaced apart from each other, and a region of the active layer 4 corresponding to the source electrode 5 and the drain electrode 6, which are spaced apart from each other, is a channel region 4 a. fig. 2 is a schematic plan view of the thin film transistor, in which only the gate electrode 2, the active layer 4, and the source electrode 5 and the drain electrode 6 of the thin film transistor are shown, wherein the channel region 4a has a length of L and a width of W.
In the design process of the thin film transistor array substrate, the thin film transistor is required to have the characteristics of larger on-state current and smaller off-state current, wherein one method for improving the on-state current is to increase the width-to-length ratio (W/L) of a channel region, the width W is increased or the length L is reduced, in order to ensure the resolution of a display screen, the area of a pixel region needs to be as small as possible, the aperture ratio needs to be as large as possible, and therefore the driving thin film transistor and peripheral circuits cannot exceed a certain area, so that the width W of the channel region of the thin film transistor is limited to be too wide, in this case, the problem that the phenomenon that the width-to-length ratio of the channel region of the thin film transistor needs to be increased can be solved only by reducing the length L, but the phenomenon that the phenomenon of leakage current, channel breakdown and the like are caused when the length L of the channel region of the thin film transistor is reduced to a certain extent, so that the phenomenon that the channel region of the thin film transistor cannot work is always searched.
Disclosure of Invention
In view of the above, the present invention provides an array substrate and a method for manufacturing the same, which are used to increase a width-to-length ratio (W/L) of a channel region of a thin film transistor, so as to increase an on-state current of the thin film transistor and improve a driving capability of the thin film transistor.
In order to achieve the purpose, the invention adopts the following technical scheme:
an array substrate comprising a pixel structure formed on a substrate base, the pixel structure being provided with a transistor region, the pixel structure comprising:
a patterned data line extending into the transistor region;
a patterned oxide semiconductor layer in the transistor region and connected to the data line;
a gate insulating layer covering the data line and the oxide semiconductor layer;
a patterned gate line and a gate electrode connected to each other, formed on the gate insulating layer; the gate electrode is positioned in the transistor area and extends from the upper part of the oxide semiconductor layer to two opposite side walls of the oxide semiconductor layer;
wherein a portion of the oxide semiconductor layer facing the gate electrode forms a channel region, portions on both sides of the channel region are formed into conductors to form a source electrode and a drain electrode, and one of the source electrode and the drain electrode is connected to the data line.
The pixel structure is further provided with a pixel region, and the oxide semiconductor layer further extends into the pixel region; in the pixel region, the oxide semiconductor layer is formed into a conductor to form a pixel electrode.
Wherein the material of the oxide semiconductor layer is selected from any one or more of ZnO, InZnO, ZnSnO, GaInZnO and ZrInZnO.
The gate electrode is coated on the oxide semiconductor layer and two opposite side walls thereof in a 'n' shape.
The invention provides a preparation method of the array substrate, which comprises the following steps:
providing a substrate, depositing a first metal film on the substrate, and patterning the first metal film to form the data line;
depositing an oxide semiconductor film on the substrate, wherein the oxide semiconductor film covers the data line, and the oxide semiconductor film is patterned to form the oxide semiconductor layer;
depositing the gate insulating layer on the substrate, the gate insulating layer covering the data line and the oxide semiconductor layer;
depositing a second metal film on the gate insulating layer, and patterning the second metal film to form the gate line and the gate electrode;
and conducting a conductor treatment on the oxide semiconductor layer by using the gate electrode as a mask, so that the oxide semiconductor layer exposed outside the gate electrode is converted into a conductor.
Wherein the oxide semiconductor layer exposed outside the gate electrode is converted into a conductor using a UV light irradiation process.
Wherein the oxide semiconductor layer exposed outside the gate electrode is converted into a conductor using an ion implantation process or a plasma bombardment process.
Wherein the materials of the first metal film and the second metal film are respectively molybdenum or titanium or the combination of the two.
Wherein the gate insulating layer is made of SiOxOr SiNxOr a combination of both.
The invention also provides a display device which comprises the array substrate, wherein the display device is a liquid crystal display device or an organic electroluminescent display device.
In the thin film transistor, the gate electrode extends to two opposite side walls of the oxide semiconductor layer from the upper part of the oxide semiconductor layer, a channel region formed by the gate electrode has larger channel width, and in addition, the oxide semiconductor layer positioned at two sides of the channel region is conducted to form the source electrode and the drain electrode, so that the channel length is reduced, the width-to-length ratio (W/L) of the channel region of the thin film transistor is increased, the on-state current of the thin film transistor is improved, and the driving capability of the thin film transistor is improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional thin film transistor;
fig. 2 is a schematic plan view of the thin film transistor of fig. 1;
fig. 3 is a schematic plan view of an array substrate according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view taken along line X-X as in FIG. 3;
FIG. 5 is a schematic cross-sectional view taken along line Y-Y of FIG. 3;
fig. 6 is a process flow diagram of a method for manufacturing an array substrate according to an embodiment of the invention;
fig. 7a to 7e are schematic diagrams of device structures obtained in various steps in a method for manufacturing an array substrate according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings. Examples of these preferred embodiments are illustrated in the accompanying drawings. The embodiments of the invention shown in the drawings and described in accordance with the drawings are exemplary only, and the invention is not limited to these embodiments.
It should be noted that, in order to avoid obscuring the present invention with unnecessary details, only the structures and/or processing steps closely related to the scheme according to the present invention are shown in the drawings, and other details not so relevant to the present invention are omitted.
Referring to fig. 3 to 5, fig. 3 is a schematic plan view of the array substrate provided in this embodiment, fig. 4 is a schematic cross-sectional view taken along the X-X line in fig. 3, and fig. 5 is a schematic cross-sectional view taken along the Y-Y line in fig. 3. The array substrate comprises a pixel structure 11 formed on a substrate 10, wherein the pixel structure 11 is provided with a transistor area 11a and a pixel area 11 b. The pixel structure 11 includes a patterned data line 20, a patterned oxide semiconductor layer 30, a gate insulating layer 40, a patterned gate line 50 and gate electrode 60, and a pixel electrode 34.
Specifically, the data line 20 is formed on the substrate base plate 10, and the data line 20 extends into the transistor region 11 a. The oxide semiconductor layer 30 is formed on the substrate 10, the oxide semiconductor layer 30 is located in the transistor region 11a and connected to the data line 20, and in this embodiment, the oxide semiconductor layer 30 further extends into the pixel region 11 b. The gate insulating layer 40 is formed on the base substrate 10, and the gate insulating layer 40 covers the data line 20 and the oxide semiconductor layer 30. The gate line 50 and the gate electrode 60 are formed on the gate insulating layer 40 and connected to each other, the gate electrode 60 is located in the transistor region 11a, and the gate electrode 60 extends from above the oxide semiconductor layer 30 to opposite sidewalls of the oxide semiconductor layer 30.
Wherein a portion of the oxide semiconductor layer 30 facing the gate electrode 60 forms a channel region 31, portions on both sides of the channel region 31 are conductively formed to form a source electrode 32 and a drain electrode 33, and a portion of the oxide semiconductor layer 30 extending into the pixel region 11b is conductively formed to form the pixel electrode 34. One of the source electrode 32 and the drain electrode 33 is connected to the data line 20, and the other is connected to the pixel electrode 34.
In the present embodiment, as shown in fig. 5, the gate electrode 60 is wrapped over the oxide semiconductor layer 30 (corresponding to the channel region 31) and on the two opposite sidewalls thereof in a "zigzagged shape.
The gate electrode 60 and the channel region 31, the source electrode 32 and the drain electrode 33 formed in the oxide semiconductor layer 30 form a thin film transistor structure, in the thin film transistor, on one hand, the gate electrode 60 extends from the upper part of the channel region 31 to two opposite side walls of the channel region 31, the channel width can be increased in the vertical direction without increasing the area of the thin film transistor in a plane, and on the other hand, the oxide semiconductor layer on two sides of the channel region 31 is conducted to form the source electrode 32 and the drain electrode 33, the channel length is reduced, based on the improvement of the two aspects, the width-to-length ratio (W/L) of the channel region of the thin film transistor is increased, the on-state current of the thin film transistor is increased, the driving capability of the thin film transistor is improved, and the thin film transistor can reduce the size of a device of the thin film transistor and improve the aperture ratio of a pixel structure while the width-to-length ratio of the channel region is increased.
The present embodiment further provides a method for manufacturing the array substrate, and a process of the manufacturing method is described below with reference to fig. 6 and fig. 7a to 7e in conjunction with fig. 3 to 5, wherein fig. 7a to 7e are schematic cross-sectional views corresponding to the positions of X-X in fig. 3. As shown in fig. 6, the preparation method includes the steps of:
s10, as shown in fig. 7a, providing a substrate 10, depositing a first metal film 20a on the substrate 10, and patterning the first metal film 20a to form the data line 20.
Wherein, the substrate base plate 10 is selected to be a glass base plate. The material of the first metal thin film 20a may be selected to be molybdenum (Mo) or titanium (Ti) or a combination thereof, and the thickness of the first metal thin film 20a may be selected to be
S20, as shown in fig. 7b, an oxide semiconductor thin film 30a is deposited on the base substrate 10, and the oxide semiconductor thin film 30a is patterned to form the oxide semiconductor layer 30.
Specifically, the oxide semiconductor thin film 30a is deposited on the base substrate 10, and the oxide semiconductor thin film 30a covers the data line 20. After the oxide semiconductor layer 30 is patterned, the oxide semiconductor layer 30 is connected to the data line 20.
Wherein the material of the oxide semiconductor layer 30 is selected from any one or more of ZnO, InZnO, ZnSnO, GaInZnO and ZrInZnO, and the thickness of the metal oxide thin film 30a can be selected as
S30, as shown in fig. 7c, the gate insulating layer 40 is deposited on the substrate 10, and the gate insulating layer 40 covers the data line 20 and the oxide semiconductor layer 30.
Wherein the gate insulating layer 40 is made of SiOxOr SiNxOr a combination of both, the thickness of the gate insulation layer 40 may be selected to be
S40, as shown in fig. 7d, depositing a second metal film 50a on the gate insulating layer 40, and patterning the second metal film 50a to form the gate line 50 and the gate electrode 60.
Wherein the material of the second metal film 50a can be selected to be molybdenum (Mo) or titanium (Ti) or a combination thereof, and the thickness of the second metal film 50a can be selected to be
Referring to fig. 3 to 5, the gate electrode 60 is located in the transistor region 11a, and the gate electrode 60 extends from above the oxide semiconductor layer 30 to opposite sidewalls of the oxide semiconductor layer 30.
S50, as shown in fig. 7e, the oxide semiconductor layer 30 is subjected to a conductor-forming process using the gate electrode 60 as a mask, and the oxide semiconductor layer 30 exposed to the outside of the gate electrode 60 is converted into a conductor. After the conductor forming process, the oxide semiconductor layer 30 is kept as a semiconductor by the gate electrode 60 to form a channel region 31, and the remaining portion of the oxide semiconductor layer 30 is converted into a conductor except for the channel region 31. Wherein portions on both sides of the channel region 31 are conductively formed into a source electrode 32 and a drain electrode 33, and the oxide semiconductor layer 30 in the pixel region 11b is conductively formed into a pixel electrode 34, thereby preparing an array substrate as shown in fig. 3.
In this embodiment, the oxide semiconductor layer exposed outside the gate electrode is converted into a conductor using a UV light irradiation process, as indicated by a dotted arrow 70 in fig. 7 e. In other embodiments, an ion implantation process or a plasma bombardment process may be used to convert the oxide semiconductor layer 30 exposed outside the gate electrode 60 into a conductor.
Specifically, taking the thin film transistor liquid crystal display device as an example, referring to fig. 8, the liquid crystal display device includes a liquid crystal panel 100 and a backlight module 200, the liquid crystal panel 100 is disposed opposite to the backlight module 200, the backlight module 200 provides a display light source to the liquid crystal panel 100, so that the liquid crystal panel 100 displays an image, wherein the liquid crystal panel 100 includes an array substrate 101 and a filter substrate 102 disposed opposite to each other, and further includes a liquid crystal layer 103 disposed between the array substrate 101 and the filter substrate 102, wherein the array substrate 101 employs the thin film transistor array substrate provided by the embodiment of the invention.
In summary, the present invention provides an array substrate and a method for fabricating the same, which can increase the width-to-length ratio (W/L) of the channel region of the thin film transistor on the array substrate, improve the on-state current of the thin film transistor, and improve the driving capability of the thin film transistor.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing is directed to embodiments of the present application and it is noted that numerous modifications and adaptations may be made by those skilled in the art without departing from the principles of the present application and are intended to be within the scope of the present application.
Claims (10)
1. An array substrate, comprising a pixel structure formed on a substrate, the pixel structure being provided with a transistor region, wherein the pixel structure comprises:
a patterned data line extending into the transistor region;
a patterned oxide semiconductor layer in the transistor region and connected to the data line;
a gate insulating layer covering the data line and the oxide semiconductor layer;
a patterned gate line and a gate electrode connected to each other, formed on the gate insulating layer; the gate electrode is positioned in the transistor area and extends from the upper part of the channel area of the oxide semiconductor layer to two opposite side walls of the channel area of the oxide semiconductor layer, so that the gate electrode and the two side walls have mutually overlapped parts;
wherein a portion of the oxide semiconductor layer facing the gate electrode forms a channel region, portions on both sides of the channel region are formed into conductors to form a source electrode and a drain electrode, and one of the source electrode and the drain electrode is connected to the data line.
2. The array substrate of claim 1, wherein the pixel structure is further provided with a pixel region, and the oxide semiconductor layer further extends into the pixel region; in the pixel region, the oxide semiconductor layer is formed into a conductor to form a pixel electrode.
3. The array substrate according to claim 1 or 2, wherein the material of the oxide semiconductor layer is selected from any one or more of ZnO, InZnO, ZnSnO, GaInZnO and ZrInZnO.
4. The array substrate of claim 1 or 2, wherein the gate electrode is wrapped over the oxide semiconductor layer and on two opposite sidewalls thereof in a shape of a "few".
5. A method for preparing the array substrate according to any one of claims 1 to 4, comprising:
providing a substrate, depositing a first metal film on the substrate, and patterning the first metal film to form the data line;
depositing an oxide semiconductor film on the substrate, wherein the oxide semiconductor film covers the data line, and the oxide semiconductor film is patterned to form the oxide semiconductor layer;
depositing the gate insulating layer on the substrate, the gate insulating layer covering the data line and the oxide semiconductor layer;
depositing a second metal film on the gate insulating layer, and patterning the second metal film to form the gate line and the gate electrode;
and conducting a conductor treatment on the oxide semiconductor layer by using the gate electrode as a mask, so that the oxide semiconductor layer exposed outside the gate electrode is converted into a conductor.
6. The method of claim 5, wherein the oxide semiconductor layer exposed outside the gate electrode is converted into a conductor by a UV light irradiation process.
7. The method of claim 5, wherein the oxide semiconductor layer exposed outside the gate electrode is converted into a conductor by an ion implantation process or a plasma bombardment process.
8. The method of claim 5, wherein the first metal film and the second metal film are made of molybdenum or titanium or a combination thereof.
9. The method for manufacturing the array substrate according to claim 5, wherein the gate insulating layer is made of SiOxOr SiNxOr a combination of both.
10. A display device comprising the array substrate according to any one of claims 1 to 4, wherein the display device is a liquid crystal display device or an organic electroluminescent display device.
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| CN108039353B true CN108039353B (en) | 2020-07-21 |
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| CN111045266A (en) * | 2019-12-31 | 2020-04-21 | 成都中电熊猫显示科技有限公司 | Array substrate and manufacturing method thereof |
| CN111180471A (en) * | 2020-03-02 | 2020-05-19 | 南京中电熊猫平板显示科技有限公司 | Array substrate and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101226311A (en) * | 2007-01-16 | 2008-07-23 | 株式会社日立显示器 | Display device |
| CN103745978B (en) * | 2014-01-03 | 2016-08-17 | 京东方科技集团股份有限公司 | Display device, array base palte and preparation method thereof |
| CN107425075A (en) * | 2017-05-17 | 2017-12-01 | 厦门天马微电子有限公司 | Film transistor device and its manufacture method, array base palte and display device |
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| JP2007073705A (en) * | 2005-09-06 | 2007-03-22 | Canon Inc | Oxide-semiconductor channel film transistor and its method of manufacturing same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101226311A (en) * | 2007-01-16 | 2008-07-23 | 株式会社日立显示器 | Display device |
| CN103745978B (en) * | 2014-01-03 | 2016-08-17 | 京东方科技集团股份有限公司 | Display device, array base palte and preparation method thereof |
| CN107425075A (en) * | 2017-05-17 | 2017-12-01 | 厦门天马微电子有限公司 | Film transistor device and its manufacture method, array base palte and display device |
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