CN111045266A

CN111045266A - Array substrate and manufacturing method thereof

Info

Publication number: CN111045266A
Application number: CN201911407686.5A
Authority: CN
Inventors: 李智炜; 徐威; 殷桂华; 胡珂; 刘翔; 李广圣
Original assignee: Chengdu CEC Panda Display Technology Co Ltd
Current assignee: Chengdu CEC Panda Display Technology Co Ltd
Priority date: 2019-12-31
Filing date: 2019-12-31
Publication date: 2020-04-21

Abstract

The invention provides an array substrate and a manufacturing method thereof. The array substrate comprises a substrate, a grid arranged on the substrate, an insulating layer covering the grid and the substrate, and a semiconductor layer covering the insulating layer, wherein the semiconductor layer is provided with a first interval and a second interval, the first interval and the second interval divide the semiconductor layer into a first semiconductor part, a second semiconductor part and a third semiconductor part, and a source electrode and a drain electrode are respectively arranged in the first interval and the second interval; wherein the third semiconductor portion adjacent to one side of the drain electrode is formed into a conductor to form a pixel electrode. The array substrate has good performance, and the manufacturing process of the array substrate is simple and the manufacturing cost is low.

Description

Array substrate and manufacturing method thereof

Technical Field

The invention relates to the technical field of liquid crystal display, in particular to an array substrate and a manufacturing method thereof.

Background

The liquid crystal display panel generally comprises an array substrate, a color film substrate and a liquid crystal molecular layer clamped between the array substrate and the color film substrate, which are arranged oppositely, and the liquid crystal molecular layer can be controlled to rotate by applying a driving voltage between the array substrate and the color film substrate, so that light rays of the backlight module are refracted out to generate a picture.

The array substrate in the prior art is generally formed by depositing a metal layer on a glass substrate, and forming the metal layer into a gate by a photolithography process; sequentially depositing a grid electrode insulating layer and a semiconductor layer on the glass substrate and the grid electrode, and forming an active island pattern through a photoetching process; then depositing a source drain metal layer on the semiconductor layer, and forming a source electrode and a drain electrode through a photoetching process; depositing a passivation layer on the semiconductor layer and the source electrode and the drain electrode, and forming a conductive through hole communicated to the surface of the semiconductor layer on the surface of the passivation layer through a photoetching process; and finally, depositing a transparent conductive film on the passivation layer, and forming a pixel electrode and a communication pattern of the conductive through hole and the pixel electrode through a photoetching process.

However, the performance of the semiconductor layer of the array substrate in the prior art is not good, and the process for manufacturing the array substrate is complicated and the manufacturing cost is high.

Disclosure of Invention

The invention provides an array substrate and a manufacturing method thereof, the performance of the array substrate is better, the manufacturing process of the array substrate is simpler, and the manufacturing cost is lower.

In one aspect, the present invention provides an array substrate, including a substrate, a gate disposed on the substrate, an insulating layer covering the gate and the substrate, and a semiconductor layer covering the insulating layer, wherein the semiconductor layer has a first interval and a second interval, the first interval and the second interval divide the semiconductor layer into a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion, and a source and a drain are disposed in the first interval and the second interval, respectively; wherein the third semiconductor portion adjacent to one side of the drain electrode is formed into a pixel electrode by conductor formation;

the upper part of the source electrode is attached to the surface of the semiconductor layer, and the lower part of the source electrode extends into the first interval and is attached to the insulating layer; the two sides of the upper part of the drain electrode are respectively attached to the surfaces of the second semiconductor part and the pixel electrode, and the lower part of the drain electrode extends into the second interval and is attached to the insulating layer;

the semiconductor device further comprises a barrier layer arranged on the semiconductor layer, wherein the barrier layer comprises a first barrier portion and a second barrier portion, the first barrier portion is located on the first semiconductor portion, the second barrier portion is located on the second semiconductor portion, a third interval is arranged between the first barrier portion and the second barrier portion, the third interval corresponds to the first interval, and two sides of the second semiconductor portion are exposed outside the second barrier portion.

Optionally, the blocking layer further includes a third blocking portion located on the pixel electrode, a fourth space is formed between the second blocking portion and the third blocking portion, the fourth space corresponds to the second space, and one side of the pixel electrode adjacent to the drain electrode is exposed outside the third blocking portion.

Optionally, the upper portion of the source is located in the third space, and two side edges of the upper portion of the source are respectively in contact with the first blocking portion and the second blocking portion; the upper part of the drain electrode is positioned in the fourth interval, and two side edges of the upper part of the drain electrode are respectively contacted with the second blocking part and the third blocking part.

Optionally, the array substrate further includes a planarization layer disposed on the barrier layer, and the planarization layer covers the array substrate.

In another aspect, the present invention provides a method for manufacturing an array substrate, including the following steps:

forming a gate electrode on a substrate;

sequentially forming an insulating layer, a semiconductor layer and a barrier layer on the substrate and the grid;

patterning the semiconductor layer by a photolithography process; wherein the semiconductor layer is patterned into a first semiconductor section, a second semiconductor section, and a third semiconductor section, the second semiconductor section and the first semiconductor section and the third semiconductor section having a first space and a second space therebetween, respectively;

etching the barrier layer to pattern the barrier layer so that both sides of the second semiconductor portion and one side of the third semiconductor portion adjacent to the second semiconductor portion are exposed outside the etched barrier layer;

conducting both sides of the second semiconductor portion exposed outside the barrier layer to form contacts connected to the source and drain electrodes on both sides of the second semiconductor portion, respectively, and conducting the third semiconductor portion to form a pixel electrode;

and forming a source electrode and a drain electrode at the first interval and the second interval respectively by a photolithography process, wherein opposite sides of the source electrode and the drain electrode are both in contact with the second semiconductor portion, and the other side of the drain electrode is in contact with the pixel electrode.

Optionally, patterning the semiconductor layer by a photolithography process specifically includes:

arranging a photoresist layer on the barrier layer;

exposing and developing the photoresist layer by adopting a half-tone mask plate to form a photoresist layer pattern; the photoresist layer pattern comprises a non-photoresist area, a semi-photoresist area and a full-photoresist area; the non-photoresist area comprises a first non-photoresist area and a second non-photoresist area, and the semi-photoresist area comprises a first semi-photoresist area, a second semi-photoresist area and a third semi-photoresist area; the first photoresist-free area and the second photoresist-free area correspond to a first interval and a second interval respectively, the first half photoresist area and the second half photoresist area are adjacent to the first photoresist-free area and the second photoresist-free area respectively and located between the first photoresist-free area and the second photoresist-free area and correspond to two sides of the second semiconductor part exposed outside the barrier layer, the third half photoresist area is adjacent to the other side of the second photoresist-free area, and the photoresist layer is a full photoresist area except the photoresist-free area and the half photoresist area;

and etching the barrier layer and the semiconductor layer with the photoresist layer pattern as a protection layer to form a first semiconductor portion, a second semiconductor portion and a third semiconductor portion in the semiconductor layer.

Optionally, etching the barrier layer to pattern the barrier layer specifically includes:

after the semiconductor layer is patterned, ashing the photoresist layer pattern to remove the half photoresist region and thin the full photoresist region;

and etching the barrier layer by taking the ashed photoresist layer pattern as protection, and removing the photoresist layer after etching to form the patterned barrier layer.

Optionally, the third half photoresist region completely covers the third semiconductor portion, and the third semiconductor portion is conducted with a conductor to form a pixel electrode, which specifically includes:

and ashing the photoresist layer pattern and etching the barrier layer to form a patterned barrier layer, exposing the third semiconductor part, and performing plasma treatment on the exposed semiconductor layer to make the third semiconductor part be conductive to form a pixel electrode.

Optionally, the third half photoresist region partially covers the third semiconductor portion, and the third semiconductor portion is conducted with a conductor to form a pixel electrode, which specifically includes:

and after ashing the photoresist layer pattern and etching the barrier layer to form a patterned barrier layer, partially exposing one side of the third semiconductor part adjacent to the drain electrode, and performing laser annealing treatment from the substrate to the direction of the semiconductor layer to make the third semiconductor part be a conductor to form a pixel electrode.

Optionally, after forming the source and the drain, the method further includes: and forming a flat layer on the barrier layer so that the flat layer covers the array substrate.

The array substrate comprises a substrate, wherein a grid electrode is arranged on the substrate, an insulating layer and a semiconductor layer are sequentially covered on the substrate and the grid electrode, the semiconductor layer is divided into a first semiconductor part, a second semiconductor part and a third semiconductor part by enabling the semiconductor layer to have a first interval and a second interval, a source electrode and a drain electrode are respectively arranged in the first interval and the second interval, and a thin film transistor structure is formed by the source electrode, the drain electrode and the second semiconductor part between the source electrode and the drain electrode so as to control the pixel electrode to work; the first interval and the second interval are arranged on the semiconductor layer, so that the source electrode and the drain electrode are respectively positioned in the first interval and the second interval, the positions of the source electrode and the drain electrode can be better positioned, and the performance of a thin film transistor structure formed among the source electrode, the drain electrode and the second semiconductor part can be improved; and the second interval separates the third semiconductor part from the semiconductor layer, and the third semiconductor part is conducted to form a conductor to form a pixel electrode, so that the pixel electrode can be positioned in the semiconductor layer and directly connected with the drain electrode, and a transparent conductive film does not need to be arranged on the array substrate, thereby not only improving the utilization rate of the semiconductor layer, but also reducing the manufacturing cost of the array substrate, and simultaneously reducing the thickness of the array substrate.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description will be given below of the drawings required for the description of the embodiments or the prior art, and it is apparent that the drawings in the following description are some embodiments of the present invention. For a person skilled in the art, without inventive effort, further figures can be obtained from these figures.

Fig. 1 is a schematic flow chart illustrating a manufacturing method of an array substrate according to a first embodiment and a second embodiment of the present invention;

fig. 2 is a schematic flow chart of patterning a semiconductor layer by a photolithography process according to the first embodiment and the second embodiment of the present invention;

fig. 3 is a schematic flow chart of etching a barrier layer according to the first embodiment and the second embodiment of the present invention;

fig. 4 is a schematic structural diagram of a gate formed on a surface of a substrate according to an embodiment of the invention;

FIG. 5 is a schematic structural diagram of a substrate and a gate overlying an insulating layer according to an embodiment of the invention;

fig. 6 is a schematic structural diagram of sequentially forming a semiconductor layer, a barrier layer and a photoresist layer on an insulating layer according to a first embodiment of the present invention;

FIG. 7 is a schematic structural diagram illustrating a photoresist layer pattern formed according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a semiconductor layer pattern formed by etching according to an embodiment of the present invention;

FIG. 9 is a schematic diagram illustrating a structure of an ashed photoresist layer pattern according to one embodiment of the present invention;

fig. 10 is a schematic structural diagram of a barrier layer pattern formed by etching according to an embodiment of the invention;

FIG. 11 is a schematic structural diagram of a third semiconductor portion with a photoresist layer removed and a conductor formed according to an embodiment of the present invention;

FIG. 12 is a top view of FIG. 11;

fig. 13 is a schematic structural diagram of forming a source and a drain according to a first embodiment of the invention;

FIG. 14 is a schematic diagram illustrating a structure of forming a planarization layer on a barrier layer according to an embodiment of the present invention;

FIG. 15 is a top view of FIG. 14;

fig. 16 is a schematic structural diagram of a gate formed on a surface of a substrate according to a second embodiment of the present invention;

fig. 17 is a schematic structural view of a substrate and a gate overlying an insulating layer according to a second embodiment of the present invention;

fig. 18 is a schematic structural view illustrating a semiconductor layer, a barrier layer and a photoresist layer sequentially formed on an insulating layer according to a second embodiment of the present invention;

FIG. 19 is a schematic structural diagram illustrating a photoresist layer pattern formed according to a second embodiment of the present invention;

fig. 20 is a schematic structural diagram of a semiconductor layer pattern formed by etching according to the second embodiment of the present invention;

FIG. 21 is a schematic structural view of a pattern of an ashed photoresist layer provided in accordance with a second embodiment of the present invention;

fig. 22 is a schematic structural diagram of a barrier layer pattern formed by etching according to the second embodiment of the present invention;

FIG. 23 is a schematic structural diagram of a second semiconductor portion with a photoresist layer removed and a third semiconductor portion conductively formed according to an embodiment of the present invention;

fig. 24 is a schematic structural diagram of forming a source and a drain according to a second embodiment of the present invention;

fig. 25 is a schematic structural diagram of forming a planarization layer on a barrier layer according to a second embodiment of the present invention.

Description of reference numerals:

1-a substrate;

2-a gate metal layer; 21-scanning line; 22-a gate;

3-an insulating layer;

4-a semiconductor layer;

41-a first semiconductor portion; 42-a second semiconductor portion; 43 a-a third semiconductor portion; 43 b-pixel electrodes; 44-a first interval; 45-second interval;

5-a barrier layer;

51-a first barrier; 52-a second barrier; 53-a third barrier; 54-a third interval; 55-fourth interval;

61-data lines; 62-source electrode; 63-a drain electrode;

7-a planarization layer;

8-a photoresist layer;

81-no photoresist regions; 82-half photoresist area; 83-all photoresist region;

811-first photoresist-free region; 812-a second non-photoresist region; 821-a first half photoresist region; 822-a second half photoresist area; 823-third half photoresist area;

9-mask plate; 9 a-halftone mask;

91-a light-transmitting region; 92-opaque region; 93-semi-opaque region.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example one

Fig. 1 is a schematic flow chart illustrating a manufacturing method of an array substrate according to a first embodiment and a second embodiment of the present invention. As shown in fig. 1, the method for manufacturing the array substrate 1 according to the present embodiment includes the following steps:

s100, a gate 22 is formed on the substrate 1.

Fig. 4 is a schematic structural diagram of a gate formed on a surface of a substrate according to an embodiment of the invention. Referring to fig. 4, in a process flow of manufacturing the array substrate 1, first, a substrate 1 needs to be provided, where the substrate 1 may be a transparent substrate 1, for example, the substrate 1 is a glass substrate 1; then, a gate 22 is formed on the substrate 1, specifically, a gate metal layer 2 is first deposited on the substrate 1, and the thickness of the gate metal layer 2 may be about

The gate metal layer 2 may be deposited on the substrate 1 by a sputtering or thermal evaporation process, wherein the gate metal layer 2 may be made of a metal or alloy material such as Cr, W, Cu, Ti, Ta, Mo, or the like, and the gate metal layer 2 composed of multiple metal layers may also meet functional requirements, which is not specifically limited in this embodiment.

After the gate metal layer 2 is formed, the gate metal layer 2 needs to be patterned into the gate 22 through a first photolithography process, as shown in fig. 4, a photoresist layer 8 may be coated on the gate metal layer 2, for example, the photoresist layer 8 may be a photoresist layer, by providing a light-transmitting region 91 and a light-blocking region 92 on the mask 9, ultraviolet light is irradiated onto the surface of the photoresist layer 8 through the mask 9, which causes a chemical reaction of the photoresist in the exposed region of the photoresist layer 8, and the photoresist in the exposed region (positive photoresist) or the photoresist in the unexposed region (negative photoresist) is removed by dissolving through a developing technique.

Referring to fig. 4, for example, the photoresist layer 8 of this embodiment is a positive photoresist, the region of the mask 9 corresponding to the gate 22 is an opaque region 92, the rest is a transparent region 91, the region of the mask 9 irradiated by the ultraviolet light through the transparent region 91 of the mask 9 onto the photoresist layer 8 is an exposed region of the photoresist layer 8, that is, the exposed region is the other region except the gate 22, the photoresist in the exposed region is removed by a developing technique, the remaining photoresist in the photoresist layer 8 only covers the region of the gate metal layer 2 corresponding to the gate 22, and the other region of the gate metal layer 2 is exposed, at this time, the exposed gate metal layer 2 is etched again, finally only the gate 22 is remained, and finally, the photoresist covering the gate 22 is removed again, so that the gate 22 can be formed on the substrate 1.

Of course, the photoresist layer 8 of this embodiment may also adopt a negative photoresist, and at this time, the region on the mask 9 corresponding to the gate 22 may be a light-transmitting region 91, and the rest are light-blocking regions 92, and the exposed region of the photoresist layer 8 where the chemical reaction occurs is the region corresponding to the gate 22, and then the photoresist in the unexposed region is removed by a developing technique, that is, the other regions on the photoresist layer 8 except the region corresponding to the gate 22 are removed, and then the exposed gate metal layer 2 is etched, which is not described herein again.

It can be understood that, the exposure and development process for transferring the mask pattern on the mask plate 9 to the photoresist layer 8 to form the pattern of the photoresist layer 8 by irradiating the photoresist layer 8 with ultraviolet light through the mask plate 9, and the process for etching the region not covered by the photoresist layer 8 after forming the pattern of the photoresist layer 8 are the same as or similar to the above process flows, and the exposure, development and etching processes occurring after this embodiment are not described in detail.

In addition, in practical applications, the array substrate 1 includes a plurality of sub-pixel regions separated by a plurality of scan lines 21 and a plurality of data lines 61, each sub-pixel region is provided with a thin film transistor device, and for convenience of description, a schematic diagram of manufacturing only one sub-pixel region is drawn in the drawings of the present embodiment. It can be understood that the array substrate 1 in this embodiment includes a plurality of sub-pixel regions, and therefore, in the manufacturing process of the array substrate 1 in this embodiment, the step of forming the gate 22 on the substrate 1 specifically means that the gate 22 is formed at a position corresponding to each sub-pixel region of the array substrate 1, and the conditions of patterning the semiconductor layer 4 and forming the source electrode 62 and the drain electrode 63 are the same or similar to each other, and are not repeated herein.

S200, an insulating layer 3, a semiconductor layer 4, and a barrier layer 5 are sequentially formed on the substrate 1 and the gate electrode 22.

Fig. 5 is a schematic structural diagram of a substrate and a gate overlying insulating layer according to an embodiment of the invention. Referring to fig. 1 and 5, after the gate 22 is formed on the substrate 1, the insulating layer 3 is formed on the substrate 1 and the gate 22, such that the insulating layer 3 covers the substrate 1 and the gate 22, the insulating layer 3 is mainly used for protecting the gate 22, and the gate 22 is insulated from the source 62, the drain 63 and the semiconductor layer 4, so as to ensure the performance of the gate 22, and the insulating layer 3 can also protect the gate 22 from being etched in the subsequent etching process.

Illustratively, the insulating layer 3 may be continuously deposited by a vapor deposition method of plasma enhanced chemistry, and the deposition thickness of the insulating layer 3 may be

The insulating layer 3 may be made of oxide, nitride or oxynitride material, and the corresponding reaction gas may be SiH₄Or N₂O, etc., wherein the reaction gas corresponding to the formation of the nitride or oxynitride may be SiH₄、NH₃、N₂Or SiH₂Cl₂、NH₃、N₂。

Fig. 6 is a schematic structural diagram of sequentially forming a semiconductor layer, a barrier layer, and a photoresist layer on an insulating layer according to a first embodiment of the present invention. Referring to fig. 1 and 6, after depositing an insulating layer 3 on a substrate 1 and a gate electrode 22, and then sequentially depositing a semiconductor layer 4 and a barrier layer 5 on the insulating layer 3, wherein the semiconductor layer 4 may be deposited by sputtering or thermal evaporation, and the deposition thickness of the semiconductor layer 4 may be about

The material of the semiconductor layer 4 is usually a metal oxide, and for example, amorphous IGZO, HIZO, IZO, a-InZnO, ZnO: F, In can be used for the semiconductor layer 4₂O₃:Sn、In₂O₃:Mo、Cd₂SnO₄、ZnO:Al、TiO₂Nb, Cd-Sn-O or other metal oxides.

Preferably, the semiconductor layer 4 may be an indium gallium zinc oxide IGZO semiconductor layer 4, the IGZO semiconductor layer 4 may reduce power consumption of the display screen, and the cost is low, so that the response speed of the pixel may be better improved, and the faster response speed also greatly improves the line scanning rate of the pixel, thereby improving the resolution of the display screen.

After the semiconductor layer 4 is deposited on the insulating layer 3, a barrier layer 5 may be further deposited on the semiconductor layer 4, the barrier layer 5 may be formed by a continuous deposition through a plasma enhanced chemical vapor deposition method, and the deposition thickness of the barrier layer 5 may be, for example

The barrier layer 5 may be an oxide, nitride or oxynitride, and the reaction gas corresponding to the silicon oxide may be SiH₄And N₂The gas corresponding to O, nitride or oxynitride may be SiH₄、NH₃And N₂Or SiH₂Cl₂、NH₃And N₂(ii) a The barrier layer 5 may also be made of Al₂O₃Or a double-layer barrier structure.

It should be noted that, in the present embodiment, by providing the barrier layer 5 on the semiconductor layer 4, disposing the body structure of the source electrode 62 and the drain electrode 63 on the barrier layer 5, and contacting the source electrode 62 and the drain electrode 63 with the semiconductor layer 4 below the barrier layer 5, compared with the prior art in which the barrier layer 5 is not provided, but the source electrode 62 and the drain electrode 63 are directly formed on the semiconductor layer 4 through a photolithography process, since the barrier layer 5 is provided on the semiconductor layer 4, when the source electrode 62 and the drain electrode 63 are formed, the barrier layer 5 can better define the positions of the source electrode 62 and the drain electrode 63, which can improve the performance of the thin film transistor formed by connecting the source electrode 62 and the drain electrode 63 with the semiconductor layer 4.

In addition, since the source electrode 62 and the drain electrode 63 are formed by the photolithography process, the barrier layer 5 can prevent the etching liquid from directly affecting or corroding the semiconductor layer 4 in the process of etching the source electrode 62 and the drain electrode 63, and the barrier layer 5 can protect the semiconductor layer 4 from being damaged, so that the performance of the semiconductor layer 4 can be improved, the working stability of the semiconductor layer 4 can be improved, the threshold drift voltage of the thin film transistor can be reduced, and the performance of the thin film transistor can be remarkably improved.

Referring to fig. 6, after forming the barrier layer 5 on the semiconductor layer 4, a photoresist layer 8 is coated on the barrier layer 5, the photoresist layer 8 is set to prepare for the next photolithography process, the photoresist layer 8 is exposed and developed through a mask 9 to form a desired pattern of the photoresist layer 8, and then the semiconductor layer 4 is etched using the pattern of the photoresist layer 8 as a protection to pattern the semiconductor layer 4.

S300, patterning the semiconductor layer 4 through a photoetching process; the semiconductor layer 4 is patterned into a first semiconductor section 41, a second semiconductor section 42, and a third semiconductor section 43a, and the second semiconductor section 42 and the first semiconductor section 41 and the third semiconductor section 43a have a first gap 44 and a second gap 45, respectively.

Fig. 2 is a schematic flow chart of patterning a semiconductor layer by a photolithography process according to the first embodiment and the second embodiment of the present invention. Referring to fig. 1 and 2, after the semiconductor layer 4 and the barrier layer 5 are formed, a second photolithography process is then performed to pattern the semiconductor layer 4, thereby forming regions where the source electrode 62 and the drain electrode 63 are disposed on the semiconductor layer 4. The patterned semiconductor layer 4 includes a first semiconductor portion 41, a second semiconductor portion 42, and a third semiconductor portion 43a, a first space 44 is provided between the first semiconductor portion 41 and the second semiconductor portion 42, and a second space 45 is provided between the second semiconductor portion 42 and the third semiconductor portion 43a, so that the semiconductor layer 4 is divided into three parts spaced apart from each other, and the first space 44 and the second space 45 are formed to correspond to the source electrode 62 and the drain electrode 63, respectively, that is, the positions of the source electrode 62 and the drain electrode 63 are defined by the first space 44 and the second space 45.

In this embodiment, the semiconductor layer 4 is patterned into the first semiconductor portion 41, the second semiconductor portion 42 and the third semiconductor portion 43a, the first space 44 between the second semiconductor portion 42 and the first semiconductor portion 41 may be used to provide the source electrode 62, the second space 45 between the second semiconductor portion 42 and the third semiconductor portion 43a may be used to provide the drain electrode 63, the source electrode 62, the drain electrode 63 and the second semiconductor portion 42 therebetween form a thin film transistor, the positions of the source electrode 62 and the drain electrode 63 may be more precisely defined by the first space 44 and the second space 45, the alignment requirement during the process is reduced, the performance of the thin film transistor may be improved, and the barrier layer 5 is provided on the semiconductor layer 4, so that the performance of the thin film transistor may be further improved by the protective effect of the barrier layer 5 on the semiconductor layer 4.

The patterning of the semiconductor layer 4 by the photolithography process may specifically include:

and S310, arranging a photoresist layer 8 on the barrier layer 5.

Referring to fig. 2 and 6, after the photoresist layer 8 is coated on the barrier layer 5 and the photoresist layer 8 is patterned by the second photolithography process, the photoresist layer 8 pattern may be used as a protection to etch the semiconductor layer 4, so as to pattern the semiconductor layer 4, and therefore, the photoresist layer 8 needs to be firstly disposed on the barrier layer 5 to satisfy the conditions of the second photolithography process, which is not described herein again.

S320, exposing and developing the photoresist layer 8 by adopting a half-tone mask 9a to form a photoresist layer 8 pattern; the photoresist layer 8 pattern comprises a photoresist-free region 81, a half-photoresist region 82 and a full-photoresist region 83; the non-photoresist region 81 includes a first non-photoresist region 811 and a second non-photoresist region 812, and the half-photoresist region 82 includes a first half-photoresist region 821, a second half-photoresist region 822, and a third half-photoresist region 823; the first photoresist-free region 811 and the second photoresist-free region 812 correspond to the first space 44 and the second space 45, the first half photoresist region 821 and the second half photoresist region 822 are adjacent to the first photoresist-free region 811 and the second photoresist-free region 812 and located therebetween, and correspond to two sides of the second semiconductor portion exposed outside the barrier layer, the third half photoresist region 823 is adjacent to and disposed on the other side of the second photoresist-free region 812, and the photoresist layer 8 is a full photoresist region 83 except the photoresist-free region 81 and the half photoresist region 82.

Fig. 7 is a schematic structural diagram of forming a photoresist layer pattern according to an embodiment of the present invention. Referring to fig. 2 and 7, in the second photolithography process to form the patterned semiconductor layer 4, the photoresist layer 8 on the barrier layer 5 is first exposed and developed to form a pattern of the photoresist layer 8. Specifically, the halftone mask 9a may be used for exposing and developing the photoresist layer 8, so that the photoresist layer 8 having the photoresist-free region 81, the half photoresist region 82 and the full photoresist region 83 is patterned by the halftone mask 9 a.

As shown in fig. 7, the photoresist-free region 81 of the photoresist layer 8 pattern includes a first photoresist-free region 811 and a second photoresist-free region 812, and the first photoresist-free region 811 may correspond to the first space 44 of the semiconductor layer 4, and the second photoresist-free region 812 may correspond to the second space 45 of the semiconductor layer 4, so that the first photoresist-free region 811 and the second photoresist-free region 812 may expose the barrier layer 5 in the region corresponding to the first space 44 and the second space 45 of the semiconductor layer 4, thereby facilitating the subsequent etching of the barrier layer 5 and the semiconductor layer 4 to form the patterned semiconductor layer 4.

The half-photoresist regions 82 of the photoresist layer 8 pattern include a first half-photoresist region 821 and a second half-photoresist region 822, and the first half-photoresist region 821 and the second half-photoresist region 822 are adjacently located at opposite inner sides of the first non-photoresist region 811 and the second non-photoresist region 812, respectively, so that after the photoresist layer 8 pattern and the barrier layer 5 are further processed, both sides of the second semiconductor portion 42 can be exposed outside the barrier layer 5 to facilitate the contact of the source electrode 62 and the drain electrode 63 with the second semiconductor portion 42, so that the source electrode 62, the drain electrode 63 and the second semiconductor portion 42 form a thin film transistor.

In addition, the half photoresist region 82 further includes a third half photoresist region 823, such that after the photoresist layer 8 is patterned, at least a region of one side of the third semiconductor portion 43a adjacent to the second semiconductor portion 42 is exposed to facilitate the contact of the drain electrode 63 with the third semiconductor portion 43a, by forming the third half photoresist region 823 on the other side of the second non-photoresist region 812, and the pixel electrode 43b is formed by the third semiconductor portion 43a through the further processing of the third semiconductor portion 43a, such that the drain electrode 63 can be contacted with the pixel electrode 43b to communicate the thin film transistor with the pixel electrode.

It will be appreciated that the regions of the photoresist layer 8 other than the non-photoresist regions 81 and the half-photoresist regions 82 are all-photoresist regions 83, and that the all-photoresist regions 83 do not change during the exposure and development of the photoresist layer 8 using the halftone mask 9a process.

Referring to fig. 7, it should be noted that the structure of the mask pattern of the halftone mask 9a corresponds to the pattern of the photoresist layer 8, and exemplarily, the halftone mask 9a has a light-transmitting region 91, a semi-light-transmitting region 93 and an opaque region 92, for the photoresist layer 8 is a positive photoresist, the light-transmitting region 91 of the halftone mask 9a corresponds to the first non-photoresist region 811 and the second non-photoresist region 812 of the photoresist layer 8, the semi-light-transmitting region 93 corresponds to the first semi-photoresist region 821, the second semi-photoresist region 822 and the third semi-photoresist region 823 of the photoresist layer 8, and the opaque region 92 corresponds to the full-photoresist region 83 of the photoresist layer 8; for a negative photoresist of the photoresist layer 8, the light-transmitting region 91 of the halftone mask 9a corresponds to the full photoresist region 83 of the photoresist layer 8, the semi-light-transmitting region 93 corresponds to the first semi-photoresist region 821, the second semi-photoresist region 822 and the third semi-photoresist region 823 of the photoresist layer 8, and the light-blocking region 92 corresponds to the first non-photoresist region 811 and the second non-photoresist region 812 of the photoresist layer 8.

S330, the barrier layer 5 and the semiconductor layer 4 are etched with the photoresist layer 8 pattern as a protection, so that the first semiconductor portion 41, the second semiconductor portion 42, and the third semiconductor portion 43a are formed in the semiconductor layer 4.

Fig. 8 is a schematic structural diagram of a semiconductor layer pattern formed by etching according to an embodiment of the present invention. Referring to fig. 2 and 8, after the photoresist layer 8 is exposed and developed through the half-tone mask 9a and the photoresist layer 8 is patterned, the barrier layer 5 and the semiconductor layer 4 are etched to pattern the semiconductor layer 4, thereby forming a first semiconductor portion 41, a second semiconductor portion 42, and a third semiconductor portion 43 a.

Specifically, the semiconductor layer 4 is etched using the pattern of the photoresist layer 8 as a mask, and due to the blocking of the full photoresist region 83 and the half photoresist region 82 of the pattern of the photoresist layer 8, only the region of the semiconductor layer 4 exposed in the non-photoresist region 81 of the photoresist layer 8 is etched, so that the regions corresponding to the first non-photoresist region 811 and the second non-photoresist region 812 are etched to form the first spacer 44 and the second spacer 45, and the semiconductor layer 4 is patterned to form the first semiconductor portion 41, the second semiconductor portion 42, and the third semiconductor portion 43 a.

Since the semiconductor layer 4 is located below the barrier layer 5, before etching the semiconductor layer 4, the barrier layer 5 needs to be etched first, regions of the barrier layer 5 corresponding to the first and

second spaces

44 and 45 of the semiconductor layer 4 are exposed outside the pattern of the photoresist layer 8, and after etching the two regions of the barrier layer 5, the regions of the semiconductor layer 4 corresponding to the first and

second spaces

44 and 45 can be exposed, so that the semiconductor layer 4 can be etched to pattern the semiconductor layer 4.

S400, etching the barrier layer 5 to pattern the barrier layer 5, so that both sides of the second semiconductor portion 42 and a side of the third semiconductor portion 43a adjacent to the second semiconductor portion 42 are exposed outside the etched barrier layer 5.

As shown in fig. 1, after the patterned semiconductor layer 4 is formed, since the barrier layer 5 is disposed on the semiconductor layer 4, the barrier layer 5 needs to be further etched, so that both sides of the second semiconductor portion 42 of the patterned semiconductor layer 4 can be exposed outside the barrier layer 5, and further, after the source electrode 62 and the drain electrode 63 are formed, the source electrode 62 and the drain electrode 63 can be in contact with the exposed second semiconductor portion 42 under the barrier layer 5, so that the thin film transistor structure can be formed between the source electrode 62, the second semiconductor portion 42 and the drain electrode 63.

Meanwhile, after the barrier layer 5 is etched, at least one side of the third semiconductor portion 43a adjacent to the second semiconductor portion 42 is exposed outside the barrier layer 5, and the third semiconductor portion 43a is further processed to be conductive to form the pixel electrode 43b, so that the drain electrode 63 is in contact with one side of the third semiconductor portion 43a adjacent to the second semiconductor portion 42, that is, the drain electrode 63 is in direct contact with the pixel electrode 43b, and the thin film transistor can be connected to the pixel electrode 43 b.

Fig. 3 is a schematic flow chart of etching a barrier layer according to the first embodiment and the second embodiment of the present invention. Referring to fig. 3, etching the barrier layer 5 to pattern the barrier layer 5 may specifically include:

s410, after the semiconductor layer 4 is patterned, the photoresist layer 8 is ashed to remove the half photoresist region 82 and thin the full photoresist region 83.

FIG. 9 is a schematic structural diagram of an ashed photoresist layer pattern according to one embodiment of the present invention. Referring to fig. 3 and 9, after the barrier layer 5 and the semiconductor layer 4 are etched using the pattern of the semiconductor layer 4 as a mask to form a pattern of the semiconductor layer 4, the pattern of the photoresist layer 8 is subjected to ashing treatment, so that the photoresist layer 8 as a whole can be thinned, the original half photoresist region 82 can be removed, only the original all-photoresist region 83 remains, and the thickness of the all-photoresist region 83 is reduced.

Thus, after the half photoresist region 82 originally covering the barrier layer 5 is removed, the region of the barrier layer 5 corresponding to the original half photoresist region 82, that is, the region of the barrier layer 5 corresponding to the first half photoresist region 821, the second half photoresist region 822, and the third half photoresist region 823 is exposed outside the ashed photoresist layer 8. Since the first half photoresist region 821 and the second half photoresist region 822 correspond to both sides of the second semiconductor portion 42 of the semiconductor layer 4, respectively, and the third half photoresist region 823 corresponds to at least one side of the third semiconductor portion 43a of the semiconductor layer 4 adjacent to the second semiconductor portion 42, the region of the barrier layer 5 corresponding to both sides of the second semiconductor portion 42 is exposed outside the ashed photoresist layer 8, and the region of the barrier layer 5 corresponding to at least one side of the third semiconductor portion 43a adjacent to the second semiconductor portion 42 is exposed outside the ashed photoresist layer 8.

And S420, etching the barrier layer 5 by taking the pattern of the ashed photoresist layer 8 as a protection, and removing the photoresist layer 8 after the etching is finished so as to form the patterned barrier layer 5.

Fig. 10 is a schematic structural diagram of a barrier layer pattern formed by etching according to an embodiment of the invention. Referring to fig. 3 and 10, the ashed photoresist layer 8 pattern is used as a mask to etch the barrier layer 5, and since the regions of the barrier layer 5 corresponding to the two sides of the second semiconductor portion 42 of the semiconductor layer 4 are exposed outside the ashed photoresist layer 8 and at least the side of the barrier layer 5 corresponding to the third semiconductor portion 43a adjacent to the second semiconductor portion 42 is exposed outside the ashed photoresist layer 8, the regions of the barrier layer 5 can be removed during etching of the barrier layer 5, and further the regions of the semiconductor layer 4 corresponding to the regions of the barrier layer 5 can be exposed outside the barrier layer 5, that is, the two sides of the second semiconductor portion 42 are exposed outside the barrier layer 5 and at least the side of the third semiconductor portion 43a adjacent to the second semiconductor portion 42 is exposed outside the barrier layer 5.

After the source electrode 62 and the drain electrode 63 are formed in this way, the source electrode 62 and the drain electrode 63 are respectively positioned in the first space 44 and the second space 45 of the semiconductor layer 4, and the source electrode 62 and the drain electrode 63 are respectively in contact with both sides of the second semiconductor section 42, so that the source electrode 62, the drain electrode 63 and the second semiconductor section 42 are connected to form a thin film transistor, and the drain electrode 63 can be in contact with the third semiconductor section 43a, and the third semiconductor section 43a is electrically conducted to the pixel electrode 43b, so that the drain electrode 63 is directly connected to the pixel electrode 43b, and further, the thin film transistor can be communicated with the pixel electrode 43 b.

After etching the barrier layer 5 and patterning the barrier layer 5, the photoresist layer 8 is removed to expose the entire barrier layer 5 to be conductive to the third semiconductor portion 43a, and the source electrode 62 and the drain electrode 63 are formed on the barrier layer 5.

S500, the second semiconductor portion 42 exposed outside the barrier layer 5 is made conductive on both sides, contacts connected to the source electrode 62 and the drain electrode 63 are formed on both sides of the second semiconductor portion 42, and the third semiconductor portion 43a is made conductive to form the pixel electrode 43 b.

FIG. 11 is a schematic structural diagram of a third semiconductor portion with a photoresist layer removed and a conductor formed according to an embodiment of the present invention; fig. 12 is a top view of fig. 11. Referring to fig. 1, 11 and 12, after the barrier layer 5 is patterned by etching, both sides of the second semiconductor portion 42 of the semiconductor layer 4 are exposed outside the barrier layer 5, and at least one side of the third semiconductor portion 43a of the semiconductor layer 4 adjacent to the second semiconductor portion 42 is exposed outside the barrier layer 5, and after the photoresist layer 8 is removed, the third semiconductor portion 43a of the semiconductor layer 4 is subjected to a conductor treatment to form a pixel electrode 43b on the third semiconductor portion 43a, so that the source electrode 62 and the drain electrode 63 are formed, and then the drain electrode 63 is directly in contact with the pixel electrode 43b, thereby communicating the thin film transistor and the pixel electrode.

In this embodiment, the semiconductor layer 4 is patterned into the first semiconductor portion 41, the second semiconductor portion 42, and the third semiconductor portion 43a, and the first and

second spacers

44, 45 are provided between the second semiconductor portion 42 and the first and

third semiconductor portions

41, 43a, respectively, so that the source electrode 62 and the drain electrode 63 can be formed in the first and

second spacers

44, 45, respectively, so that the positions of the source electrode 62 and the drain electrode 63 can be better defined, and the barrier layer 5 is provided on the semiconductor layer 4, so that the barrier layer 5 can protect the semiconductor layer 4 in the process of forming the source electrode 62 and the drain electrode 63, so that the performance of the semiconductor layer 4, the source electrode 62, and the drain electrode 63 can be improved, and the performance of the thin film transistor can be improved.

In addition, since the third semiconductor portion 43a is directly conducted to the pixel electrode 43b and the drain electrode 63 is directly in contact with the pixel electrode 43b, a pixel function can be realized, and thus, a transparent conductive film is not additionally arranged on the surface of the array substrate 1 as a pixel electrode, which can reduce the number of manufacturing processes of the array substrate 1; moreover, the thickness of the array substrate 1 can be reduced due to the reduction of the transparent conductive film; in addition, since the third semiconductor section 43a is directly used as the pixel electrode 43b, the utilization rate of the semiconductor layer 4 is improved; this can improve the production efficiency of the array substrate 1 and reduce the production cost of the array substrate 1.

In one embodiment, the third half photoresist region 823 may completely cover the third semiconductor portion 43a, and the third semiconductor portion 43a is conducted to form the pixel electrode 43b, and may specifically include:

after the resist layer 8 is ashed and the barrier layer 5 is etched to form the patterned barrier layer 5, the third semiconductor portion 43a is exposed to the whole, and the exposed semiconductor layer 4 is subjected to plasma treatment to convert the third semiconductor portion 43a into a conductor to form the pixel electrode 43 b.

As shown in fig. 7 to 11, in the present embodiment, the third half photoresist region 823 extends from the side adjacent to the second non-photoresist region 812 up to the edge of the photoresist layer 8, and after the semiconductor layer 4 is patterned, the third half photoresist region 823 covers the entire third semiconductor portion 43a, so that after the ashing process is performed on the photoresist layer 8, the third half photoresist region 823 is removed, and further the region of the barrier layer 5 corresponding to the third semiconductor portion 43a is exposed outside the ashed photoresist layer 8, and after the etching process is further performed on the barrier layer 5 using the pattern of the ashed photoresist layer 8 as a mask, the region of the barrier layer 5 corresponding to the third semiconductor portion 43a is completely removed, and further the entire third semiconductor portion 43a of the conductor layer is exposed outside the barrier layer 5.

Since the third semiconductor portion 43a is completely exposed from the barrier layer 5, it is possible to perform plasma treatment on the semiconductor layer 4, and the plasma treatment can be applied to the entire third semiconductor portion 43a, so that the third semiconductor portion 43a can be made conductive, whereby the third semiconductor portion 43a can form the pixel electrode 43b, and the conductive third semiconductor portion 43a can be brought into direct contact with the drain electrode 63 as the pixel electrode 43b, thereby making it possible to communicate the thin film transistor with the pixel electrode.

As shown in fig. 9 to 11, after the photoresist layer 8 is ashed and the barrier layer 5 is etched to form the barrier layer 5 pattern, since both sides of the second semiconductor portion 42 of the semiconductor layer 4 are also exposed outside the barrier layer 5, both sides of the second semiconductor portion 42 are also made into a conductor when the semiconductor layer 4 is subjected to plasma processing, and thus two contacts contacting the source electrode 62 and the drain electrode 63 can be formed on both sides of the second semiconductor portion 42, which is not described herein again.

And S600, forming a source electrode 62 and a drain electrode 63 at the first and

second spacers

44 and 45, respectively, by a photolithography process, wherein opposite sides of the source and drain

electrodes

62 and 63 are in contact with the second semiconductor portion 42, and the other side of the drain electrode 63 is in contact with the pixel electrode 43 b.

Fig. 13 is a schematic structural diagram of forming a source and a drain according to a first embodiment of the invention. Referring to fig. 1 and 13, after the third semiconductor portion 43a is formed into a conductive pixel electrode 43b, a source electrode 62 and a drain electrode 63 are formed on the barrier layer 5 by a third photolithography process, wherein the source electrode 62 and the drain electrode 63 are respectively formed in the first space 44 and the second space 45 of the semiconductor layer 4, and the source electrode 62 and the drain electrode 63 are both in contact with the second semiconductor portion 42, so that a thin film transistor structure can be formed between the source electrode 62, the drain electrode 63 and the second semiconductor portion 42, and the drain electrode 63 is in contact with the other conductive third semiconductor portion 43a, i.e., the drain electrode 63 is in contact with the pixel electrode 43b, so that the thin film transistor and the pixel electrode structure can be connected.

Specifically, the specific steps of forming the source electrode 62 and the drain electrode 63 are:

firstly, depositing a source-drain electrode 63 metal layer on a barrier layer 5, then coating a photoresist layer 8 on the source-drain electrode 63 metal layer, and performing a third photolithography process by using a mask 9 to form a source electrode 62 and a drain electrode 63, wherein an opaque region 92 on the mask 9 corresponds to a region (positive photoresist) on the photoresist layer 8 corresponding to the source electrode 62 and the drain electrode 63, or a transparent region 91 on the mask 9 corresponds to a region (negative photoresist) on the photoresist layer 8 corresponding to the source electrode 62 and the drain electrode 63;

after the photoresist layer 8 is exposed, the photoresist in the exposed area (positive photoresist) or the photoresist in the unexposed area (negative photoresist) is removed by dissolving through a developing technology;

exposing the other areas except the source electrode 62 and the drain electrode 63 on the drain-source electrode metal layer, carrying out etching treatment on the drain-source electrode metal layer by using the patterned photoresist layer 8 as a mask, and removing the areas which are not covered by the photoresist layer 8, thus forming the drain electrode 63 and the source electrode 62.

In one possible implementation, after forming the source electrode 62 and the drain electrode 63, the following steps may be further included:

and S700, forming a flat layer 7 on the barrier layer 5, so that the flat layer 7 covers the array substrate.

FIG. 14 is a schematic diagram illustrating a structure of forming a planarization layer on a barrier layer according to an embodiment of the present invention; fig. 15 is a top view of fig. 14. Referring to fig. 1, fig. 14 and fig. 15, fig. 14 is a cross-sectional view taken along a line a-a in fig. 15, and by forming the planarization layer 7 on the barrier layer 5, the planarization layer 7 can protect the barrier layer 5 and the source electrode 62, the drain electrode 63 and the third semiconductor portion 43a exposed outside the barrier layer 5, thereby ensuring stable operation of the thin film transistor; also, the planarization layer 7 generally has a planarized surface, and thus the planarization layer 7 may improve the planarization of the array substrate 1.

In particular, the thickness can be deposited by a plasma enhanced chemical vapor deposition process to a thickness of about

The material of the planar layer 7 may be selected from oxide, nitride or oxynitride, and the corresponding reaction gas may be SiH₄，NH₃And N₂Or SiH₂Cl₂、NH₃And N₂。

According to the manufacturing method of the array substrate, the pixel structure of the array substrate can be formed only through three times of photoetching processes, compared with the prior art, the times of photoetching processes are effectively reduced, the process steps of the array substrate are simplified, the production efficiency of the array substrate can be improved, and the production cost of the array substrate is reduced; moreover, the semiconductor layer is formed into the first semiconductor part, the second semiconductor part and the third semiconductor part with the first interval and the second interval through the halftone mask process, so that the source electrode and the drain electrode can be formed in the first interval and the second interval, the positioning accuracy of the source electrode and the drain electrode is improved, the connection of the source electrode and the drain electrode with the second semiconductor part is more stable, and the performance and the stability of the thin film transistor can be improved; in addition, the barrier layer is arranged on the semiconductor layer, so that the barrier layer can protect the semiconductor layer, and the performance of the thin film transistor can be further improved; finally, the third semiconductor part of the semiconductor layer is directly conducted to form the pixel electrode, the thin film transistor is communicated with the pixel electrode through the third semiconductor part which is conducted to form the conductor, and a transparent conductive film is not needed to be arranged additionally, so that the thickness of the array substrate can be reduced, the production cost of the array substrate is reduced, and the utilization rate of semiconductor layer materials is improved.

Example two

Fig. 16 is a schematic structural diagram of a gate formed on a surface of a substrate according to a second embodiment of the present invention; fig. 17 is a schematic structural view of a substrate and a gate overlying an insulating layer according to a second embodiment of the present invention; fig. 18 is a schematic structural view illustrating a semiconductor layer, a barrier layer and a photoresist layer sequentially formed on an insulating layer according to a second embodiment of the present invention; FIG. 19 is a schematic structural diagram illustrating a photoresist layer pattern formed according to a second embodiment of the present invention; fig. 20 is a schematic structural diagram of a semiconductor layer pattern formed by etching according to the second embodiment of the present invention;

FIG. 21 is a schematic structural view of a pattern of an ashed photoresist layer provided in accordance with a second embodiment of the present invention; fig. 22 is a schematic structural diagram of a barrier layer pattern formed by etching according to the second embodiment of the present invention; FIG. 23 is a schematic structural diagram of a second semiconductor portion with a photoresist layer removed and a third semiconductor portion conductively formed according to an embodiment of the present invention; fig. 24 is a schematic structural diagram of forming a source and a drain according to a second embodiment of the present invention; fig. 25 is a schematic structural diagram of forming a planarization layer on a barrier layer according to a second embodiment of the present invention.

Referring to fig. 1 to 3 and 16 to 25, the present embodiment provides a manufacturing method of an array substrate 1, wherein the manufacturing method has substantially the same step flow as the manufacturing method provided in the first embodiment. Specifically, the manufacturing method of the array substrate 1 includes the following steps:

s100, forming a grid 22 on the substrate 1;

s200, sequentially forming an insulating layer 3, a semiconductor layer 4 and a barrier layer 5 on the substrate 1 and the grid 22;

s300, patterning the semiconductor layer 4 through a photoetching process; wherein the semiconductor layer 4 is patterned into a first semiconductor portion 41, a second semiconductor portion 42, and a third semiconductor portion 43a, and a first gap 44 and a second gap 45 are respectively provided between the second semiconductor portion 42 and the first semiconductor portion 41 and between the second semiconductor portion 42 and the third semiconductor portion 43 a;

s400, etching the barrier layer 5 to pattern the barrier layer 5, so that both sides of the second semiconductor portion 42 and a side of the third semiconductor portion 43a adjacent to the second semiconductor portion 42 are exposed outside the etched barrier layer 5;

s500, forming conductors on both sides of the second semiconductor portion 42 exposed outside the barrier layer 5, forming contacts connected to the source electrode 62 and the drain electrode 63 on both sides of the second semiconductor portion 42, and forming a pixel electrode 43b on the third semiconductor portion 43 a;

s600, forming a source electrode 62 and a drain electrode 63 at the first and

second spacers

44 and 45, respectively, by a photolithography process, wherein opposite sides of the source electrode 62 and the drain electrode 63 are in contact with the second semiconductor portion 42, and the other side of the drain electrode 63 is in contact with the pixel electrode 43 b;

Wherein, S300 specifically comprises the following steps:

s310, arranging a photoresist layer 8 on the barrier layer 5;

s320, exposing and developing the photoresist layer 8 by adopting a half-tone mask 9a to form a photoresist layer 8 pattern; the photoresist layer 8 pattern comprises a photoresist-free region 81, a half-photoresist region 82 and a full-photoresist region 83; the non-photoresist region 81 includes a first non-photoresist region 811 and a second non-photoresist region 812, and the half-photoresist region 82 includes a first half-photoresist region 821, a second half-photoresist region 822, and a third half-photoresist region 823; the first non-photoresist region 811 and the second non-photoresist region 812 correspond to the first interval 44 and the second interval 45, respectively, the first half-photoresist region 821 and the second half-photoresist region 822 are adjacent to the first non-photoresist region 811 and the second non-photoresist region 812, respectively, are located between the first non-photoresist region and the second non-photoresist region 812, respectively, and correspond to two sides of the second semiconductor portion 42 exposed outside the barrier layer 5, the third half-photoresist region 823 is adjacent to and disposed on the other side of the second non-photoresist region 812, and the photoresist layer 8 is a full-photoresist region 83 except the non-photoresist region 81 and the half-photoresist region 82;

S400 specifically includes the following steps:

s410, after the semiconductor layer 4 is patterned, ashing the photoresist layer 8 to remove the half photoresist region 82 and thin the full photoresist region 83;

The detailed implementation and effects of the above steps are described in detail in the first embodiment, and are not described herein again.

Referring to fig. 19 to 25, in the present embodiment, unlike the first embodiment, in the photoresist layer 8 pattern formed in S320, the third half photoresist region 823 does not extend all the way from the side adjacent to the second non-photoresist region 812 to the edge of the photoresist layer 8, that is, the third half photoresist region 823 only covers a partial area of the third semiconductor portion 43 a. Therefore, S500 in this embodiment is different from the first embodiment.

Specifically, in this embodiment, the third half photoresist region 823 may partially cover the third semiconductor portion 43a, and may make the third semiconductor portion 43a into a conductor to form the pixel electrode 43b, which may specifically include:

after the resist layer 8 is ashed and the barrier layer 5 is etched to form the patterned barrier layer 5, the third semiconductor portion 43a is partially exposed on the side adjacent to the drain electrode 63, and laser annealing is performed from the substrate 1 in the direction of the semiconductor layer 4 to convert the third semiconductor portion 43a into a conductor to form the pixel electrode 43 b.

In this embodiment, after patterning the semiconductor layer 4, the third half photoresist region 823 only partially covers the third semiconductor portion 43a, so that after ashing the photoresist layer 8, the third half photoresist region 823 is removed, and further, the region of the barrier layer 5 corresponding to the third half photoresist region 823 is exposed outside the ashed photoresist layer 8, that is, the region of the barrier layer 5 corresponding to the third semiconductor portion 43a is partially exposed outside the ashed photoresist layer 8, and after further etching the barrier layer 5 using the ashed photoresist layer 8 pattern as a mask, the exposed region of the barrier layer 5 is removed, and further, the region of the third semiconductor portion 43a adjacent to the second semiconductor portion 42 is exposed outside the barrier layer 5.

Since only a partial region of the third semiconductor section 43a is exposed outside the barrier layer 5, the third semiconductor section 43a cannot be made into a conductor by performing the plasma treatment on the semiconductor layer 4 in the first embodiment, and therefore, in this embodiment, the third semiconductor section 43a is made into a conductor of the pixel electrode 43b by performing the laser annealing treatment from the substrate 1 side toward the semiconductor layer 4.

Here, it is understood that since the laser annealing process is performed on the entire region of the substrate 1, the laser light is received by the semiconductor layer 4 at any portion of the semiconductor layer 4 except for a portion of the semiconductor layer 4 which cannot reach the semiconductor layer 4 through the gate electrode 22, and therefore the region of the semiconductor layer 4 is made conductive except for a partial region of the semiconductor layer 4 corresponding to the gate electrode 22, and the entire region of the third semiconductor portion 43a is made conductive as the pixel electrode 43 b.

EXAMPLE III

The present embodiment provides an array substrate 1, the array substrate 1 may include a substrate 1, a gate electrode 22 disposed on the substrate 1, an insulating layer 3 covering the gate electrode 22 and the substrate 1, and a semiconductor layer 4 covering the insulating layer 3, the semiconductor layer 4 has a first space 44 and a second space 45, the first space 44 and the second space 45 divide the semiconductor layer 4 into a first semiconductor portion 41, a second semiconductor portion 42, and a third semiconductor portion 43a, and a source electrode 62 and a drain electrode 63 are disposed in the first space 44 and the second space 45, respectively; the third semiconductor portion 43a adjacent to the drain electrode 63 is made conductive to form a pixel electrode 43 b.

Specifically, the array substrate 1 provided in this embodiment is manufactured by the manufacturing method of the array substrate 1 in the first embodiment or the second embodiment, wherein the specific structure, function, and working principle of the array substrate 1 are described in detail by describing the manufacturing method of the array substrate 1 in the first embodiment and the second embodiment, and are not described herein again.

In which the semiconductor layer 4 is divided into the first semiconductor portion 41, the second semiconductor portion 42, and the third semiconductor portion 43a by providing the semiconductor layer 4 with the first and

second spacers

44 and 45, so that the source electrode 62 and the drain electrode 63 can be formed in the first and

second spacers

44 and 45, respectively, and the first and

second spacers

44 and 45 can define the positions of the source electrode 62 and the drain electrode 63, so that the positions of the source electrode 62 and the drain electrode 63 are highly precise, and the connection stability between the source electrode 62, the second semiconductor portion 42, and the drain electrode 63 is better, and thus the performance of the formed thin film transistor is better.

In addition, the third semiconductor portion 43a separated by itself can be made into a conductor, so that the third semiconductor portion 43a is made into a conductor to form the pixel electrode 43b, the drain electrode 63 directly contacts with the third semiconductor portion 43a made into a conductor, that is, the drain electrode 63 is directly connected with the pixel electrode 43b, so that the thin film transistor and the pixel electrode can be communicated without additionally arranging a transparent conductive film on the surface of the array substrate 1, so that the transparent conductive film layer is reduced, the production cost of the array substrate 1 can be reduced, the thickness of the array substrate 1 can be reduced, and the utilization rate of the semiconductor layer 4 is enhanced.

Exemplarily, the semiconductor layer 4 may be an Indium Gallium Zinc Oxide (IGZO) layer.

As shown in fig. 14 or 25, an upper portion of the source electrode 62 may be attached to the surface of the semiconductor layer 4, and a lower portion of the source electrode 62 may extend into the first space 44 and be attached to the insulating layer 3; both sides of the upper portion of the drain electrode 63 may be attached to the surfaces of the second semiconductor section 42 and the pixel electrode 43b, respectively, and the lower portion of the drain electrode 63 may extend into the second space 45 and be attached to the insulating layer 3.

By attaching the upper portion of the source electrode 62 to the surface of the semiconductor layer 4 and the lower portion of the source electrode 62 extending into the first spacer 44 to be attached to the insulating layer 3, the source electrode 62 can be brought into contact with the second semiconductor portion 42, and the stability of the source electrode 62 can be improved; by respectively bonding the two sides of the upper portion of the drain electrode 63 to the second semiconductor portion 42 and the pixel electrode 43b, and by bonding the lower portion of the drain electrode 63 to the insulating layer 3 while extending into the second space 45, the source electrode 62, the drain electrode 63, and the second semiconductor portion 42 can form a thin film transistor, and the pixel electrode 43b can communicate the thin film transistor and the pixel electrode, and the stability of the drain electrode 63 can be improved, thereby improving the performance of the thin film transistor.

As shown in fig. 14, the array substrate 1 may further include a barrier layer 5 disposed on the semiconductor layer 4, the barrier layer 5 may include a first barrier portion 51 on the first semiconductor portion 41 and a second barrier portion 52 on the second semiconductor portion 42, a third space 54 is provided between the first barrier portion 51 and the second barrier portion 52, the third space 54 corresponds to the first space 44, and both sides of the second semiconductor portion 42 are exposed outside the second barrier portion 52.

By arranging the barrier layer 5 on the semiconductor layer 4, the barrier layer 5 has a protective effect on the semiconductor layer 4, and in the process of etching the source electrode 62 and the drain electrode 63, the barrier layer 5 can protect the semiconductor layer 4 below the barrier layer from being affected, so that the performance of the semiconductor layer 4 can be improved, and the performance of the thin film transistor can be further improved. The barrier layer 5 may at least include a first barrier portion 51 and a second barrier portion 52, the first barrier portion 51 and the second barrier portion 52 are respectively located above the first semiconductor portion 41 and the second semiconductor portion 42, and a third space 54 is provided between the first barrier portion 51 and the second barrier portion 52, which is not described herein again.

In addition, both sides of the second semiconductor section 42 are exposed outside the second barrier section 52, so that the source and drain

electrodes

62 and 63 can be in contact with both sides of the second semiconductor section 42, and thus a thin film transistor structure can be formed between the source and drain

electrodes

62, 42 and 63.

As shown in fig. 25, in another possible embodiment, the blocking layer 5 may further include a third blocking portion 53 on the pixel electrode 43b, a fourth interval 55 is formed between the second blocking portion 52 and the third blocking portion 53, the fourth interval 55 corresponds to the second interval 45, and a side of the pixel electrode 43b adjacent to the drain electrode 63 is exposed outside the third blocking portion 53.

The barrier layer 5 further includes a third barrier portion 53, the third barrier portion 53 is correspondingly located on the third semiconductor portion 43a, since the third semiconductor portion 43a is formed into a pixel electrode 43b by a conductor, that is, the third barrier portion 53 is located on the pixel electrode 43b, a fourth gap 55 is formed between the third barrier portion 53 and the second barrier portion 52, the fourth gap 55 corresponds to the second gap 45, and the width of the fourth gap 55 is greater than the width of the second gap 45, so that the edge of the pixel electrode 43b is exposed outside the third barrier portion 53, and thus the drain electrode 63 can contact the pixel electrode 43b, and the pixel electrode 43b can communicate the thin film transistor with the pixel electrode.

Alternatively, the upper portion of the source electrode 62 may be located in the third space 54, and both side edges of the upper portion of the source electrode 62 are in contact with the first barrier 51 and the second barrier 52, respectively; the upper portion of the drain electrode 63 is positioned in the fourth space 55, and both side edges of the upper portion of the drain electrode 63 are in contact with the second barrier 52 and the third barrier 53, respectively.

As described in the first and second embodiments, when forming the source electrode 62 and the drain electrode 63, a metal layer of a source drain electrode 63 may be deposited on the barrier layer 5, and then the source electrode 62 and the drain electrode 63 may be formed by a photolithography process, so that upper portions of the source electrode 62 and the drain electrode 63 protrude above the barrier layer 5, and both side edges of the upper portion of the source electrode 62 may respectively contact the first barrier portion 51 and the second barrier portion 52, and both side edges of the upper portion of the drain electrode 63 may respectively contact the second barrier portion 52 and the third barrier portion 53, wherein, in a case where the third barrier portion 53 is not included, one side of the upper portion of the drain electrode 63 contacts the second barrier portion 52, which will not be described herein again.

As shown in fig. 14 or 25, optionally, the array substrate 1 may further include a planarization layer 7 disposed on the barrier layer 5, and the planarization layer 7 covers the array substrate. The flat layer 7 is further arranged on the barrier layer 5, the flat layer 7 covers the barrier layer 5 and the source electrode 62 and the drain electrode 63, the flat layer 7 can protect the barrier layer 5 and the source electrode 62, the drain electrode 63 and the pixel electrode 43b exposed outside the barrier layer 5, and stable operation of the thin film transistor can be guaranteed; also, the planarization layer 7 generally has a planarized surface, and thus the planarization layer 7 may improve the planarization of the array substrate 1.

The array substrate provided by the embodiment comprises a substrate, wherein a grid electrode is arranged on the substrate, an insulating layer and a semiconductor layer are sequentially covered on the substrate and the grid electrode, the semiconductor layer is divided into a first semiconductor part, a second semiconductor part and a third semiconductor part by enabling the semiconductor layer to have a first interval and a second interval, a source electrode and a drain electrode are respectively arranged in the first interval and the second interval, and a thin film transistor structure is formed by the source electrode, the drain electrode and the second semiconductor part between the source electrode and the drain electrode so as to control the pixel electrode to work; the first interval and the second interval are arranged on the semiconductor layer, so that the source electrode and the drain electrode are respectively positioned in the first interval and the second interval, the positions of the source electrode and the drain electrode can be better positioned, and the performance of a thin film transistor structure formed among the source electrode, the drain electrode and the second semiconductor part can be improved; and the second interval separates the third semiconductor part from the semiconductor layer, and the third semiconductor part is conducted to form a conductor to form a pixel electrode, so that the pixel electrode can be positioned in the semiconductor layer and directly connected with the drain electrode, and a transparent conductive film does not need to be arranged on the array substrate, thereby not only improving the utilization rate of the semiconductor layer, but also reducing the manufacturing cost of the array substrate, and simultaneously reducing the thickness of the array substrate.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An array substrate, comprising a substrate, a gate electrode disposed on the substrate, an insulating layer covering the gate electrode and the substrate, and a semiconductor layer covering the insulating layer, wherein the semiconductor layer has a first interval and a second interval, the first interval and the second interval divide the semiconductor layer into a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion, and a source electrode and a drain electrode are disposed in the first interval and the second interval, respectively; wherein the third semiconductor portion adjacent to one side of the drain electrode is formed into a pixel electrode by conductor formation;

the semiconductor device further comprises a barrier layer arranged on the semiconductor layer, wherein the barrier layer comprises a first barrier part positioned on the first semiconductor part and a second barrier part positioned on the second semiconductor part, a third interval is arranged between the first barrier part and the second barrier part, the third interval corresponds to the first interval, and two sides of the second semiconductor part are exposed outside the second barrier part.

2. The array substrate of claim 1, wherein the blocking layer further comprises a third blocking portion on the pixel electrode, the second blocking portion and the third blocking portion have a fourth space therebetween, the fourth space corresponds to the second space, and a side of the pixel electrode adjacent to the drain electrode is exposed outside the third blocking portion.

3. The array substrate of claim 2, wherein an upper portion of the source electrode is located in the third space, and two side edges of the upper portion of the source electrode are respectively in contact with the first barrier portion and the second barrier portion; the upper part of the drain electrode is positioned in the fourth interval, and two side edges of the upper part of the drain electrode are respectively contacted with the second blocking part and the third blocking part.

4. The array substrate of claim 3, further comprising a planarization layer disposed on the barrier layer, the planarization layer covering the array substrate.

5. The manufacturing method of the array substrate is characterized by comprising the following steps:

forming a gate electrode on a substrate;

patterning the semiconductor layer by a photolithography process; wherein the semiconductor layer is patterned into a first semiconductor section, a second semiconductor section, and a third semiconductor section, the second semiconductor section and the first and third semiconductor sections having a first and second spacing therebetween, respectively;

conducting both sides of the second semiconductor portion exposed outside the barrier layer to form contacts connected to the source and drain electrodes on both sides of the second semiconductor portion, and conducting the third semiconductor portion to form a pixel electrode;

and respectively forming a source electrode and a drain electrode at the first interval and the second interval by a photoetching process, wherein one sides of the source electrode and the drain electrode, which are opposite to each other, are in contact with the second semiconductor part, and the other side of the drain electrode is in contact with the pixel electrode.

6. The method according to claim 5, wherein the patterning the semiconductor layer by a photolithography process comprises:

a photoresist layer is arranged on the barrier layer;

exposing and developing the photoresist layer by adopting a half-tone mask plate to form a photoresist layer pattern; the photoresist layer pattern comprises a non-photoresist area, a semi-photoresist area and a full-photoresist area; the non-photoresist area comprises a first non-photoresist area and a second non-photoresist area, and the semi-photoresist area comprises a first semi-photoresist area, a second semi-photoresist area and a third semi-photoresist area; wherein the first and second non-photoresist regions correspond to the first and second intervals, respectively, the first and second half-photoresist regions are adjacent to and between the first and second non-photoresist regions, respectively, and correspond to two sides of the second semiconductor portion exposed outside the barrier layer, the third half-photoresist region is adjacent to and disposed on the other side of the second non-photoresist region, and the photoresist layer is the all-photoresist region except the non-photoresist region and the half-photoresist region;

and etching the barrier layer and the semiconductor layer by using the photoresist layer pattern as a protection so that the semiconductor layer forms the first semiconductor part, the second semiconductor part and the third semiconductor part.

7. The method according to claim 6, wherein the etching the barrier layer to pattern the barrier layer specifically comprises:

and etching the barrier layer by taking the ashed photoresist layer pattern as protection, and removing the photoresist layer after etching is finished so as to form the patterned barrier layer.

8. The method according to claim 7, wherein the third half photoresist region completely covers the third semiconductor portion, and the conducting the third semiconductor portion to form a pixel electrode comprises:

and ashing the photoresist layer pattern and etching the barrier layer to form the patterned barrier layer, wherein the third semiconductor part is completely exposed, and plasma treatment is carried out on the exposed semiconductor layer so that the third semiconductor part is conducted to form a pixel electrode.

9. The method according to claim 7, wherein the third half photoresist region partially covers the third semiconductor portion, and the conducting of the third semiconductor portion to form a pixel electrode comprises:

and ashing the photoresist layer pattern and etching the barrier layer to form a patterned barrier layer, wherein one side of the third semiconductor part adjacent to the drain electrode is partially exposed, and laser annealing treatment is carried out from the substrate to the direction of the semiconductor layer, so that the third semiconductor part is conducted to form a pixel electrode.

10. The method of manufacturing according to any one of claims 5 to 9, further comprising, after forming the source electrode and the drain electrode: and forming a flat layer on the barrier layer so that the flat layer covers the array substrate.