CN112038288B - Manufacturing method of array substrate and array substrate - Google Patents
Manufacturing method of array substrate and array substrate Download PDFInfo
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- CN112038288B CN112038288B CN202011213605.0A CN202011213605A CN112038288B CN 112038288 B CN112038288 B CN 112038288B CN 202011213605 A CN202011213605 A CN 202011213605A CN 112038288 B CN112038288 B CN 112038288B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Abstract
The invention provides a manufacturing method of an array substrate and the array substrate. The manufacturing method of the array substrate provided by the invention comprises the steps of forming a grid electrode on the substrate; forming a gate insulating layer and a semiconductor layer on the substrate and the gate electrode; patterning the semiconductor layer to form a first semiconductor portion and a second semiconductor portion, the first semiconductor portion having a first photoresist portion thereon, the second semiconductor portion having a second photoresist portion thereon; forming a pixel electrode by converting the first semiconductor portion into a conductor and converting the second semiconductor portion into a conductor; and forming a barrier layer, a drain electrode and a source electrode, wherein the barrier layer, the source electrode and the drain electrode are mutually disconnected, the barrier layer is positioned above the semiconductor layer, and the first photoresist part is positioned between the barrier layer and the first semiconductor part. According to the manufacturing method of the array substrate, the source drain metal layer and the barrier layer are formed by the same material in the same layer, the manufacturing process of the barrier layer is simplified, and the manufacturing cost is reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to a manufacturing method of an array substrate and the array substrate.
Background
A Thin Film Transistor (TFT) having a channel formed by a Metal Oxide Semiconductor (MOS) is widely used as a switching element in the display field. The thin film transistor is turned on when a certain amount of voltage (threshold voltage) is applied to the gate electrode, and is turned off when the voltage applied to the gate electrode is less than the threshold voltage. After a Metal-Oxide channel layer (Metal-Oxide channel layer) is backlit, irradiated by natural light or irradiated by a subsequent exposure process in a production process, threshold voltage deviation can be generated, and the instability of the thin film transistor is caused.
In the conventional metal oxide thin film transistor, a light shielding layer (also called as a blocking layer) is laid on an active layer, and the deviation of threshold voltage is avoided and the stability of the thin film transistor is ensured through the light shielding effect of the light shielding layer.
However, the light shielding layer is laid separately, which is complicated in process and high in manufacturing cost.
Disclosure of Invention
The invention provides a manufacturing method of an array substrate and the array substrate.
In a first aspect, the present invention provides a method for manufacturing an array substrate and an array substrate, including the following steps:
forming a gate electrode on a substrate;
sequentially forming a gate insulating layer and a semiconductor layer on the substrate and the gate electrode;
patterning the semiconductor layer through a half-tone lithography process to form a first semiconductor part and a second semiconductor part which are separated by a first interval, wherein a second interval is arranged on one side, away from the first interval, of the first semiconductor part, the first semiconductor part is provided with a first photoresist part, and the second semiconductor part is provided with a second photoresist part;
ashing the first photoresist portion and the second photoresist portion to expose both sides of the first semiconductor portion and the second semiconductor portion, making the exposed first semiconductor portion conductive so that contacts for connecting to a source electrode and a drain electrode are formed on both sides of the first semiconductor portion, respectively, and making the exposed second semiconductor portion conductive so that a pixel electrode is formed;
and respectively forming a barrier layer, a drain electrode and a source electrode at the first photoresist part, the first interval and part of the second interval by a photoetching process, wherein the barrier layer, the source electrode and the drain electrode are mutually disconnected, the source electrode and the drain electrode are respectively contacted with two opposite sides of the first semiconductor part, the drain electrode is also contacted with the pixel electrode, the barrier layer is positioned above the semiconductor layer, and the first photoresist part is positioned between the barrier layer and the first semiconductor part.
Optionally, in the manufacturing method of the array substrate provided by the present invention, the forming the barrier layer, the drain electrode, and the source electrode on the first photoresist portion, the first space, and the portion of the second space by the photolithography process respectively includes:
depositing a metal layer on the first photoresist portion, the first space, the second space and the pixel electrode;
coating photoresist on the metal layer, exposing and developing by adopting a mask to form photoresist corresponding to the patterns of the barrier layer, the source electrode and the drain electrode, then etching to form the barrier layer, the source electrode and the drain electrode, and then washing away the photoresist; a first gap is formed between the source electrode adjacent to the first side of the blocking layer and the first side of the blocking layer, and a second gap is formed between the drain electrode adjacent to the second side of the blocking layer and the second side of the blocking layer.
Optionally, the manufacturing method of the array substrate provided by the invention,
the first gap corresponds to the first side edge of the ashed first photoresist portion,
the second gap corresponds to a second side edge of the ashed first photoresist portion.
Optionally, the manufacturing method of the array substrate provided by the invention,
forming a barrier layer, a drain electrode and a source electrode on the first photoresist portion, the first space and a portion of the second space by a photolithography process, respectively, includes:
depositing a metal layer on the first photoresist portion, the first space, the second space and the pixel electrode;
and coating photoresist on the metal layer, carrying out exposure and development by adopting a half-tone mask to form photoresist corresponding to the patterns of the barrier layer, the source electrode and the drain electrode, then carrying out dry etching to form the barrier layer, the source electrode and the drain electrode, and then washing off the photoresist.
Optionally, the method for manufacturing an array substrate, provided by the present invention, patterning the semiconductor layer by a photolithography process to form the first semiconductor portion and the second semiconductor portion separated by the first space includes:
coating photoresist on the semiconductor layer;
exposing and developing the photoresist through a half-tone mask plate to form a photoresist layer pattern; the photoresist layer pattern comprises a non-photoresist area, a semi-photoresist area and a full-photoresist area, wherein the full-photoresist area corresponds to the active layer area, and the semi-photoresist area comprises a first semi-photoresist area, a second semi-photoresist area and a third semi-photoresist area; the first half photoresist area and the second half photoresist area are respectively positioned at two sides of the full photoresist area and respectively correspond to a contact of the source electrode and a contact of the drain electrode, and the third half photoresist area corresponds to the pattern of the pixel electrode;
the first half photoresist area, the second half photoresist area and the full photoresist area form a first photoresist part, and the third half photoresist area forms a second photoresist part;
and etching the semiconductor layer by taking the photoresist layer pattern as protection so as to form a first semiconductor part and a second semiconductor part on the semiconductor layer.
Optionally, in the manufacturing method of the array substrate provided by the present invention, the ashing the first photoresist portion includes:
and ashing the photoresist layer pattern to thin the full photoresist region and remove the first and second half photoresist regions, thereby exposing both sides of the first semiconductor portion.
Optionally, the method for manufacturing an array substrate according to the present invention, the forming contacts for connecting to the source and the drain on two sides of the first semiconductor portion by conducting the exposed first semiconductor portion includes:
and carrying out plasma treatment on the exposed first semiconductor part, so that contacts for connecting with the source electrode and the drain electrode are respectively formed on two sides of the first semiconductor part.
Optionally, in the manufacturing method of the array substrate provided by the present invention, the ashing the second photoresist portion includes:
the photoresist layer pattern is ashed to remove the half photoresist region, thereby exposing the second semiconductor portion.
Optionally, the method for manufacturing an array substrate according to the present invention, conducting the exposed second semiconductor portion to form a pixel electrode includes:
and carrying out plasma treatment on the exposed second semiconductor part to form a pixel electrode.
In a second aspect, the present invention also provides an array substrate, including a substrate, a gate electrode disposed on the substrate, a source electrode, a drain electrode, a first semiconductor portion and a pixel electrode layer, which are disposed so as to cover the substrate and the gate electrode;
the first semiconductor part is sequentially provided with a first photoresist part and a barrier layer; the barrier layer, the source electrode and the drain electrode are arranged on the same layer and are made of the same material, the barrier layer, the source electrode and the drain electrode are mutually disconnected, a first gap is formed between the source electrode adjacent to the first side of the barrier layer and the first side of the barrier layer, a second gap is formed between the drain electrode adjacent to the second side of the barrier layer and the second side of the barrier layer, the first gap corresponds to the first side edge of the ashed first photoresist portion, the second gap corresponds to the second side edge of the ashed first photoresist portion, the source electrode and the drain electrode are respectively contacted with two opposite sides of the first semiconductor portion, and the drain electrode is also contacted with the pixel electrode.
According to the manufacturing method of the array substrate and the array substrate, the blocking layer is supported by the first photoresist portion to form a state of being disconnected from the source electrode and the drain electrode and suspending, the first semiconductor portion is shielded by the source electrode, the drain electrode and the blocking layer, backlight or natural light is prevented from irradiating a thin film transistor channel layer, and stability of a thin film transistor is improved. Meanwhile, the source electrode, the drain electrode and the barrier layer are formed by the same material in the same layer, so that the manufacturing process of the barrier layer is simplified, and the manufacturing cost of the thin film transistor is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without inventive labor.
Fig. 1 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 2a and fig. 2b are schematic structural diagrams of a first manufacturing stage in a manufacturing method of an array substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a second preparation stage in the manufacturing method of the array substrate according to the first embodiment of the present application;
fig. 4a and 4b are schematic structural diagrams of a third manufacturing stage in a manufacturing method of an array substrate according to an embodiment of the present application;
fig. 5a and 5b are schematic structural diagrams of a fourth preparation stage in a manufacturing method of an array substrate according to an embodiment of the present application;
fig. 6a and 6b are schematic structural diagrams of a fifth preparation stage in a manufacturing method of an array substrate according to an embodiment of the present application;
FIG. 7 is an enlarged view of a portion of FIG. 6b at A;
FIG. 8 is an enlarged view of a portion of FIG. 6B at B;
fig. 9 is a schematic structural diagram of an array substrate manufactured by the manufacturing method of the array substrate according to the first embodiment of the present application;
FIG. 10 is a cross-sectional view taken along line C-C of FIG. 9;
fig. 11 is a partial enlarged view of fig. 9 at D.
Description of reference numerals:
100-a substrate; 200-a gate; 200 a-gate metal layer; 200 b-a third photoresist layer; 200 c-mask plate; 210 c-a light transmissive region; 220 c-opaque region; 300-a gate insulating layer; 400-a semiconductor layer; 400 a-a second photoresist layer; 410 a-a first photoresist portion; 420 a-a second photoresist portion; 400 b-a second reticle; 410-a first semiconductor portion; 420-a second semiconductor portion; 430-a first interval; 440-a second interval; 450-contacts; 461-first photoresist-free region; 462-second non-photoresistA zone; 471-first half photoresist area; 472-second half-photoresist region; 473-third half-photoresist region; 480-all photoresist region; 500-a drain electrode; 600-a source electrode; 700-pixel electrode; 800-a metal layer; 810-a first reticle; 820-a first photoresist layer; 900-a barrier layer; 1000-a planar layer; 1100-scan line; 1200-a data line; h1-a first gap; h2-a second gap.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," and "third" (if any) in this specification and in the claims and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein.
The thin film transistor is turned on when a certain amount of voltage (threshold voltage) is applied to the gate electrode, and is turned off when the voltage applied to the gate electrode is less than the threshold voltage. After a Metal-Oxide channel layer (Metal-Oxide channel layer) is backlit, irradiated by natural light or irradiated by a subsequent exposure process in a production process, threshold voltage deviation can be generated, and the instability of the thin film transistor is caused. In the conventional metal oxide thin film transistor, a light shielding layer (also called as a blocking layer) is laid on an active layer, and the deviation of threshold voltage is avoided and the stability of the thin film transistor is ensured through the light shielding effect of the light shielding layer. However, the light shielding layer is laid separately, which is complicated in process and high in manufacturing cost.
Therefore, the embodiment of the application provides a manufacturing method of an array substrate and the array substrate, wherein the source drain metal layer and the shading layer are made of the same material and are laid on the same layer, the manufacturing process of the shading layer is simplified, and the manufacturing cost is reduced.
The present application will be described in detail below with reference to specific examples.
Example one
Fig. 1 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure; fig. 9 is a schematic structural diagram of an array substrate manufactured by the manufacturing method of the array substrate according to the first embodiment of the present application; FIG. 10 is a cross-sectional view taken along line C-C of FIG. 9; fig. 11 is a partial enlarged view of fig. 9 at D. Referring to fig. 1, the method for manufacturing an array substrate provided by the present application includes the following steps:
s101, a gate electrode 200 is formed on the substrate 100.
Fig. 2a and fig. 2b are schematic structural diagrams of a first preparation stage in a manufacturing method of an array substrate according to an embodiment of the present disclosure. Referring to fig. 2a, 2b, and 9 to 11, in step S101, the substrate 100 may be a transparent substrate, for example, the substrate 100 is a glass substrate. The gate metal layer 200a may be deposited on the substrate 100, and for example, the gate metal layer 200a may be deposited on the substrate 100 using a sputtering or thermal evaporation process. The gate metal layer 200a may be made of Cr, W, Cu, Ti, Ta, Mo, or other metal or alloy material. In this embodiment, the number of layers of the gate metal layer 200a is not limited, and one layer of the gate metal layer 200a may be provided on the substrate 100, or two or more layers of the gate metal layer 200a may be provided.
After the gate metal layer 200a is formed, the gate metal layer 200a is patterned into the gate electrode 200 through a first photolithography process. Referring to fig. 2a, a third photoresist layer 200b may be formed by first coating a photoresist on the gate metal layer 200 a. For example, by providing the transparent region 210c and the opaque region 220c on the reticle 200c, ultraviolet light is irradiated onto the surface of the third photoresist layer 200b through the reticle 200c to cause a chemical reaction of the photoresist in the exposed region of the third photoresist layer 200b, and the photoresist in the exposed region (positive photoresist) or the photoresist in the unexposed region (negative photoresist) is removed by dissolving through a developing technique.
Referring to fig. 2a, the third photoresist layer 200b of the present embodiment is a positive photoresist, and the area of the mask 200c corresponding to the gate 200 is an opaque area 220c, and the rest is a transparent area 210 c. The region of the third photoresist layer 200b irradiated by the ultraviolet light through the light-transmitting region 210c of the mask 200c is the exposed region of the third photoresist layer 200b, i.e., the exposed region is the other region except the gate 200, the photoresist in the exposed region is removed by a developing technique, the gate metal layer 200a opposite to the light-transmitting region 210c is exposed, and the third photoresist layer 200b and the gate metal layer 200a opposite to the light-blocking region 220c are left. At this time, the exposed gate metal layer 200a is etched, and the third photoresist layer 200b opposite to the opaque region 220c is removed, so that the gate 200 is formed on the substrate 100.
Of course, the third photoresist layer 200b may also adopt a negative photoresist, which has a similar principle to the positive photoresist and is not described herein again.
It can be understood that, the exposure and development process for irradiating the third photoresist layer 200b through the mask 200c by using ultraviolet light to transfer the mask pattern on the mask 200c to the third photoresist layer 200b to form a photoresist pattern, and the process for etching the region not covered by the third photoresist layer 200b after forming the photoresist pattern are the same as or similar to the above process flows, and the exposure, development and etching processes occurring after this embodiment are not described in detail again.
Referring to fig. 9 to 11, in addition, in practical applications, the array substrate further includes a plurality of sub-pixel regions separated by a plurality of scan lines 1100 and a plurality of data lines 1200, and each sub-pixel region has a thin film transistor device disposed therein. It can be understood that the array substrate in this embodiment includes a plurality of sub-pixel regions, and therefore, in the manufacturing process of the array substrate in this embodiment, the step of forming the gate 200 on the substrate 100 specifically means that the gate 200 is formed at a position corresponding to each sub-pixel region of the array substrate 100, and the conditions of patterning the semiconductor layer 400 and forming the source electrode 600 and the drain electrode 500 are the same or similar to each other, and are not repeated herein.
S102, a gate insulating layer 300 and a semiconductor layer 400 are sequentially formed on the substrate 100 and the gate electrode 200.
Fig. 3 is a schematic structural diagram of a second preparation stage in the manufacturing method of the array substrate according to the first embodiment of the present disclosure. Referring to fig. 3, 9 to 11, after forming the gate electrode 200 on the substrate 100, a gate insulating layer 300 is formed on the substrate 100 and the gate electrode 200 such that the gate insulating layer 300 covers the substrate 100 and the gate electrode 200. The gate insulating layer 300 is used to protect the gate 200, and insulate and isolate the gate 200 from the source 600, the drain 500, and the semiconductor layer 400 formed later, so as to ensure the performance of the gate 200, and in the subsequent etching process, the gate insulating layer 300 can also protect the gate 200 from being affected by etching.
In a specific implementation, the gate insulating layer 300 may be continuously deposited by a plasma enhanced chemical vapor deposition method, and the material of the gate insulating layer 300 may be a material known to those skilled in the art, and the thickness of the gate insulating layer 300 is selected according to actual needs, which is not limited herein.
Further, after the gate insulating layer 300 is deposited on the substrate 100 and the gate electrode 200, the semiconductor layer 400 is deposited on the gate insulating layer 300. The semiconductor layer 400 may be deposited by sputtering or thermal evaporation, and the material of the semiconductor layer 400 may be a metal oxide. In specific implementation, the semiconductor layer 400 may be an indium gallium zinc oxide IGZO semiconductor layer, and the IGZO semiconductor layer may reduce power consumption of the display screen, and has a lower cost, so as to better improve a response speed of the pixel, and simultaneously, a faster response speed also greatly improves a line scanning rate of the pixel, thereby improving a resolution of the display screen.
S103, patterning the semiconductor layer 400 by a half-tone lithography process to form a first semiconductor portion 410 and a second semiconductor portion 420 separated by a first space 430, where a side of the first semiconductor portion 410 away from the first space 430 has a second space 440, the first semiconductor portion 410 has a first photoresist portion 410a, and the second semiconductor portion 420 has a second photoresist portion 420 a.
Fig. 4a and 4b are schematic structural diagrams of a third manufacturing stage in a manufacturing method of an array substrate according to an embodiment of the present application. Referring to fig. 4a, 4b, and 9 to 11, specifically, after the semiconductor layer 400 is formed, a photoresist is coated on the semiconductor layer 400 to form a second photoresist layer 400a, the second photoresist layer 400a is configured for a photolithography process, so that the second photoresist layer 400a is exposed and developed through a second mask 400b to form a first photoresist portion 410a and a second photoresist portion 420a, and the semiconductor layer 400 is protected by the first photoresist portion 410a and the second photoresist portion 420a when the semiconductor layer 400 is patterned. The second mask 400b is a halftone mask.
The semiconductor layer 400 is patterned through a second photolithography process, thereby forming regions where the source and drain electrodes 600 and 500 are disposed on the semiconductor layer 400. The patterned semiconductor layer 400 includes a first semiconductor portion 410 and a second semiconductor portion 420, wherein a first photoresist portion 410a covers the first semiconductor portion 410, and a second photoresist portion 420a covers the second semiconductor portion 420. The first semiconductor portion 410 and the second semiconductor portion 420 are disconnected by a first space 430, and the first space 430 is located to dispose the drain electrode 500. The first semiconductor portion 410 has a second spacer 440 on a side facing away from the first spacer 430, and a portion of the second spacer 440 is used to dispose the source electrode 600.
S104, the first photoresist portion 410a and the second photoresist portion 420a are ashed to expose both sides of the first semiconductor portion 410 and the second semiconductor portion 420, the exposed first semiconductor portion 410 is made conductive, contacts 450 for connection with the source electrode 600 and the drain electrode 500 are formed on both sides of the first semiconductor portion 410, respectively, and the exposed second semiconductor portion 420 is made conductive to form the pixel electrode 700. Fig. 5a and 5b are schematic structural diagrams of the fourth preparation stage in the manufacturing method of the array substrate provided in the first embodiment of the present application, that is, schematic structural diagrams prepared after S103 in the manufacturing method of the array substrate provided in the first embodiment of the present application. Referring to fig. 5a, 5b, and 9 to 11, in detail, the upper surfaces of both sides of the first photoresist portion 410a are etched to expose a portion of the first semiconductor portion 410, that is, the upper surfaces of both sides of the first semiconductor portion 410 are exposed, the exposed surface and the side surface of the first semiconductor portion 410 are plasma-treated to be made conductive, and contacts 450 for connecting to the source electrode 600 and the drain electrode 500 are respectively formed on both sides of the first semiconductor portion 410. The first photoresist portion 410a on the first semiconductor portion 410 remains. The second photoresist portion 420a is removed by ashing, and the exposed second semiconductor portion 420 is made conductive to form the pixel electrode 700.
S105, forming a barrier layer 900, a drain 500 and a source 600 on the first photoresist portion 410a, the first space 430 and a portion of the second space 440, respectively, by a photolithography process, wherein the barrier layer 900, the source 600 and the drain 500 are disconnected from each other, the source 600 and the drain 500 are respectively in contact with two opposite sides of the first semiconductor portion 410, the drain 500 is also in contact with the pixel electrode 700, the barrier layer 900 is located above the first semiconductor portion 410, and the first photoresist portion 410a is located between the barrier layer 900 and the first semiconductor portion 410.
Fig. 6a and fig. 6b are schematic structural diagrams of a fifth preparation stage in the manufacturing method of the array substrate provided in the first embodiment of the present application, that is, a schematic structural diagram of a preparation stage S105 in the manufacturing method of the array substrate provided in the first embodiment of the present application; FIG. 7 is an enlarged view of a portion of FIG. 6b at A; fig. 8 is a partial enlarged view of fig. 6B at B. Referring to fig. 6a, 6b, 7 and 8, specifically, a metal layer 800 is deposited on the remaining first photoresist portion 410a, the first space 430, the second space 440 and the pixel electrode 700, a photoresist layer is coated on the metal layer 800 to form a first photoresist layer 820, exposure and development are performed using a first mask 810 to form a photoresist corresponding to the pattern of the source electrode 600, the drain electrode 500 and the barrier layer 900, etching is then performed to form the source electrode 600, the drain electrode 500 and the barrier layer 900, and the photoresist is washed away. At this time, the first photoresist portion 410a is remained between the barrier layer 900 and the first semiconductor portion 410, the barrier layer 900 is supported by the first photoresist portion 410a to form a state of being disconnected from and floating on the source electrode 600 and the drain electrode 500, the barrier layer 900 is not connected to other circuits, the first semiconductor portion 410 is shielded by the source electrode 600, the drain electrode 500 and the barrier layer 900, a backlight or natural light is prevented from irradiating the thin film transistor channel layer, and the stability of the thin film transistor is increased. Meanwhile, the source electrode 600, the drain electrode 500 and the barrier layer 900 are formed by the same material on the same layer, so that the manufacturing process of the barrier layer 900 is simplified, and the manufacturing cost of the thin film transistor is reduced.
Wherein a first gap H is formed between the source electrode 600 adjacent to the first side of the barrier layer 900 and the first side of the barrier layer 9001So as to expose a portion of the side of the first photoresist portion 410a, and disconnect the source 600 from the barrier layer 900. A second gap H is formed between the drain electrode 500 adjacent to the second side of the barrier layer 900 and the second side of the barrier layer 9002So as to expose a portion of the side of the first photoresist portion 410a, and disconnect the drain electrode 500 from the barrier layer 900.
In some embodiments, in the step S105, the forming the barrier layer 900, the source electrode 600, and the drain electrode 500 by performing a photolithography process using a reticle includes: the first mask 810 is used for development and the barrier layer 900, the source electrode 600 and the drain electrode 500 are formed through a dry etching process. Therefore, dry etching rather than wet etching using an etching liquid can prevent the etching liquid from passing through the first gap H1And a second gap H2Gaps between the photoresist portions 410a penetrate into the first semiconductor portion 410, and corrode the first semiconductor portion 410, thereby affecting characteristics of the thin film transistor.
Wherein the first gap H1A second gap H corresponding to the first side edge of the ashed first photoresist portion 410a2Corresponding to the second side edge of the ashed first photoresist portion 410 a. Since the etching is performed at the corner position of the first photoresist portion 410a, the etching is easier and smaller than the planar gap generated by planar etching, the success rate of etching efficiency is higher, the higher shielding rate can be improved, and the shielding effect on the active layer is better.
The metal layer 800 is raised by the first photoresist portion 410a, and there is a height difference at the edge of the first photoresist portion 410a, that is, the metal layer 800 at the edge of the first photoresist portion 410a, where the metal layer 800 is weak, has a sparse material and is easy to etch, and the etching can also be realized by dry etching. In addition, since the first photoresist portion 410a pads up the barrier layer 900, even if the barrier layer 900 is formed with the barrier layerFirst gap H of source 6001The barrier layer 900 and the source electrode 600 are not short-circuited even if the height difference exists between the barrier layer 900 and the source electrode 600, so that the barrier layer 900 and the source electrode 600 are directly and easily etched completely, and poor etching caused by incomplete disconnection between the barrier layer 900 and the source electrode 600 is avoided. Second gap H between barrier layer 900 and drain 5002The same reason can be designed to be very small and is not described in detail. Example H1And H2Preferably 0.1
~0.5
。
As shown in fig. 6a, in the first gap H1During dry etching, the edge of the corresponding non-photoresist region close to the barrier layer 900 coincides with the edge projection of the first photoresist portion 410a close to the source 600, and the edge of the corresponding non-photoresist region close to the source 600 coincides with the edge projection of the first semiconductor portion 410 close to the source 600, so that the minimum first gap H can be ensured1Meanwhile, the barrier layer 900 and the source electrode 600 are completely disconnected, and the phenomenon that the barrier layer 900 and the source electrode 600 are short-circuited due to incomplete etching to cause device damage is avoided. In the same way, in the second gap H2During dry etching, the edge of the corresponding non-photoresist region close to the barrier layer 900 coincides with the edge projection of the first photoresist portion 410a close to the drain 500, one edge of the boundary coincides with the edge projection of the first photoresist portion 410a close to the drain, and the boundary of the non-photoresist region coincides with the edge of the first semiconductor portion close to the drain. With continued reference to fig. 1 to 5b, in step S103, patterning the semiconductor layer by a photolithography process to form a first semiconductor portion and a second semiconductor portion separated by a first gap includes:
s201, coating a photoresist on the semiconductor layer 400.
And S202, exposing and developing the photoresist through a half-tone mask plate to form a photoresist layer pattern.
The halftone mask is a second mask 400b, the photoresist layer pattern includes a photoresist-free region, a half-photoresist region and a full-photoresist region 480, the photoresist-free region includes a first photoresist-free region 461 and a second photoresist-free region 462, and the first photoresist-free region 461 and the second photoresist-free region 462 respectively correspond to the second interval 440 and the first interval 430; the half-photoresist region includes a first half-photoresist region 471, a second half-photoresist region 472, and a third half-photoresist region 473; the first half photoresist region 471 and the second half photoresist region 472 are respectively located at two sides of the full photoresist region 480, the first half photoresist region 471 is located between the first non-photoresist region 461 and the full photoresist region 780, the second half photoresist region 472 is located between the second non-photoresist region 462 and the full photoresist region 480, and the second non-photoresist region 462 is located between the second half photoresist region 472 and the third half photoresist region 473. The first half photoresist region 471, the second half photoresist region 472, and the all-photoresist region 480 form a first photoresist portion 410a, and the third half photoresist region 473 forms a second photoresist portion 420 a.
The full photoresist region 480 corresponds to the active layer region, the first half photoresist region 471 corresponds to a contact of the source electrode 600, the second half photoresist region 472 corresponds to a contact of the drain electrode 500, and the third half photoresist region 473 corresponds to a pattern of the pixel electrode 700.
S203, etching the semiconductor layer 400 with the photoresist layer pattern as a protection, so that the semiconductor layer 400 forms a first semiconductor portion 410 and a second semiconductor portion 420.
With continued reference to fig. 4 a-5 b, in some embodiments, ashing the first and second photoresist portions 410a and 420a includes:
s301, ashing the photoresist layer pattern to remove the half photoresist region and thin the full photoresist region 480, and removing the first half photoresist region 471 and the second half photoresist region 472, thereby exposing both sides of the first semiconductor portion 410 and the second semiconductor portion 420.
S302, performing plasma treatment on the exposed first semiconductor portion 410 to form contacts 450 for connecting to the source 600 and the drain 500 on two sides of the first semiconductor portion 410, respectively; the exposed second semiconductor part 420 is plasma-treated to form the pixel electrode 700.
Specifically, during the plasma treatment, the first semiconductor portion 410 corresponding to the first half photoresist region 471 and the second half photoresist region 472 is made conductive, and then the contact 450 for connecting the source 600 and the drain 500 is formed. The second semiconductor portion 420 corresponding to the third half photoresist region 473 is rendered conductive to form the pixel electrode 700. The above-mentioned conductor forming treatment may be performed by a plasma treatment using hydrogen plasma or argon plasma, or a conductor forming process known to those skilled in the art, and the present embodiment is not limited thereto.
According to the manufacturing method of the array substrate, the source and drain metal is directly used as the blocking layer 900, extra photomask and light blocking layer materials are not needed, and product stability and quality are improved. The first photoresist portion 410a is used as a spacer for the light blocking layer, and serves to correspondingly isolate the source electrode 600, the drain electrode 500, and the light blocking layer 900 without increasing processes. And the halftone process of the first photoresist portion 410a is not added with an additional mask, so that the production cost is reduced.
Referring to fig. 9 to 11, in one possible embodiment, after the deposition of the same material barrier layer 900, the source electrode 600 and the drain electrode 500 on the first photoresist portion 410a, the first spacer 430 and a portion of the second spacer 440, the method further includes: a planarization layer 1000 is formed on the barrier layer 900, the source electrode 600, the drain electrode 500, the pixel electrode 700, and a portion of the second spacer 440.
The planarization layer 1000 may protect the barrier layer 900, the source electrode 600, the drain electrode 500, the pixel electrode 700, and a portion of the second spacer 440, and may ensure stable operation of the thin film transistor. Also, the planarization layer 1000 generally has a flat surface, so the planarization layer 1000 can improve the flatness of the array substrate.
Specifically, the planarization layer 1000 may be deposited by a plasma enhanced chemical vapor deposition method, and the material for forming the planarization layer 100 may be an oxide, a nitride, or an oxynitride.
Meanwhile, the array substrate is prepared by three photomasks, so that the manufacturing process is saved, the production efficiency is greatly improved, and the production cost is reduced.
Example two
Referring to fig. 9 to 11, an embodiment of the present application further provides an array substrate, and the array substrate is manufactured by the manufacturing method of the array substrate provided in the first embodiment. The array substrate includes a substrate 100, a gate electrode 20 disposed on the substrate 100, a source electrode 600, a drain electrode 500, a first semiconductor portion 410, and a pixel electrode layer 700 so as to cover the substrate 100 and the gate electrode 200.
The first semiconductor portion 410 is sequentially provided with a first photoresist portion 410a and a barrier layer 900; the barrier layer 900, the source electrode 600 and the drain electrode 500 are disposed on the same layer and have the same material, the barrier layer 900, the source electrode 600 and the drain electrode 500 are disconnected from each other, the source electrode 600 and the drain electrode 500 are respectively in contact with two opposite sides of the first semiconductor portion 410, and the drain electrode 500 is also in contact with the pixel electrode 700. Wherein the first gap H1A second gap H corresponding to the first side edge of the ashed first photoresist portion 410a2Corresponding to the second side edge of the ashed first photoresist portion 410 a.
According to the array substrate provided by the application, the barrier layer 900 is supported by the first photoresist portion 410a to form a state of being disconnected from the source 600 and the drain 500 and suspended, and not communicated with other circuits, the first semiconductor portion 410 is shielded by the source 600, the drain 500 and the barrier layer 900, backlight or natural light is prevented from irradiating a thin film transistor channel layer, and the stability of the thin film transistor is improved. Meanwhile, the source electrode 600, the drain electrode 500 and the barrier layer 900 are formed by the same material on the same layer, so that the manufacturing process of the barrier layer 900 is simplified, and the manufacturing cost of the thin film transistor is reduced.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. The manufacturing method of the array substrate is characterized by comprising the following steps:
forming a gate electrode on a substrate;
sequentially forming a grid electrode insulating layer and a semiconductor layer on the substrate and the grid electrode;
patterning the semiconductor layer through a half-tone lithography process to form a first semiconductor part and a second semiconductor part which are separated by a first interval, wherein one side, which is far away from the first interval, of the first semiconductor part is provided with a second interval, the first semiconductor part is provided with a first photoresist part, and the second semiconductor part is provided with a second photoresist part;
ashing the first and second photoresist portions to expose both sides of a first semiconductor portion and the second semiconductor portion, making the exposed first semiconductor portion conductive so that contacts for connection to a source and a drain are formed on both sides of the first semiconductor portion, respectively, and making the exposed second semiconductor portion conductive so that a pixel electrode is formed;
depositing a metal layer on the first photoresist portion, the first space, the second space and the pixel electrode, coating photoresist on the metal layer, exposing and developing by using a mask to form photoresist corresponding to the patterns of a barrier layer, the source electrode and the drain electrode, then etching to form the barrier layer, the source electrode and the drain electrode, and then washing away the photoresist, wherein the barrier layer, the source electrode and the drain electrode are disconnected with each other, the source electrode and the drain electrode are respectively contacted with two opposite sides of the first semiconductor portion, the drain electrode is also contacted with the pixel electrode, the barrier layer is positioned above the semiconductor layer, and the first photoresist portion is positioned between the barrier layer and the first semiconductor portion;
a first gap is formed between the source electrode adjacent to the first side of the blocking layer and the first side of the blocking layer, a second gap is formed between the drain electrode adjacent to the second side of the blocking layer and the second side of the blocking layer, the first gap corresponds to the first side edge of the first photoresist portion after ashing, and the second gap corresponds to the second side edge of the first photoresist portion after ashing.
2. The method for manufacturing the array substrate according to claim 1, wherein the forming a barrier layer, a drain electrode and a source electrode on the first photoresist portion, the first spacers and a portion of the second spacers by a photolithography process comprises:
depositing a metal layer on the first photoresist portion, the first space, the second space, and the pixel electrode;
and coating photoresist on the metal layer, carrying out exposure and development by adopting a half-tone mask to form photoresist corresponding to the patterns of the barrier layer, the source electrode and the drain electrode, then carrying out dry etching to form the barrier layer, the source electrode and the drain electrode, and then washing away the photoresist.
3. The method of claim 1, wherein the patterning the semiconductor layer by a photolithography process to form the first and second semiconductor portions separated by the first space comprises:
coating photoresist on the semiconductor layer;
exposing and developing the photoresist through a half-tone mask to form a photoresist layer pattern; the photoresist layer pattern comprises a non-photoresist area, a semi-photoresist area and a full-photoresist area, wherein the full-photoresist area corresponds to the active layer area, and the semi-photoresist area comprises a first semi-photoresist area, a second semi-photoresist area and a third semi-photoresist area; the first half photoresist area and the second half photoresist area are respectively positioned at two sides of the all photoresist area and respectively correspond to a contact of a source electrode and a contact of a drain electrode, and the third half photoresist area corresponds to the pattern of the pixel electrode;
the first half photoresist area, the second half photoresist area and the full photoresist area form the first photoresist part, and the third half photoresist area forms the second photoresist part;
and etching the semiconductor layer by taking the photoresist layer pattern as protection so as to enable the semiconductor layer to form the first semiconductor part and the second semiconductor part.
4. The method for manufacturing the array substrate according to claim 3, wherein the ashing the first photoresist portion comprises:
and ashing the photoresist layer pattern to thin the full photoresist region, and removing the first half photoresist region and the second half photoresist region, thereby exposing two sides of the first semiconductor portion.
5. The method for manufacturing the array substrate according to claim 4, wherein the step of making the exposed first semiconductor portion into a conductor so that contacts for connecting with a source electrode and a drain electrode are formed on both sides of the first semiconductor portion comprises:
and carrying out plasma treatment on the exposed first semiconductor part, so that contacts for connecting with a source electrode and a drain electrode are formed on two sides of the first semiconductor part respectively.
6. The method for manufacturing the array substrate according to claim 3, wherein the ashing the second photoresist portion comprises:
and ashing the photoresist layer pattern to remove the third half photoresist region, thereby exposing the second semiconductor portion.
7. The method for manufacturing the array substrate according to claim 6, wherein the conducting the exposed second semiconductor portion to form a pixel electrode comprises:
and carrying out plasma treatment on the exposed second semiconductor part to form a pixel electrode.
8. An array substrate, comprising a substrate, a gate electrode disposed on the substrate, a source electrode, a drain electrode, a first semiconductor portion and a pixel electrode layer which are disposed so as to cover the substrate and the gate electrode;
the first semiconductor part is sequentially provided with a first photoresist part and a barrier layer; the barrier layer, the source electrode and the drain electrode are arranged on the same layer and are made of the same material, the barrier layer, the source electrode and the drain electrode are mutually disconnected, a first gap is formed between the source electrode adjacent to the first side of the barrier layer and the first side of the barrier layer, a second gap is formed between the drain electrode adjacent to the second side of the barrier layer and the second side of the barrier layer, the first gap corresponds to the first side edge of the ashed first photoresist portion, the second gap corresponds to the second side edge of the ashed first photoresist portion, the source electrode and the drain electrode are respectively contacted with two sides of the first semiconductor portion, and the drain electrode is also contacted with the pixel electrode.
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