KR20080035045A - Method for manufacturing display substrate - Google Patents

Abstract

A method for fabricating a display substrate is provided to prevent etch gas used in a subsequent dry etch process from coming in contact with the etch surface of a second metal pattern by reflowing a photoresist pattern after a second metal pattern is formed during a process for fabricating a display substrate by using four masks. A first metal pattern includes a gate interconnection and a gate electrode(120) of a TFT. A gate insulation layer(130), an active layer(140), a metal layer and a first photoresist pattern are sequentially formed on the resultant structure. The metal layer is etched to be the same shape as the first photoresist pattern so that a second metal pattern including a data interconnection is formed. The first photoresist pattern is reflowed to form a second photoresist pattern covering the etch surface of the second metal pattern. The active layer is etched by using the second photoresist pattern. A predetermined thickness of the second photoresist pattern is etched to expose a part of the second metal pattern. The exposed second metal pattern is etched to form a source/drain electrode of the TFT. A pixel electrode is electrically connected to the drain electrode. A passivation layer can be formed between the second metal pattern and the pixel electrode.

Description

Manufacturing method of display substrate {METHOD FOR MANUFACTURING DISPLAY SUBSTRATE}

1 is a plan view of a display substrate manufactured by a method of manufacturing a display substrate according to an exemplary embodiment of the present invention.

2 to 11 are process diagrams illustrating a method of manufacturing a display substrate according to an exemplary embodiment of the present invention using a cross section taken along the line II ′ of FIG. 1.

<Description of the symbols for the main parts of the drawings>

100: display substrate 110: base substrate

120: gate electrode 130: gate insulating layer

140: active layer 140a: semiconductor layer

140b: ohmic contact layer 150: second metal layer

152: electrode pattern 154: source electrode

156: drain electrode 160: passivation layer

162 contact hole 170 pixel electrode

The present invention relates to a method of manufacturing a display substrate, and more particularly, to a method of manufacturing a display substrate for reducing defects.

In general, a plurality of gate lines parallel to each other and a plurality of source lines insulated from and intersecting with the gate lines are formed on the display substrate, and a pixel is formed in each area surrounded by the gate lines and the data lines. Each pixel is provided with a pixel electrode and a switching element for applying a pixel voltage to the pixel electrode.

The gate lines, the data lines, and the switching elements are formed through a photolithography process using an exposure mask. Since the exposure mask occupies a large portion of the manufacturing cost, a four-sheet mask process has recently been developed to reduce manufacturing costs and manufacturing processes.

In the four mask process, the semiconductor layer, the ohmic contact layer, and the metal layer are sequentially applied on the base substrate on which the gate metal pattern including the gate wiring is formed, and the metal layer is patterned by a wet etching process to form a source metal pattern including the source wiring. do. Subsequently, the ohmic contact layer and the semiconductor layer are dry-etched using the source metal pattern as an etch mask to form an active layer patterned in the same manner as the source metal pattern. In this case, an etching process for forming the active layer is mainly performed by a dry etching method using an etching gas.

In the dry etching process, the etching surface of the source metal pattern is exposed to the etching gas. Therefore, when the metal material constituting the source metal pattern has poor chemical resistance and good surface oxidation, the metal material constituting the source metal pattern and the etching gas may react to form reaction byproducts. The reaction by-products formed in this way may penetrate into the active layer in a subsequent process to cause poor characteristics of the switching device, and may be adsorbed on an etching surface to increase wiring resistance and wiring defects.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to manufacture a display substrate which can prevent corrosion of the source metal pattern by preventing exposure of the etch surface of the source metal pattern during a dry etching process. To provide a way.

According to an aspect of the present invention, there is provided a method of manufacturing a display substrate, including forming a first metal pattern including a gate wiring and a gate electrode of a thin film transistor, and forming the substrate on which the first metal pattern is formed. Sequentially forming a gate insulating layer, an active layer, a metal layer, and a first photoresist pattern on the substrate; and etching the metal layer in the same shape as the first photoresist pattern to form a second metal pattern including data lines. Forming a second photoresist pattern covering the etched surface of the second metal pattern by reflowing the first photoresist pattern; and etching the active layer using the second photoresist pattern Exposing a portion of the second metal pattern by etching the second photoresist pattern by a predetermined thickness; Etching the second metal pattern to form a source electrode and a drain electrode of the thin film transistor; and forming a pixel electrode electrically connected to the drain electrode.

According to the method of manufacturing the display substrate, the photoresist pattern may be reflowed to prevent the etching gas used in the etching process of the active layer and the etching surface of the second metal pattern from contacting each other.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a plan view of a display substrate manufactured by a method of manufacturing a display substrate according to an exemplary embodiment of the present invention.

2 to 11 are process diagrams illustrating a method of manufacturing a display substrate according to an exemplary embodiment of the present invention using a cross section taken along the line II ′ of FIG. 1.

1 and 2, a first metal layer (not shown) is formed on the base substrate 110. The first metal layer (not shown) may be formed of, for example, a metal such as chromium, aluminum, tantalum, molybdenum, titanium, tungsten, copper, silver, or an alloy thereof, or two or more layers having different physical properties. It can be formed as. The first metal layer (not shown) is deposited by a sputtering process.

Subsequently, a photoresist film (not shown) is coated on the first metal layer, and the photoresist film is patterned by photolithography using a first mask MASK 1 to form a first photoresist pattern PR1. .

Next, a first metal layer (not shown) is patterned by an etching process using the first photoresist pattern PR1 to include a gate electrode GL and a gate electrode 120 of the thin film transistor TFT. A metal pattern is formed.

The gate line GL extends in the first direction on the base substrate 110, and the gate electrode 120 protrudes from the gate line GL.

Although not shown, the first metal pattern may further include a storage common line extending in the first direction between the gate lines GL.

When the etching process for forming the first metal pattern is completed, the first photoresist pattern PR1 is removed using a strip solution.

Referring to FIG. 3, a silicon nitride (SiNx) or silicon oxide (SiOx) series is formed on a base substrate 110 on which the first metal pattern is formed by using a plasma enhanced chemical vapor deposition (PECVD) method. A gate insulating layer 130 made of a material, an active layer 140a made of amorphous silicon (a-Si: H), and an ohmic contact layer 140b doped with high concentration of n + ions are sequentially stacked.

Subsequently, a second metal layer 150 is formed on the ohmic contact layer 140b. The second metal layer 150 may be formed of, for example, a metal such as chromium, aluminum, tantalum, molybdenum, titanium, tungsten, copper, silver, or an alloy thereof, or two or more layers having different physical properties. Can be formed. Preferably, the second metal layer 150 is formed of copper or a copper alloy and may be deposited by a sputtering process.

Next, a photoresist film PL is coated on the entire surface of the second metal layer 150. The photoresist film PL is formed of, for example, a positive photoresist in which the exposed region is dissolved by a developer. Subsequently, a soft baking process for evaporating the solvent component in the photoresist film PL is performed. The soft bake process is carried out in such a manner that the temperature treatment, for example, 120 to 130 degrees for 50 to 60 seconds.

3 and 4, the photoresist film PL is patterned by performing a photolithography process using a second mask MASK 2.

In detail, the second mask MASK2 includes an opening 2, a light blocking part 4, and a transflective part 6. When the amount of light exposed at the opening 2 is called the first light amount, the second transmissive portion 6 exposes a second light amount corresponding to about half of the first light amount. Light is blocked in the light shielding portion 4.

After the exposure process using the second mask MASK2 is finished, a post exposure bake is performed in a general photographic process. However, in the present embodiment, the exposure is performed to facilitate the reflow process described below with reference to FIG. 6. It is preferable to omit the post-baking process.

Subsequently, when the photoresist film PL exposed by the second mask MASK2 is developed with a developer, all of the photoresist film PL corresponding to the opening 2 is removed by the developer.

The photoresist film PL corresponding to the light blocking portion 4 forms a first thickness portion d1 having the same thickness as before development.

The photoresist film PL corresponding to the transflective portion 6 forms a second thickness portion d2 corresponding to about half the thickness of the first thickness portion d1. Accordingly, the second photoresist pattern PR2 including the first thickness part d1 and the second thickness part d2 is formed on the second metal layer 150.

Next, a post bake process is performed on the second photoresist pattern PR2 to remove the solvent and water remaining in the developed second photoresist pattern PR2 and to stabilize the image of the pattern. . The post bake process is preferably carried out at a temperature of about 120 degrees.

1, 4, and 5, the second metal layer 150 is first wet-etched using the second photoresist pattern PR2. Accordingly, a second metal pattern including the electrode pattern 152 and the source wiring DL is formed on the base substrate 110.

In this case, since the second metal layer 150 is etched isotropically by an etchant, an under cutting is performed in which the electrode pattern 152 and the source wiring DL are embedded in a side surface of the second photoresist pattern PR2. ) May occur. In the undercutting portion U, an etching surface of the electrode pattern 152 and the source wiring DL is exposed.

On the other hand, the source wiring DL extends in a second direction crossing the first direction. Therefore, the pixel portion P is defined on the base substrate 110 by the gate lines GL extending in the first direction and the source lines DL extending in the second direction.

The electrode pattern 152 is connected from the source wiring DL and is formed to overlap a predetermined region with the gate electrode 120. The electrode pattern 152 is a pattern for forming the source electrode 154 and the drain electrode 156 of the switching element TFT, and the source electrode 154 and the drain electrode 156 are connected to each other without being spaced apart from each other. Has

 Referring to FIG. 6, the second photoresist pattern is baked at a specific temperature to impart fluidity to the second photoresist pattern PR2. Accordingly, a reflow occurs in which the second photoresist pattern PR2 flows along the etching surface of the second metal pattern, so that the second photoresist pattern PR2 is an etching surface of the second metal pattern. To cover.

Specifically, in order to generate a reflow of the second photoresist pattern PR2, a substrate on which the second photoresist pattern PR2 is formed is disposed in a baking oven, and the second photo is heated at a temperature of 130 degrees to 150 degrees. The resist pattern PR2 is heat-treated.

That is, in the present invention, a hard bake process, which proceeds to a temperature of about 130 degrees after the formation of the photoresist pattern in a general photolithography, is omitted, and a temperature of 130 degrees or more that may cause reflow of the photoresist pattern. Heat treatment with

Reflow of the photoresist pattern is hard to occur at a temperature of 130 degrees or less, and hardening of the photoresist pattern becomes more severe at a temperature of 150 degrees or more, and thus heat treatment is performed at a temperature of 130 to 150 degrees.

Referring to FIG. 7, the ohmic contact layer 140b and the semiconductor layer 140a are sequentially etched using the reflowed second photoresist pattern PR2. Etching of the ohmic contact layer 140b and the semiconductor layer 140a is performed by a dry etching process. Accordingly, an active layer 140 having a structure in which the semiconductor layer 140a and the ohmic contact layer 140b are stacked is formed under the second metal pattern in the same manner as the second metal pattern.

 Meanwhile, according to the exemplary embodiment of the present invention, since the reflowed second photoresist pattern PR2 covers the etching surface of the second metal pattern, the ohmic contact layer 140b and the semiconductor layer 140a may be etched. The etching gases used are prevented from contacting the etching surface.

Accordingly, since surface oxidation of the second metal pattern and reaction by-products due to chemical reaction between the second metal pattern and the etching gas may be prevented, poor wiring and wiring resistance may be reduced.

Referring to FIG. 8, an ashing process of removing a predetermined thickness of the reflowed second photoresist pattern PR2 using an oxygen plasma is performed.

Accordingly, referring to FIGS. 4 and 8, the second thickness portion d2 formed to about half the thickness of the first thickness portion d1 is removed and the first thickness portion d1 remains at a predetermined thickness. do. The electrode pattern 152 is exposed in a region where the second thickness part d2 is removed.

Subsequently, a second wet etching process of etching the exposed portion of the electrode pattern 152 is performed using the remaining second photoresist pattern PR2.

Accordingly, referring to FIGS. 1 and 9, a source electrode 154 protruding from the source wiring DL and a drain electrode 156 spaced a predetermined distance from the source electrode 154 are formed.

The source electrode 154 and the drain electrode 156 overlap the gate electrode 120 at a predetermined interval. The ohmic contact layer 140b of the active layer 140 is exposed at the spaced portion between the source electrode 154 and the drain electrode 156.

Subsequently, the ohmic contact layer 140b exposed from the gap between the source electrode 154 and the drain electrode 156 is etched. The etching of the ohmic contact layer 140b is performed by dry etching, for example.

Accordingly, the thin film transistor TFT including the gate electrode 120, the active layer 140, the source electrode 154, and the drain electrode 156 is formed on the base substrate 110.

The second photoresist pattern PR2 remaining on the thin film transistor may be removed by a strip process using a strip solution.

Meanwhile, according to the exemplary embodiment of the present invention, the second metal pattern is prevented from contacting the etching gas and the second metal pattern provided during the dry etching process of forming the active layer 140 by reflowing the second photoresist pattern PR2. Reaction byproducts of the etching gas may be prevented from penetrating into the active layer 140. Accordingly, driving reliability of the thin film transistor TFT may be improved.

Referring to FIG. 10, a passivation layer 160 is formed on the gate insulating layer 130 on which the thin film transistor TFT is formed. The passivation layer 160 may be formed of a silicon nitride or silicon oxide-based material in the same manner as the gate insulating layer 130, and may be formed using a plasma chemical vapor deposition method.

Subsequently, a third photoresist pattern PR3 is formed on the passivation layer 160 by a photolithography process using a third mask MASK 3, followed by an etching process using the third photoresist pattern PR3. The passivation layer 160 is patterned to form a contact hole 162 exposing one end of the drain electrode 156.

When the etching process for forming the contact hole 162 is finished, the third photoresist pattern PR3 is removed with a strip solution.

1 and 11, a transparent conductive material is coated on the passivation layer 162 on which the contact hole 162 is formed. The transparent conductive material is made of, for example, indium tin oxide or indium zinc oxide. Subsequently, a fourth photoresist pattern PR4 is formed on the transparent conductive material by a photolithography process using a fourth mask MASK 4.

Next, the transparent conductive material (not shown) is patterned by an etching process using the fourth photoresist pattern PR4. Accordingly, the pixel electrode 170 is formed to be in electrical contact with the drain electrode 156 through the contact hole 162.

Subsequently, a strip process is performed to remove the fourth photoresist pattern PR4 remaining on the pixel electrode 170. Accordingly, the display substrate 100 according to the exemplary embodiment of the present invention is completed.

As described above, according to the present invention, the etching of the etching gas and the second metal pattern used in the subsequent dry etching process by reflowing the photoresist pattern after forming the second metal pattern during the manufacturing process of the display substrate using the four masks. Surface contact can be prevented. Accordingly, since corrosion of the second metal pattern and generation of reaction by-products are suppressed, defects in the wiring and the thin film transistor may be reduced, thereby improving reliability of the display substrate.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (8)

Forming a first metal pattern including a gate wiring and a gate electrode of the thin film transistor; Sequentially forming a gate insulating layer, an active layer, a metal layer, and a first photoresist pattern on the substrate on which the first metal pattern is formed; Etching the metal layer in the same shape as the first photoresist pattern to form a second metal pattern including data lines; Reflowing the first photoresist pattern to form a second photoresist pattern covering an etched surface of the second metal pattern; Etching the active layer using the second photoresist pattern; Etching the second photoresist pattern to a predetermined thickness to expose a portion of the second metal pattern; Etching the exposed second metal pattern to form a source electrode and a drain electrode of the thin film transistor; And Forming a pixel electrode electrically connected to the drain electrode. The method of claim 1, wherein the metal layer comprises copper. The method of claim 1, wherein the covering of the etching surface of the second metal pattern comprises heat-treating the first photoresist pattern at a temperature of 130 to 150 degrees. The method of claim 1, wherein the active layer has a stacked structure of a semiconductor layer and an ohmic contact layer. The method of claim 4, further comprising etching the ohmic contact layer exposed between the source electrode and the drain electrode. The method of claim 1, further comprising forming a passivation layer between the second metal pattern and the pixel electrode. The method of claim 1, wherein the forming of the second metal pattern is performed by a wet etching process. The method of claim 1, wherein the etching of the active layer is performed by a dry etching process.

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